Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /** |
| 2 | * @file nmi_int.c |
| 3 | * |
| 4 | * @remark Copyright 2002 OProfile authors |
| 5 | * @remark Read the file COPYING |
| 6 | * |
| 7 | * @author John Levon <levon@movementarian.org> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/init.h> |
| 11 | #include <linux/notifier.h> |
| 12 | #include <linux/smp.h> |
| 13 | #include <linux/oprofile.h> |
| 14 | #include <linux/sysdev.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <asm/nmi.h> |
| 17 | #include <asm/msr.h> |
| 18 | #include <asm/apic.h> |
| 19 | |
| 20 | #include "op_counter.h" |
| 21 | #include "op_x86_model.h" |
| 22 | |
| 23 | static struct op_x86_model_spec const * model; |
| 24 | static struct op_msrs cpu_msrs[NR_CPUS]; |
| 25 | static unsigned long saved_lvtpc[NR_CPUS]; |
| 26 | |
| 27 | static int nmi_start(void); |
| 28 | static void nmi_stop(void); |
| 29 | |
| 30 | /* 0 == registered but off, 1 == registered and on */ |
| 31 | static int nmi_enabled = 0; |
| 32 | |
| 33 | #ifdef CONFIG_PM |
| 34 | |
Pavel Machek | 438510f | 2005-04-16 15:25:24 -0700 | [diff] [blame] | 35 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | { |
| 37 | if (nmi_enabled == 1) |
| 38 | nmi_stop(); |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | |
| 43 | static int nmi_resume(struct sys_device *dev) |
| 44 | { |
| 45 | if (nmi_enabled == 1) |
| 46 | nmi_start(); |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | |
| 51 | static struct sysdev_class oprofile_sysclass = { |
| 52 | set_kset_name("oprofile"), |
| 53 | .resume = nmi_resume, |
| 54 | .suspend = nmi_suspend, |
| 55 | }; |
| 56 | |
| 57 | |
| 58 | static struct sys_device device_oprofile = { |
| 59 | .id = 0, |
| 60 | .cls = &oprofile_sysclass, |
| 61 | }; |
| 62 | |
| 63 | |
| 64 | static int __init init_driverfs(void) |
| 65 | { |
| 66 | int error; |
| 67 | if (!(error = sysdev_class_register(&oprofile_sysclass))) |
| 68 | error = sysdev_register(&device_oprofile); |
| 69 | return error; |
| 70 | } |
| 71 | |
| 72 | |
| 73 | static void exit_driverfs(void) |
| 74 | { |
| 75 | sysdev_unregister(&device_oprofile); |
| 76 | sysdev_class_unregister(&oprofile_sysclass); |
| 77 | } |
| 78 | |
| 79 | #else |
| 80 | #define init_driverfs() do { } while (0) |
| 81 | #define exit_driverfs() do { } while (0) |
| 82 | #endif /* CONFIG_PM */ |
| 83 | |
| 84 | |
| 85 | static int nmi_callback(struct pt_regs * regs, int cpu) |
| 86 | { |
| 87 | return model->check_ctrs(regs, &cpu_msrs[cpu]); |
| 88 | } |
| 89 | |
| 90 | |
| 91 | static void nmi_cpu_save_registers(struct op_msrs * msrs) |
| 92 | { |
| 93 | unsigned int const nr_ctrs = model->num_counters; |
| 94 | unsigned int const nr_ctrls = model->num_controls; |
| 95 | struct op_msr * counters = msrs->counters; |
| 96 | struct op_msr * controls = msrs->controls; |
| 97 | unsigned int i; |
| 98 | |
| 99 | for (i = 0; i < nr_ctrs; ++i) { |
| 100 | rdmsr(counters[i].addr, |
| 101 | counters[i].saved.low, |
| 102 | counters[i].saved.high); |
| 103 | } |
| 104 | |
| 105 | for (i = 0; i < nr_ctrls; ++i) { |
| 106 | rdmsr(controls[i].addr, |
| 107 | controls[i].saved.low, |
| 108 | controls[i].saved.high); |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | |
| 113 | static void nmi_save_registers(void * dummy) |
| 114 | { |
| 115 | int cpu = smp_processor_id(); |
| 116 | struct op_msrs * msrs = &cpu_msrs[cpu]; |
| 117 | model->fill_in_addresses(msrs); |
| 118 | nmi_cpu_save_registers(msrs); |
| 119 | } |
| 120 | |
| 121 | |
| 122 | static void free_msrs(void) |
| 123 | { |
| 124 | int i; |
KAMEZAWA Hiroyuki | c8912599 | 2006-03-28 01:56:39 -0800 | [diff] [blame] | 125 | for_each_possible_cpu(i) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | kfree(cpu_msrs[i].counters); |
| 127 | cpu_msrs[i].counters = NULL; |
| 128 | kfree(cpu_msrs[i].controls); |
| 129 | cpu_msrs[i].controls = NULL; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | |
| 134 | static int allocate_msrs(void) |
| 135 | { |
| 136 | int success = 1; |
| 137 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
| 138 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; |
| 139 | |
| 140 | int i; |
Andrew Morton | 394e390 | 2006-03-23 03:01:05 -0800 | [diff] [blame] | 141 | for_each_online_cpu(i) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL); |
| 143 | if (!cpu_msrs[i].counters) { |
| 144 | success = 0; |
| 145 | break; |
| 146 | } |
| 147 | cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL); |
| 148 | if (!cpu_msrs[i].controls) { |
| 149 | success = 0; |
| 150 | break; |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | if (!success) |
| 155 | free_msrs(); |
| 156 | |
| 157 | return success; |
| 158 | } |
| 159 | |
| 160 | |
| 161 | static void nmi_cpu_setup(void * dummy) |
| 162 | { |
| 163 | int cpu = smp_processor_id(); |
| 164 | struct op_msrs * msrs = &cpu_msrs[cpu]; |
| 165 | spin_lock(&oprofilefs_lock); |
| 166 | model->setup_ctrs(msrs); |
| 167 | spin_unlock(&oprofilefs_lock); |
| 168 | saved_lvtpc[cpu] = apic_read(APIC_LVTPC); |
| 169 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 170 | } |
| 171 | |
| 172 | |
| 173 | static int nmi_setup(void) |
| 174 | { |
| 175 | if (!allocate_msrs()) |
| 176 | return -ENOMEM; |
| 177 | |
| 178 | /* We walk a thin line between law and rape here. |
| 179 | * We need to be careful to install our NMI handler |
| 180 | * without actually triggering any NMIs as this will |
| 181 | * break the core code horrifically. |
| 182 | */ |
| 183 | if (reserve_lapic_nmi() < 0) { |
| 184 | free_msrs(); |
| 185 | return -EBUSY; |
| 186 | } |
| 187 | /* We need to serialize save and setup for HT because the subset |
| 188 | * of msrs are distinct for save and setup operations |
| 189 | */ |
| 190 | on_each_cpu(nmi_save_registers, NULL, 0, 1); |
| 191 | on_each_cpu(nmi_cpu_setup, NULL, 0, 1); |
| 192 | set_nmi_callback(nmi_callback); |
| 193 | nmi_enabled = 1; |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | |
| 198 | static void nmi_restore_registers(struct op_msrs * msrs) |
| 199 | { |
| 200 | unsigned int const nr_ctrs = model->num_counters; |
| 201 | unsigned int const nr_ctrls = model->num_controls; |
| 202 | struct op_msr * counters = msrs->counters; |
| 203 | struct op_msr * controls = msrs->controls; |
| 204 | unsigned int i; |
| 205 | |
| 206 | for (i = 0; i < nr_ctrls; ++i) { |
| 207 | wrmsr(controls[i].addr, |
| 208 | controls[i].saved.low, |
| 209 | controls[i].saved.high); |
| 210 | } |
| 211 | |
| 212 | for (i = 0; i < nr_ctrs; ++i) { |
| 213 | wrmsr(counters[i].addr, |
| 214 | counters[i].saved.low, |
| 215 | counters[i].saved.high); |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | |
| 220 | static void nmi_cpu_shutdown(void * dummy) |
| 221 | { |
| 222 | unsigned int v; |
| 223 | int cpu = smp_processor_id(); |
| 224 | struct op_msrs * msrs = &cpu_msrs[cpu]; |
| 225 | |
| 226 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
| 227 | * mode and vector nr combination can be illegal. That's by design: on |
| 228 | * power on apic lvt contain a zero vector nr which are legal only for |
| 229 | * NMI delivery mode. So inhibit apic err before restoring lvtpc |
| 230 | */ |
| 231 | v = apic_read(APIC_LVTERR); |
| 232 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
| 233 | apic_write(APIC_LVTPC, saved_lvtpc[cpu]); |
| 234 | apic_write(APIC_LVTERR, v); |
| 235 | nmi_restore_registers(msrs); |
| 236 | } |
| 237 | |
| 238 | |
| 239 | static void nmi_shutdown(void) |
| 240 | { |
| 241 | nmi_enabled = 0; |
| 242 | on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1); |
| 243 | unset_nmi_callback(); |
| 244 | release_lapic_nmi(); |
| 245 | free_msrs(); |
| 246 | } |
| 247 | |
| 248 | |
| 249 | static void nmi_cpu_start(void * dummy) |
| 250 | { |
| 251 | struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()]; |
| 252 | model->start(msrs); |
| 253 | } |
| 254 | |
| 255 | |
| 256 | static int nmi_start(void) |
| 257 | { |
| 258 | on_each_cpu(nmi_cpu_start, NULL, 0, 1); |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | |
| 263 | static void nmi_cpu_stop(void * dummy) |
| 264 | { |
| 265 | struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()]; |
| 266 | model->stop(msrs); |
| 267 | } |
| 268 | |
| 269 | |
| 270 | static void nmi_stop(void) |
| 271 | { |
| 272 | on_each_cpu(nmi_cpu_stop, NULL, 0, 1); |
| 273 | } |
| 274 | |
| 275 | |
| 276 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
| 277 | |
| 278 | static int nmi_create_files(struct super_block * sb, struct dentry * root) |
| 279 | { |
| 280 | unsigned int i; |
| 281 | |
| 282 | for (i = 0; i < model->num_counters; ++i) { |
| 283 | struct dentry * dir; |
| 284 | char buf[2]; |
| 285 | |
| 286 | snprintf(buf, 2, "%d", i); |
| 287 | dir = oprofilefs_mkdir(sb, root, buf); |
| 288 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
| 289 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); |
| 290 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); |
| 291 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); |
| 292 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); |
| 293 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); |
| 294 | } |
| 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | |
| 300 | static int __init p4_init(char ** cpu_type) |
| 301 | { |
| 302 | __u8 cpu_model = boot_cpu_data.x86_model; |
| 303 | |
| 304 | if (cpu_model > 4) |
| 305 | return 0; |
| 306 | |
| 307 | #ifndef CONFIG_SMP |
| 308 | *cpu_type = "i386/p4"; |
| 309 | model = &op_p4_spec; |
| 310 | return 1; |
| 311 | #else |
| 312 | switch (smp_num_siblings) { |
| 313 | case 1: |
| 314 | *cpu_type = "i386/p4"; |
| 315 | model = &op_p4_spec; |
| 316 | return 1; |
| 317 | |
| 318 | case 2: |
| 319 | *cpu_type = "i386/p4-ht"; |
| 320 | model = &op_p4_ht2_spec; |
| 321 | return 1; |
| 322 | } |
| 323 | #endif |
| 324 | |
| 325 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); |
| 326 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | |
| 331 | static int __init ppro_init(char ** cpu_type) |
| 332 | { |
| 333 | __u8 cpu_model = boot_cpu_data.x86_model; |
| 334 | |
Benjamin LaHaise | 64471eb | 2006-05-15 09:44:24 -0700 | [diff] [blame] | 335 | if (cpu_model == 14) |
| 336 | *cpu_type = "i386/core"; |
| 337 | else if (cpu_model > 0xd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 338 | return 0; |
Benjamin LaHaise | 64471eb | 2006-05-15 09:44:24 -0700 | [diff] [blame] | 339 | else if (cpu_model == 9) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | *cpu_type = "i386/p6_mobile"; |
| 341 | } else if (cpu_model > 5) { |
| 342 | *cpu_type = "i386/piii"; |
| 343 | } else if (cpu_model > 2) { |
| 344 | *cpu_type = "i386/pii"; |
| 345 | } else { |
| 346 | *cpu_type = "i386/ppro"; |
| 347 | } |
| 348 | |
| 349 | model = &op_ppro_spec; |
| 350 | return 1; |
| 351 | } |
| 352 | |
| 353 | /* in order to get driverfs right */ |
| 354 | static int using_nmi; |
| 355 | |
David Gibson | 96d0821 | 2005-09-06 15:17:26 -0700 | [diff] [blame] | 356 | int __init op_nmi_init(struct oprofile_operations *ops) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | { |
| 358 | __u8 vendor = boot_cpu_data.x86_vendor; |
| 359 | __u8 family = boot_cpu_data.x86; |
| 360 | char *cpu_type; |
| 361 | |
| 362 | if (!cpu_has_apic) |
| 363 | return -ENODEV; |
| 364 | |
| 365 | switch (vendor) { |
| 366 | case X86_VENDOR_AMD: |
| 367 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ |
| 368 | |
| 369 | switch (family) { |
| 370 | default: |
| 371 | return -ENODEV; |
| 372 | case 6: |
| 373 | model = &op_athlon_spec; |
| 374 | cpu_type = "i386/athlon"; |
| 375 | break; |
| 376 | case 0xf: |
| 377 | model = &op_athlon_spec; |
| 378 | /* Actually it could be i386/hammer too, but give |
| 379 | user space an consistent name. */ |
| 380 | cpu_type = "x86-64/hammer"; |
| 381 | break; |
| 382 | } |
| 383 | break; |
| 384 | |
| 385 | case X86_VENDOR_INTEL: |
| 386 | switch (family) { |
| 387 | /* Pentium IV */ |
| 388 | case 0xf: |
| 389 | if (!p4_init(&cpu_type)) |
| 390 | return -ENODEV; |
| 391 | break; |
| 392 | |
| 393 | /* A P6-class processor */ |
| 394 | case 6: |
| 395 | if (!ppro_init(&cpu_type)) |
| 396 | return -ENODEV; |
| 397 | break; |
| 398 | |
| 399 | default: |
| 400 | return -ENODEV; |
| 401 | } |
| 402 | break; |
| 403 | |
| 404 | default: |
| 405 | return -ENODEV; |
| 406 | } |
| 407 | |
| 408 | init_driverfs(); |
| 409 | using_nmi = 1; |
| 410 | ops->create_files = nmi_create_files; |
| 411 | ops->setup = nmi_setup; |
| 412 | ops->shutdown = nmi_shutdown; |
| 413 | ops->start = nmi_start; |
| 414 | ops->stop = nmi_stop; |
| 415 | ops->cpu_type = cpu_type; |
| 416 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | |
David Gibson | 96d0821 | 2005-09-06 15:17:26 -0700 | [diff] [blame] | 421 | void op_nmi_exit(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | { |
| 423 | if (using_nmi) |
| 424 | exit_driverfs(); |
| 425 | } |