Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * BRIEF MODULE DESCRIPTION |
| 3 | * ITE 8172G interrupt/setup routines. |
| 4 | * |
| 5 | * Copyright 2000,2001 MontaVista Software Inc. |
| 6 | * Author: MontaVista Software, Inc. |
| 7 | * ppopov@mvista.com or source@mvista.com |
| 8 | * |
| 9 | * Part of this file was derived from Carsten Langgaard's |
| 10 | * arch/mips/mips-boards/atlas/atlas_int.c. |
| 11 | * |
| 12 | * Carsten Langgaard, carstenl@mips.com |
| 13 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify it |
| 16 | * under the terms of the GNU General Public License as published by the |
| 17 | * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | * option) any later version. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | * |
| 31 | * You should have received a copy of the GNU General Public License along |
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 34 | */ |
| 35 | #include <linux/errno.h> |
| 36 | #include <linux/init.h> |
| 37 | #include <linux/irq.h> |
| 38 | #include <linux/kernel_stat.h> |
| 39 | #include <linux/module.h> |
| 40 | #include <linux/signal.h> |
| 41 | #include <linux/sched.h> |
| 42 | #include <linux/types.h> |
| 43 | #include <linux/interrupt.h> |
| 44 | #include <linux/ioport.h> |
| 45 | #include <linux/timex.h> |
| 46 | #include <linux/slab.h> |
| 47 | #include <linux/random.h> |
| 48 | #include <linux/serial_reg.h> |
| 49 | #include <linux/bitops.h> |
| 50 | |
| 51 | #include <asm/bootinfo.h> |
| 52 | #include <asm/io.h> |
| 53 | #include <asm/mipsregs.h> |
| 54 | #include <asm/system.h> |
| 55 | #include <asm/it8172/it8172.h> |
| 56 | #include <asm/it8172/it8172_int.h> |
| 57 | #include <asm/it8172/it8172_dbg.h> |
| 58 | |
| 59 | /* revisit */ |
| 60 | #define EXT_IRQ0_TO_IP 2 /* IP 2 */ |
| 61 | #define EXT_IRQ5_TO_IP 7 /* IP 7 */ |
| 62 | |
| 63 | #define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) |
| 64 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | extern void set_debug_traps(void); |
| 66 | extern void mips_timer_interrupt(int irq, struct pt_regs *regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | |
| 68 | struct it8172_intc_regs volatile *it8172_hw0_icregs = |
| 69 | (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE)); |
| 70 | |
| 71 | static void disable_it8172_irq(unsigned int irq_nr) |
| 72 | { |
| 73 | if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { |
| 74 | /* LPC interrupt */ |
| 75 | it8172_hw0_icregs->lpc_mask |= |
| 76 | (1 << (irq_nr - IT8172_LPC_IRQ_BASE)); |
| 77 | } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { |
| 78 | /* Local Bus interrupt */ |
| 79 | it8172_hw0_icregs->lb_mask |= |
| 80 | (1 << (irq_nr - IT8172_LB_IRQ_BASE)); |
| 81 | } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { |
| 82 | /* PCI and other interrupts */ |
| 83 | it8172_hw0_icregs->pci_mask |= |
| 84 | (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); |
| 85 | } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { |
| 86 | /* NMI interrupts */ |
| 87 | it8172_hw0_icregs->nmi_mask |= |
| 88 | (1 << (irq_nr - IT8172_NMI_IRQ_BASE)); |
| 89 | } else { |
| 90 | panic("disable_it8172_irq: bad irq %d", irq_nr); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | static void enable_it8172_irq(unsigned int irq_nr) |
| 95 | { |
| 96 | if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { |
| 97 | /* LPC interrupt */ |
| 98 | it8172_hw0_icregs->lpc_mask &= |
| 99 | ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE)); |
| 100 | } |
| 101 | else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { |
| 102 | /* Local Bus interrupt */ |
| 103 | it8172_hw0_icregs->lb_mask &= |
| 104 | ~(1 << (irq_nr - IT8172_LB_IRQ_BASE)); |
| 105 | } |
| 106 | else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { |
| 107 | /* PCI and other interrupts */ |
| 108 | it8172_hw0_icregs->pci_mask &= |
| 109 | ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); |
| 110 | } |
| 111 | else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { |
| 112 | /* NMI interrupts */ |
| 113 | it8172_hw0_icregs->nmi_mask &= |
| 114 | ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE)); |
| 115 | } |
| 116 | else { |
| 117 | panic("enable_it8172_irq: bad irq %d", irq_nr); |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | static unsigned int startup_ite_irq(unsigned int irq) |
| 122 | { |
| 123 | enable_it8172_irq(irq); |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | #define shutdown_ite_irq disable_it8172_irq |
| 128 | #define mask_and_ack_ite_irq disable_it8172_irq |
| 129 | |
| 130 | static void end_ite_irq(unsigned int irq) |
| 131 | { |
| 132 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 133 | enable_it8172_irq(irq); |
| 134 | } |
| 135 | |
| 136 | static struct hw_interrupt_type it8172_irq_type = { |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 137 | .typename = "ITE8172", |
| 138 | .startup = startup_ite_irq, |
| 139 | .shutdown = shutdown_ite_irq, |
| 140 | .enable = enable_it8172_irq, |
| 141 | .disable = disable_it8172_irq, |
| 142 | .ack = mask_and_ack_ite_irq, |
| 143 | .end = end_ite_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | |
| 147 | static void enable_none(unsigned int irq) { } |
| 148 | static unsigned int startup_none(unsigned int irq) { return 0; } |
| 149 | static void disable_none(unsigned int irq) { } |
| 150 | static void ack_none(unsigned int irq) { } |
| 151 | |
| 152 | /* startup is the same as "enable", shutdown is same as "disable" */ |
| 153 | #define shutdown_none disable_none |
| 154 | #define end_none enable_none |
| 155 | |
| 156 | static struct hw_interrupt_type cp0_irq_type = { |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 157 | .typename = "CP0 Count", |
| 158 | .startup = startup_none, |
| 159 | .shutdown = shutdown_none, |
| 160 | .enable = enable_none, |
| 161 | .disable = disable_none, |
| 162 | .ack = ack_none, |
| 163 | .end = end_none |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | }; |
| 165 | |
| 166 | void enable_cpu_timer(void) |
| 167 | { |
| 168 | unsigned long flags; |
| 169 | |
| 170 | local_irq_save(flags); |
| 171 | set_c0_status(0x100 << EXT_IRQ5_TO_IP); |
| 172 | local_irq_restore(flags); |
| 173 | } |
| 174 | |
| 175 | void __init arch_init_irq(void) |
| 176 | { |
| 177 | int i; |
| 178 | unsigned long flags; |
| 179 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | /* mask all interrupts */ |
| 181 | it8172_hw0_icregs->lb_mask = 0xffff; |
| 182 | it8172_hw0_icregs->lpc_mask = 0xffff; |
| 183 | it8172_hw0_icregs->pci_mask = 0xffff; |
| 184 | it8172_hw0_icregs->nmi_mask = 0xffff; |
| 185 | |
| 186 | /* make all interrupts level triggered */ |
| 187 | it8172_hw0_icregs->lb_trigger = 0; |
| 188 | it8172_hw0_icregs->lpc_trigger = 0; |
| 189 | it8172_hw0_icregs->pci_trigger = 0; |
| 190 | it8172_hw0_icregs->nmi_trigger = 0; |
| 191 | |
| 192 | /* active level setting */ |
| 193 | /* uart, keyboard, and mouse are active high */ |
| 194 | it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000); |
| 195 | it8172_hw0_icregs->lb_level |= 0x20; |
| 196 | |
| 197 | /* keyboard and mouse are edge triggered */ |
| 198 | it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000); |
| 199 | |
| 200 | |
| 201 | #if 0 |
| 202 | // Enable this piece of code to make internal USB interrupt |
| 203 | // edge triggered. |
| 204 | it8172_hw0_icregs->pci_trigger |= |
| 205 | (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE)); |
| 206 | it8172_hw0_icregs->pci_level &= |
| 207 | ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE)); |
| 208 | #endif |
| 209 | |
| 210 | for (i = 0; i <= IT8172_LAST_IRQ; i++) { |
| 211 | irq_desc[i].handler = &it8172_irq_type; |
| 212 | spin_lock_init(&irq_desc[i].lock); |
| 213 | } |
| 214 | irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type; |
| 215 | set_c0_status(ALLINTS_NOTIMER); |
| 216 | } |
| 217 | |
| 218 | void mips_spurious_interrupt(struct pt_regs *regs) |
| 219 | { |
| 220 | #if 1 |
| 221 | return; |
| 222 | #else |
| 223 | unsigned long status, cause; |
| 224 | |
| 225 | printk("got spurious interrupt\n"); |
| 226 | status = read_c0_status(); |
| 227 | cause = read_c0_cause(); |
| 228 | printk("status %x cause %x\n", status, cause); |
| 229 | printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr); |
| 230 | #endif |
| 231 | } |
| 232 | |
| 233 | void it8172_hw0_irqdispatch(struct pt_regs *regs) |
| 234 | { |
| 235 | int irq; |
| 236 | unsigned short intstatus = 0, status = 0; |
| 237 | |
| 238 | intstatus = it8172_hw0_icregs->intstatus; |
| 239 | if (intstatus & 0x8) { |
| 240 | panic("Got NMI interrupt"); |
| 241 | } else if (intstatus & 0x4) { |
| 242 | /* PCI interrupt */ |
| 243 | irq = 0; |
| 244 | status |= it8172_hw0_icregs->pci_req; |
| 245 | while (!(status & 0x1)) { |
| 246 | irq++; |
| 247 | status >>= 1; |
| 248 | } |
| 249 | irq += IT8172_PCI_DEV_IRQ_BASE; |
| 250 | } else if (intstatus & 0x1) { |
| 251 | /* Local Bus interrupt */ |
| 252 | irq = 0; |
| 253 | status |= it8172_hw0_icregs->lb_req; |
| 254 | while (!(status & 0x1)) { |
| 255 | irq++; |
| 256 | status >>= 1; |
| 257 | } |
| 258 | irq += IT8172_LB_IRQ_BASE; |
| 259 | } else if (intstatus & 0x2) { |
| 260 | /* LPC interrupt */ |
| 261 | /* Since some lpc interrupts are edge triggered, |
| 262 | * we could lose an interrupt this way because |
| 263 | * we acknowledge all ints at onces. Revisit. |
| 264 | */ |
| 265 | status |= it8172_hw0_icregs->lpc_req; |
| 266 | it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */ |
| 267 | irq = 0; |
| 268 | while (!(status & 0x1)) { |
| 269 | irq++; |
| 270 | status >>= 1; |
| 271 | } |
| 272 | irq += IT8172_LPC_IRQ_BASE; |
| 273 | } else |
| 274 | return; |
| 275 | |
| 276 | do_IRQ(irq, regs); |
| 277 | } |
| 278 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 279 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
| 280 | { |
| 281 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 282 | |
| 283 | if (!pending) |
| 284 | mips_spurious_interrupt(regs); |
| 285 | else if (pending & CAUSEF_IP7) |
| 286 | ll_timer_interrupt(127, regs); |
| 287 | else if (pending & CAUSEF_IP2) |
| 288 | it8172_hw0_irqdispatch(regs); |
| 289 | } |
| 290 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | void show_pending_irqs(void) |
| 292 | { |
| 293 | fputs("intstatus: "); |
| 294 | put32(it8172_hw0_icregs->intstatus); |
| 295 | puts(""); |
| 296 | |
| 297 | fputs("pci_req: "); |
| 298 | put32(it8172_hw0_icregs->pci_req); |
| 299 | puts(""); |
| 300 | |
| 301 | fputs("lb_req: "); |
| 302 | put32(it8172_hw0_icregs->lb_req); |
| 303 | puts(""); |
| 304 | |
| 305 | fputs("lpc_req: "); |
| 306 | put32(it8172_hw0_icregs->lpc_req); |
| 307 | puts(""); |
| 308 | } |