Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can distribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License (Version 2) as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 11 | * for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along |
| 14 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 15 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 16 | * |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/kernel_stat.h> |
| 23 | #include <asm/mips-boards/simint.h> |
| 24 | |
| 25 | |
| 26 | extern void mips_cpu_irq_init(int); |
| 27 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 28 | static inline int clz(unsigned long x) |
| 29 | { |
| 30 | __asm__ ( |
| 31 | " .set push \n" |
| 32 | " .set mips32 \n" |
| 33 | " clz %0, %1 \n" |
| 34 | " .set pop \n" |
| 35 | : "=r" (x) |
| 36 | : "r" (x)); |
Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 37 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 38 | return x; |
| 39 | } |
| 40 | |
| 41 | /* |
| 42 | * Version of ffs that only looks at bits 12..15. |
| 43 | */ |
| 44 | static inline unsigned int irq_ffs(unsigned int pending) |
| 45 | { |
| 46 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
| 47 | return -clz(pending) + 31 - CAUSEB_IP; |
| 48 | #else |
| 49 | unsigned int a0 = 7; |
| 50 | unsigned int t0; |
| 51 | |
| 52 | t0 = s0 & 0xf000; |
| 53 | t0 = t0 < 1; |
| 54 | t0 = t0 << 2; |
| 55 | a0 = a0 - t0; |
| 56 | s0 = s0 << t0; |
| 57 | |
| 58 | t0 = s0 & 0xc000; |
| 59 | t0 = t0 < 1; |
| 60 | t0 = t0 << 1; |
| 61 | a0 = a0 - t0; |
| 62 | s0 = s0 << t0; |
| 63 | |
| 64 | t0 = s0 & 0x8000; |
| 65 | t0 = t0 < 1; |
| 66 | //t0 = t0 << 2; |
| 67 | a0 = a0 - t0; |
| 68 | //s0 = s0 << t0; |
| 69 | |
| 70 | return a0; |
| 71 | #endif |
| 72 | } |
| 73 | |
| 74 | static inline void sim_hw0_irqdispatch(struct pt_regs *regs) |
Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 75 | { |
| 76 | do_IRQ(2, regs); |
| 77 | } |
| 78 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 79 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
| 80 | { |
| 81 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 82 | int irq; |
| 83 | |
| 84 | irq = irq_ffs(pending); |
| 85 | |
| 86 | if (irq > 0) |
| 87 | do_IRQ(MIPSCPU_INT_BASE + irq, regs); |
| 88 | else |
| 89 | spurious_interrupt(regs); |
| 90 | } |
| 91 | |
Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 92 | void __init arch_init_irq(void) |
| 93 | { |
Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 94 | mips_cpu_irq_init(MIPSCPU_INT_BASE); |
| 95 | } |