Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 Momentum Computer, Inc. |
| 3 | * Author: Matthew Dharm, mdharm@momenco.com |
| 4 | * |
| 5 | * Based on work by: |
| 6 | * Copyright (C) 2000 RidgeRun, Inc. |
| 7 | * Author: RidgeRun, Inc. |
| 8 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com |
| 9 | * |
| 10 | * Copyright 2001 MontaVista Software Inc. |
| 11 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
| 12 | * |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 13 | * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify it |
| 16 | * under the terms of the GNU General Public License as published by the |
| 17 | * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | * option) any later version. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | * |
| 31 | * You should have received a copy of the GNU General Public License along |
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 34 | */ |
| 35 | #include <linux/init.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/signal.h> |
| 38 | #include <linux/types.h> |
| 39 | #include <asm/irq_cpu.h> |
| 40 | #include <asm/mipsregs.h> |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 41 | #include <asm/time.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 43 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
| 44 | { |
| 45 | unsigned int pending = read_c0_cause() & read_c0_status(); |
| 46 | |
| 47 | if (pending & STATUSF_IP0) |
| 48 | do_IRQ(0, regs); |
| 49 | else if (pending & STATUSF_IP1) |
| 50 | do_IRQ(1, regs); |
| 51 | else if (pending & STATUSF_IP2) |
| 52 | do_IRQ(2, regs); |
| 53 | else if (pending & STATUSF_IP3) |
| 54 | do_IRQ(3, regs); |
| 55 | else if (pending & STATUSF_IP4) |
| 56 | do_IRQ(4, regs); |
| 57 | else if (pending & STATUSF_IP5) |
| 58 | do_IRQ(5, regs); |
| 59 | else if (pending & STATUSF_IP6) |
| 60 | do_IRQ(6, regs); |
| 61 | else if (pending & STATUSF_IP7) |
| 62 | ll_timer_interrupt(7, regs); |
| 63 | else { |
| 64 | /* |
| 65 | * Now look at the extended interrupts |
| 66 | */ |
| 67 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; |
| 68 | if (pending & STATUSF_IP8) |
| 69 | ll_mv64340_irq(regs); |
| 70 | } |
| 71 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
| 73 | static struct irqaction cascade_mv64340 = { |
| 74 | no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL |
| 75 | }; |
| 76 | |
| 77 | void __init arch_init_irq(void) |
| 78 | { |
| 79 | /* |
| 80 | * Clear all of the interrupts while we change the able around a bit. |
| 81 | * int-handler is not on bootstrap |
| 82 | */ |
| 83 | clear_c0_status(ST0_IM); |
| 84 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | mips_cpu_irq_init(0); |
| 86 | rm7k_cpu_irq_init(8); |
| 87 | |
| 88 | /* set up the cascading interrupts */ |
| 89 | setup_irq(8, &cascade_mv64340); |
| 90 | |
| 91 | mv64340_irq_init(16); |
| 92 | |
| 93 | set_c0_status(ST0_IM); |
| 94 | } |