Andrew Victor | 65dbf34 | 2006-04-02 19:18:51 +0100 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h |
| 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * |
| 7 | * MultiMedia Card Interface (MCI) registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91RM9200_MCI_H |
| 17 | #define AT91RM9200_MCI_H |
| 18 | |
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ |
| 21 | #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ |
| 22 | #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ |
| 23 | #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ |
| 24 | #define AT91_MCI_SWRST (1 << 7) /* Software Reset */ |
| 25 | |
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ |
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ |
| 28 | #define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ |
| 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ |
| 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ |
| 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ |
| 32 | |
| 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ |
| 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ |
| 35 | #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ |
| 36 | #define AT91_MCI_DTOMUL_1 (0 << 4) |
| 37 | #define AT91_MCI_DTOMUL_16 (1 << 4) |
| 38 | #define AT91_MCI_DTOMUL_128 (2 << 4) |
| 39 | #define AT91_MCI_DTOMUL_256 (3 << 4) |
| 40 | #define AT91_MCI_DTOMUL_1K (4 << 4) |
| 41 | #define AT91_MCI_DTOMUL_4K (5 << 4) |
| 42 | #define AT91_MCI_DTOMUL_64K (6 << 4) |
| 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) |
| 44 | |
| 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ |
| 46 | #define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ |
| 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ |
| 48 | |
| 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ |
| 50 | |
| 51 | #define AT91_MCI_CMDR 0x14 /* Command Register */ |
| 52 | #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ |
| 53 | #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ |
| 54 | #define AT91_MCI_RSPTYP_NONE (0 << 6) |
| 55 | #define AT91_MCI_RSPTYP_48 (1 << 6) |
| 56 | #define AT91_MCI_RSPTYP_136 (2 << 6) |
| 57 | #define AT91_MCI_SPCMD (7 << 8) /* Special Command */ |
| 58 | #define AT91_MCI_SPCMD_NONE (0 << 8) |
| 59 | #define AT91_MCI_SPCMD_INIT (1 << 8) |
| 60 | #define AT91_MCI_SPCMD_SYNC (2 << 8) |
| 61 | #define AT91_MCI_SPCMD_ICMD (4 << 8) |
| 62 | #define AT91_MCI_SPCMD_IRESP (5 << 8) |
| 63 | #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ |
| 64 | #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ |
| 65 | #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ |
| 66 | #define AT91_MCI_TRCMD_NONE (0 << 16) |
| 67 | #define AT91_MCI_TRCMD_START (1 << 16) |
| 68 | #define AT91_MCI_TRCMD_STOP (2 << 16) |
| 69 | #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ |
| 70 | #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ |
| 71 | #define AT91_MCI_TRTYP_BLOCK (0 << 19) |
| 72 | #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) |
| 73 | #define AT91_MCI_TRTYP_STREAM (2 << 19) |
| 74 | |
| 75 | #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ |
| 76 | #define AT91_MCR_RDR 0x30 /* Receive Data Register */ |
| 77 | #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ |
| 78 | |
| 79 | #define AT91_MCI_SR 0x40 /* Status Register */ |
| 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ |
| 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ |
| 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ |
| 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ |
| 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ |
| 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ |
| 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ |
| 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ |
| 88 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ |
| 89 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ |
| 90 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ |
| 91 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ |
| 92 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ |
| 93 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ |
| 94 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ |
| 95 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ |
| 96 | #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ |
| 97 | #define AT91_MCI_OVRE (1 << 30) /* Overrun */ |
| 98 | #define AT91_MCI_UNRE (1 << 31) /* Underrun */ |
| 99 | |
| 100 | #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ |
| 101 | #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ |
| 102 | #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ |
| 103 | |
| 104 | #endif |