| Akira Takeuchi | 368dd5a | 2010-10-27 17:28:55 +0100 | [diff] [blame] | 1 | /* ASB2364 FPGA registers |
| 2 | */ |
| 3 | |
| 4 | #ifndef _ASM_UNIT_FPGA_REGS_H |
| 5 | #define _ASM_UNIT_FPGA_REGS_H |
| 6 | |
| 7 | #include <asm/cpu-regs.h> |
| 8 | |
| 9 | #ifdef __KERNEL__ |
| 10 | |
| 11 | #define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16) |
| 12 | #define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16) |
| 13 | #define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16) |
| 14 | #define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16) |
| 15 | #define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16) |
| 16 | |
| David Howells | 5f91a1a | 2011-03-18 16:52:53 +0000 | [diff] [blame] | 17 | #define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16) |
| David Howells | 6044cf1 | 2010-10-27 17:28:58 +0100 | [diff] [blame] | 18 | #define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0) |
| 19 | #define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1) |
| 20 | #define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2) |
| 21 | #define ASB2364_FPGA_REG_IRQ_USB ASB2364_FPGA_REG_IRQ(3) |
| 22 | #define ASB2364_FPGA_REG_IRQ_FPGA ASB2364_FPGA_REG_IRQ(5) |
| Akira Takeuchi | 368dd5a | 2010-10-27 17:28:55 +0100 | [diff] [blame] | 23 | |
| David Howells | 6044cf1 | 2010-10-27 17:28:58 +0100 | [diff] [blame] | 24 | #define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16) |
| 25 | #define ASB2364_FPGA_REG_MASK_LAN ASB2364_FPGA_REG_MASK(0) |
| 26 | #define ASB2364_FPGA_REG_MASK_UART ASB2364_FPGA_REG_MASK(1) |
| 27 | #define ASB2364_FPGA_REG_MASK_I2C ASB2364_FPGA_REG_MASK(2) |
| 28 | #define ASB2364_FPGA_REG_MASK_USB ASB2364_FPGA_REG_MASK(3) |
| 29 | #define ASB2364_FPGA_REG_MASK_FPGA ASB2364_FPGA_REG_MASK(5) |
| Akira Takeuchi | 368dd5a | 2010-10-27 17:28:55 +0100 | [diff] [blame] | 30 | |
| 31 | #define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16) |
| 32 | #define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16) |
| 33 | #define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16) |
| 34 | #define ASB2364_FPGA_REG_CPLD6_SET2 __SYSREG(0xa9002604, u16) |
| 35 | #define ASB2364_FPGA_REG_CPLD7_SET1 __SYSREG(0xa9002700, u16) |
| 36 | #define ASB2364_FPGA_REG_CPLD7_SET2 __SYSREG(0xa9002704, u16) |
| 37 | #define ASB2364_FPGA_REG_CPLD8_SET1 __SYSREG(0xa9002800, u16) |
| 38 | #define ASB2364_FPGA_REG_CPLD8_SET2 __SYSREG(0xa9002804, u16) |
| 39 | #define ASB2364_FPGA_REG_CPLD9_SET1 __SYSREG(0xa9002900, u16) |
| 40 | #define ASB2364_FPGA_REG_CPLD9_SET2 __SYSREG(0xa9002904, u16) |
| 41 | #define ASB2364_FPGA_REG_CPLD10_SET1 __SYSREG(0xa9002a00, u16) |
| 42 | #define ASB2364_FPGA_REG_CPLD10_SET2 __SYSREG(0xa9002a04, u16) |
| 43 | |
| 44 | #define SyncExBus() \ |
| 45 | do { \ |
| 46 | unsigned short w; \ |
| 47 | w = *(volatile short *)0xa9000000; \ |
| 48 | } while (0) |
| 49 | |
| 50 | #endif /* __KERNEL__ */ |
| 51 | |
| 52 | #endif /* _ASM_UNIT_FPGA_REGS_H */ |