Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * The data in this file should be completely autogeneratable from |
| 12 | * the TI hardware database or other technical documentation. |
| 13 | * |
| 14 | * XXX these should be marked initdata for multi-OMAP kernels |
| 15 | */ |
| 16 | #include <plat/omap_hwmod.h> |
| 17 | #include <mach/irqs.h> |
| 18 | #include <plat/cpu.h> |
| 19 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 20 | #include <plat/serial.h> |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 21 | #include <plat/l4_3xxx.h> |
| 22 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 70034d3 | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 23 | #include <plat/gpio.h> |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 24 | #include <plat/smartreflex.h> |
Charulatha V | 0f616a4 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 25 | #include <plat/mcspi.h> |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 26 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 27 | #include "omap_hwmod_common_data.h" |
| 28 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 29 | #include "prm-regbits-34xx.h" |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 30 | #include "cm-regbits-34xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 31 | #include "wd_timer.h" |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * OMAP3xxx hardware module integration data |
| 35 | * |
| 36 | * ALl of the data in this section should be autogeneratable from the |
| 37 | * TI hardware database or other technical documentation. Data that |
| 38 | * is driver-specific or driver-kernel integration-specific belongs |
| 39 | * elsewhere. |
| 40 | */ |
| 41 | |
| 42 | static struct omap_hwmod omap3xxx_mpu_hwmod; |
Kevin Hilman | 540064b | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 43 | static struct omap_hwmod omap3xxx_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 44 | static struct omap_hwmod omap3xxx_l3_main_hwmod; |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 45 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
| 46 | static struct omap_hwmod omap3xxx_l4_per_hwmod; |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 47 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 48 | static struct omap_hwmod omap3xxx_i2c1_hwmod; |
| 49 | static struct omap_hwmod omap3xxx_i2c2_hwmod; |
| 50 | static struct omap_hwmod omap3xxx_i2c3_hwmod; |
Varadarajan, Charulatha | 70034d3 | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 51 | static struct omap_hwmod omap3xxx_gpio1_hwmod; |
| 52 | static struct omap_hwmod omap3xxx_gpio2_hwmod; |
| 53 | static struct omap_hwmod omap3xxx_gpio3_hwmod; |
| 54 | static struct omap_hwmod omap3xxx_gpio4_hwmod; |
| 55 | static struct omap_hwmod omap3xxx_gpio5_hwmod; |
| 56 | static struct omap_hwmod omap3xxx_gpio6_hwmod; |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 57 | static struct omap_hwmod omap34xx_sr1_hwmod; |
| 58 | static struct omap_hwmod omap34xx_sr2_hwmod; |
Charulatha V | 0f616a4 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 59 | static struct omap_hwmod omap34xx_mcspi1; |
| 60 | static struct omap_hwmod omap34xx_mcspi2; |
| 61 | static struct omap_hwmod omap34xx_mcspi3; |
| 62 | static struct omap_hwmod omap34xx_mcspi4; |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 63 | |
G, Manjunath Kondaiah | 01438ab | 2010-12-20 18:27:19 -0800 | [diff] [blame] | 64 | static struct omap_hwmod omap3xxx_dma_system_hwmod; |
| 65 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 66 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 67 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
| 68 | .master = &omap3xxx_l3_main_hwmod, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 69 | .slave = &omap3xxx_l4_core_hwmod, |
| 70 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 71 | }; |
| 72 | |
| 73 | /* L3 -> L4_PER interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 74 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
| 75 | .master = &omap3xxx_l3_main_hwmod, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 76 | .slave = &omap3xxx_l4_per_hwmod, |
| 77 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 78 | }; |
| 79 | |
| 80 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 81 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 82 | .master = &omap3xxx_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 83 | .slave = &omap3xxx_l3_main_hwmod, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 84 | .user = OCP_USER_MPU, |
| 85 | }; |
| 86 | |
| 87 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 88 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
| 89 | &omap3xxx_mpu__l3_main, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 93 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
| 94 | &omap3xxx_l3_main__l4_core, |
| 95 | &omap3xxx_l3_main__l4_per, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 99 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 100 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 101 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 102 | .masters = omap3xxx_l3_main_masters, |
| 103 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), |
| 104 | .slaves = omap3xxx_l3_main_slaves, |
| 105 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 106 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 107 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 111 | static struct omap_hwmod omap3xxx_uart1_hwmod; |
| 112 | static struct omap_hwmod omap3xxx_uart2_hwmod; |
| 113 | static struct omap_hwmod omap3xxx_uart3_hwmod; |
| 114 | static struct omap_hwmod omap3xxx_uart4_hwmod; |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 115 | |
| 116 | /* L4_CORE -> L4_WKUP interface */ |
| 117 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { |
| 118 | .master = &omap3xxx_l4_core_hwmod, |
| 119 | .slave = &omap3xxx_l4_wkup_hwmod, |
| 120 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 121 | }; |
| 122 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 123 | /* L4 CORE -> UART1 interface */ |
| 124 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { |
| 125 | { |
| 126 | .pa_start = OMAP3_UART1_BASE, |
| 127 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, |
| 128 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 129 | }, |
| 130 | }; |
| 131 | |
| 132 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
| 133 | .master = &omap3xxx_l4_core_hwmod, |
| 134 | .slave = &omap3xxx_uart1_hwmod, |
| 135 | .clk = "uart1_ick", |
| 136 | .addr = omap3xxx_uart1_addr_space, |
| 137 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), |
| 138 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 139 | }; |
| 140 | |
| 141 | /* L4 CORE -> UART2 interface */ |
| 142 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { |
| 143 | { |
| 144 | .pa_start = OMAP3_UART2_BASE, |
| 145 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, |
| 146 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 147 | }, |
| 148 | }; |
| 149 | |
| 150 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
| 151 | .master = &omap3xxx_l4_core_hwmod, |
| 152 | .slave = &omap3xxx_uart2_hwmod, |
| 153 | .clk = "uart2_ick", |
| 154 | .addr = omap3xxx_uart2_addr_space, |
| 155 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), |
| 156 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 157 | }; |
| 158 | |
| 159 | /* L4 PER -> UART3 interface */ |
| 160 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { |
| 161 | { |
| 162 | .pa_start = OMAP3_UART3_BASE, |
| 163 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, |
| 164 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 165 | }, |
| 166 | }; |
| 167 | |
| 168 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
| 169 | .master = &omap3xxx_l4_per_hwmod, |
| 170 | .slave = &omap3xxx_uart3_hwmod, |
| 171 | .clk = "uart3_ick", |
| 172 | .addr = omap3xxx_uart3_addr_space, |
| 173 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), |
| 174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 175 | }; |
| 176 | |
| 177 | /* L4 PER -> UART4 interface */ |
| 178 | static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { |
| 179 | { |
| 180 | .pa_start = OMAP3_UART4_BASE, |
| 181 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, |
| 182 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 183 | }, |
| 184 | }; |
| 185 | |
| 186 | static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { |
| 187 | .master = &omap3xxx_l4_per_hwmod, |
| 188 | .slave = &omap3xxx_uart4_hwmod, |
| 189 | .clk = "uart4_ick", |
| 190 | .addr = omap3xxx_uart4_addr_space, |
| 191 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), |
| 192 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 193 | }; |
| 194 | |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 195 | /* I2C IP block address space length (in bytes) */ |
| 196 | #define OMAP2_I2C_AS_LEN 128 |
| 197 | |
| 198 | /* L4 CORE -> I2C1 interface */ |
| 199 | static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { |
| 200 | { |
| 201 | .pa_start = 0x48070000, |
| 202 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 203 | .flags = ADDR_TYPE_RT, |
| 204 | }, |
| 205 | }; |
| 206 | |
| 207 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { |
| 208 | .master = &omap3xxx_l4_core_hwmod, |
| 209 | .slave = &omap3xxx_i2c1_hwmod, |
| 210 | .clk = "i2c1_ick", |
| 211 | .addr = omap3xxx_i2c1_addr_space, |
| 212 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), |
| 213 | .fw = { |
| 214 | .omap2 = { |
| 215 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, |
| 216 | .l4_prot_group = 7, |
| 217 | .flags = OMAP_FIREWALL_L4, |
| 218 | } |
| 219 | }, |
| 220 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 221 | }; |
| 222 | |
| 223 | /* L4 CORE -> I2C2 interface */ |
| 224 | static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { |
| 225 | { |
| 226 | .pa_start = 0x48072000, |
| 227 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 228 | .flags = ADDR_TYPE_RT, |
| 229 | }, |
| 230 | }; |
| 231 | |
| 232 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { |
| 233 | .master = &omap3xxx_l4_core_hwmod, |
| 234 | .slave = &omap3xxx_i2c2_hwmod, |
| 235 | .clk = "i2c2_ick", |
| 236 | .addr = omap3xxx_i2c2_addr_space, |
| 237 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), |
| 238 | .fw = { |
| 239 | .omap2 = { |
| 240 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
| 241 | .l4_prot_group = 7, |
| 242 | .flags = OMAP_FIREWALL_L4, |
| 243 | } |
| 244 | }, |
| 245 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 246 | }; |
| 247 | |
| 248 | /* L4 CORE -> I2C3 interface */ |
| 249 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { |
| 250 | { |
| 251 | .pa_start = 0x48060000, |
| 252 | .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, |
| 253 | .flags = ADDR_TYPE_RT, |
| 254 | }, |
| 255 | }; |
| 256 | |
| 257 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
| 258 | .master = &omap3xxx_l4_core_hwmod, |
| 259 | .slave = &omap3xxx_i2c3_hwmod, |
| 260 | .clk = "i2c3_ick", |
| 261 | .addr = omap3xxx_i2c3_addr_space, |
| 262 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), |
| 263 | .fw = { |
| 264 | .omap2 = { |
| 265 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, |
| 266 | .l4_prot_group = 7, |
| 267 | .flags = OMAP_FIREWALL_L4, |
| 268 | } |
| 269 | }, |
| 270 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 271 | }; |
| 272 | |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 273 | /* L4 CORE -> SR1 interface */ |
| 274 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { |
| 275 | { |
| 276 | .pa_start = OMAP34XX_SR1_BASE, |
| 277 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, |
| 278 | .flags = ADDR_TYPE_RT, |
| 279 | }, |
| 280 | }; |
| 281 | |
| 282 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { |
| 283 | .master = &omap3xxx_l4_core_hwmod, |
| 284 | .slave = &omap34xx_sr1_hwmod, |
| 285 | .clk = "sr_l4_ick", |
| 286 | .addr = omap3_sr1_addr_space, |
| 287 | .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space), |
| 288 | .user = OCP_USER_MPU, |
| 289 | }; |
| 290 | |
| 291 | /* L4 CORE -> SR1 interface */ |
| 292 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { |
| 293 | { |
| 294 | .pa_start = OMAP34XX_SR2_BASE, |
| 295 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, |
| 296 | .flags = ADDR_TYPE_RT, |
| 297 | }, |
| 298 | }; |
| 299 | |
| 300 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { |
| 301 | .master = &omap3xxx_l4_core_hwmod, |
| 302 | .slave = &omap34xx_sr2_hwmod, |
| 303 | .clk = "sr_l4_ick", |
| 304 | .addr = omap3_sr2_addr_space, |
| 305 | .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space), |
| 306 | .user = OCP_USER_MPU, |
| 307 | }; |
| 308 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 309 | /* Slave interfaces on the L4_CORE interconnect */ |
| 310 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 311 | &omap3xxx_l3_main__l4_core, |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 312 | &omap3_l4_core__sr1, |
| 313 | &omap3_l4_core__sr2, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | /* Master interfaces on the L4_CORE interconnect */ |
| 317 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { |
| 318 | &omap3xxx_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 319 | &omap3_l4_core__uart1, |
| 320 | &omap3_l4_core__uart2, |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 321 | &omap3_l4_core__i2c1, |
| 322 | &omap3_l4_core__i2c2, |
| 323 | &omap3_l4_core__i2c3, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | /* L4 CORE */ |
| 327 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 328 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 329 | .class = &l4_hwmod_class, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 330 | .masters = omap3xxx_l4_core_masters, |
| 331 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), |
| 332 | .slaves = omap3xxx_l4_core_slaves, |
| 333 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 334 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 335 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | /* Slave interfaces on the L4_PER interconnect */ |
| 339 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 340 | &omap3xxx_l3_main__l4_per, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | /* Master interfaces on the L4_PER interconnect */ |
| 344 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 345 | &omap3_l4_per__uart3, |
| 346 | &omap3_l4_per__uart4, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | /* L4 PER */ |
| 350 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 351 | .name = "l4_per", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 352 | .class = &l4_hwmod_class, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 353 | .masters = omap3xxx_l4_per_masters, |
| 354 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), |
| 355 | .slaves = omap3xxx_l4_per_slaves, |
| 356 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 357 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 358 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 359 | }; |
| 360 | |
| 361 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 362 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { |
| 363 | &omap3xxx_l4_core__l4_wkup, |
| 364 | }; |
| 365 | |
| 366 | /* Master interfaces on the L4_WKUP interconnect */ |
| 367 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { |
| 368 | }; |
| 369 | |
| 370 | /* L4 WKUP */ |
| 371 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 372 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 373 | .class = &l4_hwmod_class, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 374 | .masters = omap3xxx_l4_wkup_masters, |
| 375 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), |
| 376 | .slaves = omap3xxx_l4_wkup_slaves, |
| 377 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 378 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 379 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 380 | }; |
| 381 | |
| 382 | /* Master interfaces on the MPU device */ |
| 383 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 384 | &omap3xxx_mpu__l3_main, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | /* MPU */ |
| 388 | static struct omap_hwmod omap3xxx_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 389 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 390 | .class = &mpu_hwmod_class, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 391 | .main_clk = "arm_fck", |
| 392 | .masters = omap3xxx_mpu_masters, |
| 393 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), |
| 394 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 395 | }; |
| 396 | |
Kevin Hilman | 540064b | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 397 | /* |
| 398 | * IVA2_2 interface data |
| 399 | */ |
| 400 | |
| 401 | /* IVA2 <- L3 interface */ |
| 402 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { |
| 403 | .master = &omap3xxx_l3_main_hwmod, |
| 404 | .slave = &omap3xxx_iva_hwmod, |
| 405 | .clk = "iva2_ck", |
| 406 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 407 | }; |
| 408 | |
| 409 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { |
| 410 | &omap3xxx_l3__iva, |
| 411 | }; |
| 412 | |
| 413 | /* |
| 414 | * IVA2 (IVA2) |
| 415 | */ |
| 416 | |
| 417 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
| 418 | .name = "iva", |
| 419 | .class = &iva_hwmod_class, |
| 420 | .masters = omap3xxx_iva_masters, |
| 421 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), |
| 422 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 423 | }; |
| 424 | |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 425 | /* l4_wkup -> wd_timer2 */ |
| 426 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { |
| 427 | { |
| 428 | .pa_start = 0x48314000, |
| 429 | .pa_end = 0x4831407f, |
| 430 | .flags = ADDR_TYPE_RT |
| 431 | }, |
| 432 | }; |
| 433 | |
| 434 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
| 435 | .master = &omap3xxx_l4_wkup_hwmod, |
| 436 | .slave = &omap3xxx_wd_timer2_hwmod, |
| 437 | .clk = "wdt2_ick", |
| 438 | .addr = omap3xxx_wd_timer2_addrs, |
| 439 | .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), |
| 440 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 441 | }; |
| 442 | |
| 443 | /* |
| 444 | * 'wd_timer' class |
| 445 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 446 | * overflow condition |
| 447 | */ |
| 448 | |
| 449 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { |
| 450 | .rev_offs = 0x0000, |
| 451 | .sysc_offs = 0x0010, |
| 452 | .syss_offs = 0x0014, |
| 453 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | |
| 454 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 455 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), |
| 456 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 457 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 458 | }; |
| 459 | |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 460 | /* I2C common */ |
| 461 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 462 | .rev_offs = 0x00, |
| 463 | .sysc_offs = 0x20, |
| 464 | .syss_offs = 0x10, |
| 465 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 466 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 467 | SYSC_HAS_AUTOIDLE), |
| 468 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 469 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 470 | }; |
| 471 | |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 472 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 473 | .name = "wd_timer", |
| 474 | .sysc = &omap3xxx_wd_timer_sysc, |
| 475 | .pre_shutdown = &omap2_wd_timer_disable |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 476 | }; |
| 477 | |
| 478 | /* wd_timer2 */ |
| 479 | static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { |
| 480 | &omap3xxx_l4_wkup__wd_timer2, |
| 481 | }; |
| 482 | |
| 483 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
| 484 | .name = "wd_timer2", |
| 485 | .class = &omap3xxx_wd_timer_hwmod_class, |
| 486 | .main_clk = "wdt2_fck", |
| 487 | .prcm = { |
| 488 | .omap2 = { |
| 489 | .prcm_reg_id = 1, |
| 490 | .module_bit = OMAP3430_EN_WDT2_SHIFT, |
| 491 | .module_offs = WKUP_MOD, |
| 492 | .idlest_reg_id = 1, |
| 493 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, |
| 494 | }, |
| 495 | }, |
| 496 | .slaves = omap3xxx_wd_timer2_slaves, |
| 497 | .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), |
| 498 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 499 | }; |
| 500 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 501 | /* UART common */ |
| 502 | |
| 503 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 504 | .rev_offs = 0x50, |
| 505 | .sysc_offs = 0x54, |
| 506 | .syss_offs = 0x58, |
| 507 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 508 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 509 | SYSC_HAS_AUTOIDLE), |
| 510 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 511 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 512 | }; |
| 513 | |
| 514 | static struct omap_hwmod_class uart_class = { |
| 515 | .name = "uart", |
| 516 | .sysc = &uart_sysc, |
| 517 | }; |
| 518 | |
| 519 | /* UART1 */ |
| 520 | |
| 521 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 522 | { .irq = INT_24XX_UART1_IRQ, }, |
| 523 | }; |
| 524 | |
| 525 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 526 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 527 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 528 | }; |
| 529 | |
| 530 | static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { |
| 531 | &omap3_l4_core__uart1, |
| 532 | }; |
| 533 | |
| 534 | static struct omap_hwmod omap3xxx_uart1_hwmod = { |
| 535 | .name = "uart1", |
| 536 | .mpu_irqs = uart1_mpu_irqs, |
| 537 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 538 | .sdma_reqs = uart1_sdma_reqs, |
| 539 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 540 | .main_clk = "uart1_fck", |
| 541 | .prcm = { |
| 542 | .omap2 = { |
| 543 | .module_offs = CORE_MOD, |
| 544 | .prcm_reg_id = 1, |
| 545 | .module_bit = OMAP3430_EN_UART1_SHIFT, |
| 546 | .idlest_reg_id = 1, |
| 547 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, |
| 548 | }, |
| 549 | }, |
| 550 | .slaves = omap3xxx_uart1_slaves, |
| 551 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), |
| 552 | .class = &uart_class, |
| 553 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 554 | }; |
| 555 | |
| 556 | /* UART2 */ |
| 557 | |
| 558 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 559 | { .irq = INT_24XX_UART2_IRQ, }, |
| 560 | }; |
| 561 | |
| 562 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 563 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 564 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 565 | }; |
| 566 | |
| 567 | static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { |
| 568 | &omap3_l4_core__uart2, |
| 569 | }; |
| 570 | |
| 571 | static struct omap_hwmod omap3xxx_uart2_hwmod = { |
| 572 | .name = "uart2", |
| 573 | .mpu_irqs = uart2_mpu_irqs, |
| 574 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 575 | .sdma_reqs = uart2_sdma_reqs, |
| 576 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 577 | .main_clk = "uart2_fck", |
| 578 | .prcm = { |
| 579 | .omap2 = { |
| 580 | .module_offs = CORE_MOD, |
| 581 | .prcm_reg_id = 1, |
| 582 | .module_bit = OMAP3430_EN_UART2_SHIFT, |
| 583 | .idlest_reg_id = 1, |
| 584 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, |
| 585 | }, |
| 586 | }, |
| 587 | .slaves = omap3xxx_uart2_slaves, |
| 588 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), |
| 589 | .class = &uart_class, |
| 590 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 591 | }; |
| 592 | |
| 593 | /* UART3 */ |
| 594 | |
| 595 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 596 | { .irq = INT_24XX_UART3_IRQ, }, |
| 597 | }; |
| 598 | |
| 599 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 600 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 601 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 602 | }; |
| 603 | |
| 604 | static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { |
| 605 | &omap3_l4_per__uart3, |
| 606 | }; |
| 607 | |
| 608 | static struct omap_hwmod omap3xxx_uart3_hwmod = { |
| 609 | .name = "uart3", |
| 610 | .mpu_irqs = uart3_mpu_irqs, |
| 611 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 612 | .sdma_reqs = uart3_sdma_reqs, |
| 613 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 614 | .main_clk = "uart3_fck", |
| 615 | .prcm = { |
| 616 | .omap2 = { |
| 617 | .module_offs = OMAP3430_PER_MOD, |
| 618 | .prcm_reg_id = 1, |
| 619 | .module_bit = OMAP3430_EN_UART3_SHIFT, |
| 620 | .idlest_reg_id = 1, |
| 621 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, |
| 622 | }, |
| 623 | }, |
| 624 | .slaves = omap3xxx_uart3_slaves, |
| 625 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), |
| 626 | .class = &uart_class, |
| 627 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 628 | }; |
| 629 | |
| 630 | /* UART4 */ |
| 631 | |
| 632 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { |
| 633 | { .irq = INT_36XX_UART4_IRQ, }, |
| 634 | }; |
| 635 | |
| 636 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
| 637 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, |
| 638 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, |
| 639 | }; |
| 640 | |
| 641 | static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { |
| 642 | &omap3_l4_per__uart4, |
| 643 | }; |
| 644 | |
| 645 | static struct omap_hwmod omap3xxx_uart4_hwmod = { |
| 646 | .name = "uart4", |
| 647 | .mpu_irqs = uart4_mpu_irqs, |
| 648 | .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), |
| 649 | .sdma_reqs = uart4_sdma_reqs, |
| 650 | .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), |
| 651 | .main_clk = "uart4_fck", |
| 652 | .prcm = { |
| 653 | .omap2 = { |
| 654 | .module_offs = OMAP3430_PER_MOD, |
| 655 | .prcm_reg_id = 1, |
| 656 | .module_bit = OMAP3630_EN_UART4_SHIFT, |
| 657 | .idlest_reg_id = 1, |
| 658 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, |
| 659 | }, |
| 660 | }, |
| 661 | .slaves = omap3xxx_uart4_slaves, |
| 662 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), |
| 663 | .class = &uart_class, |
| 664 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), |
| 665 | }; |
| 666 | |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 667 | static struct omap_hwmod_class i2c_class = { |
| 668 | .name = "i2c", |
| 669 | .sysc = &i2c_sysc, |
| 670 | }; |
| 671 | |
| 672 | /* I2C1 */ |
| 673 | |
| 674 | static struct omap_i2c_dev_attr i2c1_dev_attr = { |
| 675 | .fifo_depth = 8, /* bytes */ |
| 676 | }; |
| 677 | |
| 678 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 679 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 680 | }; |
| 681 | |
| 682 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 683 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 684 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 685 | }; |
| 686 | |
| 687 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { |
| 688 | &omap3_l4_core__i2c1, |
| 689 | }; |
| 690 | |
| 691 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
| 692 | .name = "i2c1", |
| 693 | .mpu_irqs = i2c1_mpu_irqs, |
| 694 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 695 | .sdma_reqs = i2c1_sdma_reqs, |
| 696 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 697 | .main_clk = "i2c1_fck", |
| 698 | .prcm = { |
| 699 | .omap2 = { |
| 700 | .module_offs = CORE_MOD, |
| 701 | .prcm_reg_id = 1, |
| 702 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
| 703 | .idlest_reg_id = 1, |
| 704 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
| 705 | }, |
| 706 | }, |
| 707 | .slaves = omap3xxx_i2c1_slaves, |
| 708 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), |
| 709 | .class = &i2c_class, |
| 710 | .dev_attr = &i2c1_dev_attr, |
| 711 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 712 | }; |
| 713 | |
| 714 | /* I2C2 */ |
| 715 | |
| 716 | static struct omap_i2c_dev_attr i2c2_dev_attr = { |
| 717 | .fifo_depth = 8, /* bytes */ |
| 718 | }; |
| 719 | |
| 720 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 721 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 722 | }; |
| 723 | |
| 724 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 725 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 726 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 727 | }; |
| 728 | |
| 729 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { |
| 730 | &omap3_l4_core__i2c2, |
| 731 | }; |
| 732 | |
| 733 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
| 734 | .name = "i2c2", |
| 735 | .mpu_irqs = i2c2_mpu_irqs, |
| 736 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 737 | .sdma_reqs = i2c2_sdma_reqs, |
| 738 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 739 | .main_clk = "i2c2_fck", |
| 740 | .prcm = { |
| 741 | .omap2 = { |
| 742 | .module_offs = CORE_MOD, |
| 743 | .prcm_reg_id = 1, |
| 744 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
| 745 | .idlest_reg_id = 1, |
| 746 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
| 747 | }, |
| 748 | }, |
| 749 | .slaves = omap3xxx_i2c2_slaves, |
| 750 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), |
| 751 | .class = &i2c_class, |
| 752 | .dev_attr = &i2c2_dev_attr, |
| 753 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 754 | }; |
| 755 | |
| 756 | /* I2C3 */ |
| 757 | |
| 758 | static struct omap_i2c_dev_attr i2c3_dev_attr = { |
| 759 | .fifo_depth = 64, /* bytes */ |
| 760 | }; |
| 761 | |
| 762 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
| 763 | { .irq = INT_34XX_I2C3_IRQ, }, |
| 764 | }; |
| 765 | |
| 766 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
| 767 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, |
| 768 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, |
| 769 | }; |
| 770 | |
| 771 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { |
| 772 | &omap3_l4_core__i2c3, |
| 773 | }; |
| 774 | |
| 775 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
| 776 | .name = "i2c3", |
| 777 | .mpu_irqs = i2c3_mpu_irqs, |
| 778 | .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), |
| 779 | .sdma_reqs = i2c3_sdma_reqs, |
| 780 | .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), |
| 781 | .main_clk = "i2c3_fck", |
| 782 | .prcm = { |
| 783 | .omap2 = { |
| 784 | .module_offs = CORE_MOD, |
| 785 | .prcm_reg_id = 1, |
| 786 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
| 787 | .idlest_reg_id = 1, |
| 788 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
| 789 | }, |
| 790 | }, |
| 791 | .slaves = omap3xxx_i2c3_slaves, |
| 792 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), |
| 793 | .class = &i2c_class, |
| 794 | .dev_attr = &i2c3_dev_attr, |
| 795 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 796 | }; |
| 797 | |
Varadarajan, Charulatha | 70034d3 | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 798 | /* l4_wkup -> gpio1 */ |
| 799 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { |
| 800 | { |
| 801 | .pa_start = 0x48310000, |
| 802 | .pa_end = 0x483101ff, |
| 803 | .flags = ADDR_TYPE_RT |
| 804 | }, |
| 805 | }; |
| 806 | |
| 807 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
| 808 | .master = &omap3xxx_l4_wkup_hwmod, |
| 809 | .slave = &omap3xxx_gpio1_hwmod, |
| 810 | .addr = omap3xxx_gpio1_addrs, |
| 811 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), |
| 812 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 813 | }; |
| 814 | |
| 815 | /* l4_per -> gpio2 */ |
| 816 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { |
| 817 | { |
| 818 | .pa_start = 0x49050000, |
| 819 | .pa_end = 0x490501ff, |
| 820 | .flags = ADDR_TYPE_RT |
| 821 | }, |
| 822 | }; |
| 823 | |
| 824 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
| 825 | .master = &omap3xxx_l4_per_hwmod, |
| 826 | .slave = &omap3xxx_gpio2_hwmod, |
| 827 | .addr = omap3xxx_gpio2_addrs, |
| 828 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), |
| 829 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 830 | }; |
| 831 | |
| 832 | /* l4_per -> gpio3 */ |
| 833 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { |
| 834 | { |
| 835 | .pa_start = 0x49052000, |
| 836 | .pa_end = 0x490521ff, |
| 837 | .flags = ADDR_TYPE_RT |
| 838 | }, |
| 839 | }; |
| 840 | |
| 841 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
| 842 | .master = &omap3xxx_l4_per_hwmod, |
| 843 | .slave = &omap3xxx_gpio3_hwmod, |
| 844 | .addr = omap3xxx_gpio3_addrs, |
| 845 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), |
| 846 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 847 | }; |
| 848 | |
| 849 | /* l4_per -> gpio4 */ |
| 850 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { |
| 851 | { |
| 852 | .pa_start = 0x49054000, |
| 853 | .pa_end = 0x490541ff, |
| 854 | .flags = ADDR_TYPE_RT |
| 855 | }, |
| 856 | }; |
| 857 | |
| 858 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
| 859 | .master = &omap3xxx_l4_per_hwmod, |
| 860 | .slave = &omap3xxx_gpio4_hwmod, |
| 861 | .addr = omap3xxx_gpio4_addrs, |
| 862 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), |
| 863 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 864 | }; |
| 865 | |
| 866 | /* l4_per -> gpio5 */ |
| 867 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { |
| 868 | { |
| 869 | .pa_start = 0x49056000, |
| 870 | .pa_end = 0x490561ff, |
| 871 | .flags = ADDR_TYPE_RT |
| 872 | }, |
| 873 | }; |
| 874 | |
| 875 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
| 876 | .master = &omap3xxx_l4_per_hwmod, |
| 877 | .slave = &omap3xxx_gpio5_hwmod, |
| 878 | .addr = omap3xxx_gpio5_addrs, |
| 879 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), |
| 880 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 881 | }; |
| 882 | |
| 883 | /* l4_per -> gpio6 */ |
| 884 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { |
| 885 | { |
| 886 | .pa_start = 0x49058000, |
| 887 | .pa_end = 0x490581ff, |
| 888 | .flags = ADDR_TYPE_RT |
| 889 | }, |
| 890 | }; |
| 891 | |
| 892 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
| 893 | .master = &omap3xxx_l4_per_hwmod, |
| 894 | .slave = &omap3xxx_gpio6_hwmod, |
| 895 | .addr = omap3xxx_gpio6_addrs, |
| 896 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), |
| 897 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 898 | }; |
| 899 | |
| 900 | /* |
| 901 | * 'gpio' class |
| 902 | * general purpose io module |
| 903 | */ |
| 904 | |
| 905 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
| 906 | .rev_offs = 0x0000, |
| 907 | .sysc_offs = 0x0010, |
| 908 | .syss_offs = 0x0014, |
| 909 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 910 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 911 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 912 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 913 | }; |
| 914 | |
| 915 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
| 916 | .name = "gpio", |
| 917 | .sysc = &omap3xxx_gpio_sysc, |
| 918 | .rev = 1, |
| 919 | }; |
| 920 | |
| 921 | /* gpio_dev_attr*/ |
| 922 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 923 | .bank_width = 32, |
| 924 | .dbck_flag = true, |
| 925 | }; |
| 926 | |
| 927 | /* gpio1 */ |
| 928 | static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { |
| 929 | { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ |
| 930 | }; |
| 931 | |
| 932 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
| 933 | { .role = "dbclk", .clk = "gpio1_dbck", }, |
| 934 | }; |
| 935 | |
| 936 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { |
| 937 | &omap3xxx_l4_wkup__gpio1, |
| 938 | }; |
| 939 | |
| 940 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { |
| 941 | .name = "gpio1", |
| 942 | .mpu_irqs = omap3xxx_gpio1_irqs, |
| 943 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), |
| 944 | .main_clk = "gpio1_ick", |
| 945 | .opt_clks = gpio1_opt_clks, |
| 946 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), |
| 947 | .prcm = { |
| 948 | .omap2 = { |
| 949 | .prcm_reg_id = 1, |
| 950 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 951 | .module_offs = WKUP_MOD, |
| 952 | .idlest_reg_id = 1, |
| 953 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
| 954 | }, |
| 955 | }, |
| 956 | .slaves = omap3xxx_gpio1_slaves, |
| 957 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), |
| 958 | .class = &omap3xxx_gpio_hwmod_class, |
| 959 | .dev_attr = &gpio_dev_attr, |
| 960 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 961 | }; |
| 962 | |
| 963 | /* gpio2 */ |
| 964 | static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { |
| 965 | { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ |
| 966 | }; |
| 967 | |
| 968 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
| 969 | { .role = "dbclk", .clk = "gpio2_dbck", }, |
| 970 | }; |
| 971 | |
| 972 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { |
| 973 | &omap3xxx_l4_per__gpio2, |
| 974 | }; |
| 975 | |
| 976 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
| 977 | .name = "gpio2", |
| 978 | .mpu_irqs = omap3xxx_gpio2_irqs, |
| 979 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), |
| 980 | .main_clk = "gpio2_ick", |
| 981 | .opt_clks = gpio2_opt_clks, |
| 982 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), |
| 983 | .prcm = { |
| 984 | .omap2 = { |
| 985 | .prcm_reg_id = 1, |
| 986 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 987 | .module_offs = OMAP3430_PER_MOD, |
| 988 | .idlest_reg_id = 1, |
| 989 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
| 990 | }, |
| 991 | }, |
| 992 | .slaves = omap3xxx_gpio2_slaves, |
| 993 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), |
| 994 | .class = &omap3xxx_gpio_hwmod_class, |
| 995 | .dev_attr = &gpio_dev_attr, |
| 996 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 997 | }; |
| 998 | |
| 999 | /* gpio3 */ |
| 1000 | static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { |
| 1001 | { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ |
| 1002 | }; |
| 1003 | |
| 1004 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
| 1005 | { .role = "dbclk", .clk = "gpio3_dbck", }, |
| 1006 | }; |
| 1007 | |
| 1008 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { |
| 1009 | &omap3xxx_l4_per__gpio3, |
| 1010 | }; |
| 1011 | |
| 1012 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
| 1013 | .name = "gpio3", |
| 1014 | .mpu_irqs = omap3xxx_gpio3_irqs, |
| 1015 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), |
| 1016 | .main_clk = "gpio3_ick", |
| 1017 | .opt_clks = gpio3_opt_clks, |
| 1018 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), |
| 1019 | .prcm = { |
| 1020 | .omap2 = { |
| 1021 | .prcm_reg_id = 1, |
| 1022 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 1023 | .module_offs = OMAP3430_PER_MOD, |
| 1024 | .idlest_reg_id = 1, |
| 1025 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
| 1026 | }, |
| 1027 | }, |
| 1028 | .slaves = omap3xxx_gpio3_slaves, |
| 1029 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), |
| 1030 | .class = &omap3xxx_gpio_hwmod_class, |
| 1031 | .dev_attr = &gpio_dev_attr, |
| 1032 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1033 | }; |
| 1034 | |
| 1035 | /* gpio4 */ |
| 1036 | static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { |
| 1037 | { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ |
| 1038 | }; |
| 1039 | |
| 1040 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
| 1041 | { .role = "dbclk", .clk = "gpio4_dbck", }, |
| 1042 | }; |
| 1043 | |
| 1044 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { |
| 1045 | &omap3xxx_l4_per__gpio4, |
| 1046 | }; |
| 1047 | |
| 1048 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
| 1049 | .name = "gpio4", |
| 1050 | .mpu_irqs = omap3xxx_gpio4_irqs, |
| 1051 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), |
| 1052 | .main_clk = "gpio4_ick", |
| 1053 | .opt_clks = gpio4_opt_clks, |
| 1054 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), |
| 1055 | .prcm = { |
| 1056 | .omap2 = { |
| 1057 | .prcm_reg_id = 1, |
| 1058 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 1059 | .module_offs = OMAP3430_PER_MOD, |
| 1060 | .idlest_reg_id = 1, |
| 1061 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
| 1062 | }, |
| 1063 | }, |
| 1064 | .slaves = omap3xxx_gpio4_slaves, |
| 1065 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), |
| 1066 | .class = &omap3xxx_gpio_hwmod_class, |
| 1067 | .dev_attr = &gpio_dev_attr, |
| 1068 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1069 | }; |
| 1070 | |
| 1071 | /* gpio5 */ |
| 1072 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { |
| 1073 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ |
| 1074 | }; |
| 1075 | |
| 1076 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
| 1077 | { .role = "dbclk", .clk = "gpio5_dbck", }, |
| 1078 | }; |
| 1079 | |
| 1080 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { |
| 1081 | &omap3xxx_l4_per__gpio5, |
| 1082 | }; |
| 1083 | |
| 1084 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
| 1085 | .name = "gpio5", |
| 1086 | .mpu_irqs = omap3xxx_gpio5_irqs, |
| 1087 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), |
| 1088 | .main_clk = "gpio5_ick", |
| 1089 | .opt_clks = gpio5_opt_clks, |
| 1090 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), |
| 1091 | .prcm = { |
| 1092 | .omap2 = { |
| 1093 | .prcm_reg_id = 1, |
| 1094 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 1095 | .module_offs = OMAP3430_PER_MOD, |
| 1096 | .idlest_reg_id = 1, |
| 1097 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
| 1098 | }, |
| 1099 | }, |
| 1100 | .slaves = omap3xxx_gpio5_slaves, |
| 1101 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), |
| 1102 | .class = &omap3xxx_gpio_hwmod_class, |
| 1103 | .dev_attr = &gpio_dev_attr, |
| 1104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1105 | }; |
| 1106 | |
| 1107 | /* gpio6 */ |
| 1108 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { |
| 1109 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ |
| 1110 | }; |
| 1111 | |
| 1112 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
| 1113 | { .role = "dbclk", .clk = "gpio6_dbck", }, |
| 1114 | }; |
| 1115 | |
| 1116 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { |
| 1117 | &omap3xxx_l4_per__gpio6, |
| 1118 | }; |
| 1119 | |
| 1120 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
| 1121 | .name = "gpio6", |
| 1122 | .mpu_irqs = omap3xxx_gpio6_irqs, |
| 1123 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), |
| 1124 | .main_clk = "gpio6_ick", |
| 1125 | .opt_clks = gpio6_opt_clks, |
| 1126 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), |
| 1127 | .prcm = { |
| 1128 | .omap2 = { |
| 1129 | .prcm_reg_id = 1, |
| 1130 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 1131 | .module_offs = OMAP3430_PER_MOD, |
| 1132 | .idlest_reg_id = 1, |
| 1133 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
| 1134 | }, |
| 1135 | }, |
| 1136 | .slaves = omap3xxx_gpio6_slaves, |
| 1137 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), |
| 1138 | .class = &omap3xxx_gpio_hwmod_class, |
| 1139 | .dev_attr = &gpio_dev_attr, |
| 1140 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1141 | }; |
| 1142 | |
G, Manjunath Kondaiah | 01438ab | 2010-12-20 18:27:19 -0800 | [diff] [blame] | 1143 | /* dma_system -> L3 */ |
| 1144 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { |
| 1145 | .master = &omap3xxx_dma_system_hwmod, |
| 1146 | .slave = &omap3xxx_l3_main_hwmod, |
| 1147 | .clk = "core_l3_ick", |
| 1148 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1149 | }; |
| 1150 | |
| 1151 | /* dma attributes */ |
| 1152 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 1153 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 1154 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, |
| 1155 | .lch_count = 32, |
| 1156 | }; |
| 1157 | |
| 1158 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
| 1159 | .rev_offs = 0x0000, |
| 1160 | .sysc_offs = 0x002c, |
| 1161 | .syss_offs = 0x0028, |
| 1162 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 1163 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
| 1164 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), |
| 1165 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1166 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1167 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1168 | }; |
| 1169 | |
| 1170 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
| 1171 | .name = "dma", |
| 1172 | .sysc = &omap3xxx_dma_sysc, |
| 1173 | }; |
| 1174 | |
| 1175 | /* dma_system */ |
| 1176 | static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { |
| 1177 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ |
| 1178 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ |
| 1179 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ |
| 1180 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ |
| 1181 | }; |
| 1182 | |
| 1183 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
| 1184 | { |
| 1185 | .pa_start = 0x48056000, |
| 1186 | .pa_end = 0x4a0560ff, |
| 1187 | .flags = ADDR_TYPE_RT |
| 1188 | }, |
| 1189 | }; |
| 1190 | |
| 1191 | /* dma_system master ports */ |
| 1192 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { |
| 1193 | &omap3xxx_dma_system__l3, |
| 1194 | }; |
| 1195 | |
| 1196 | /* l4_cfg -> dma_system */ |
| 1197 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { |
| 1198 | .master = &omap3xxx_l4_core_hwmod, |
| 1199 | .slave = &omap3xxx_dma_system_hwmod, |
| 1200 | .clk = "core_l4_ick", |
| 1201 | .addr = omap3xxx_dma_system_addrs, |
| 1202 | .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), |
| 1203 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1204 | }; |
| 1205 | |
| 1206 | /* dma_system slave ports */ |
| 1207 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { |
| 1208 | &omap3xxx_l4_core__dma_system, |
| 1209 | }; |
| 1210 | |
| 1211 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { |
| 1212 | .name = "dma", |
| 1213 | .class = &omap3xxx_dma_hwmod_class, |
| 1214 | .mpu_irqs = omap3xxx_dma_system_irqs, |
| 1215 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), |
| 1216 | .main_clk = "core_l3_ick", |
| 1217 | .prcm = { |
| 1218 | .omap2 = { |
| 1219 | .module_offs = CORE_MOD, |
| 1220 | .prcm_reg_id = 1, |
| 1221 | .module_bit = OMAP3430_ST_SDMA_SHIFT, |
| 1222 | .idlest_reg_id = 1, |
| 1223 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, |
| 1224 | }, |
| 1225 | }, |
| 1226 | .slaves = omap3xxx_dma_system_slaves, |
| 1227 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), |
| 1228 | .masters = omap3xxx_dma_system_masters, |
| 1229 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), |
| 1230 | .dev_attr = &dma_dev_attr, |
| 1231 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1232 | .flags = HWMOD_NO_IDLEST, |
| 1233 | }; |
| 1234 | |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 1235 | /* SR common */ |
| 1236 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { |
| 1237 | .clkact_shift = 20, |
| 1238 | }; |
| 1239 | |
| 1240 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
| 1241 | .sysc_offs = 0x24, |
| 1242 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), |
| 1243 | .clockact = CLOCKACT_TEST_ICLK, |
| 1244 | .sysc_fields = &omap34xx_sr_sysc_fields, |
| 1245 | }; |
| 1246 | |
| 1247 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
| 1248 | .name = "smartreflex", |
| 1249 | .sysc = &omap34xx_sr_sysc, |
| 1250 | .rev = 1, |
| 1251 | }; |
| 1252 | |
| 1253 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
| 1254 | .sidle_shift = 24, |
| 1255 | .enwkup_shift = 26 |
| 1256 | }; |
| 1257 | |
| 1258 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
| 1259 | .sysc_offs = 0x38, |
| 1260 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1261 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | |
| 1262 | SYSC_NO_CACHE), |
| 1263 | .sysc_fields = &omap36xx_sr_sysc_fields, |
| 1264 | }; |
| 1265 | |
| 1266 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { |
| 1267 | .name = "smartreflex", |
| 1268 | .sysc = &omap36xx_sr_sysc, |
| 1269 | .rev = 2, |
| 1270 | }; |
| 1271 | |
| 1272 | /* SR1 */ |
| 1273 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { |
| 1274 | &omap3_l4_core__sr1, |
| 1275 | }; |
| 1276 | |
| 1277 | static struct omap_hwmod omap34xx_sr1_hwmod = { |
| 1278 | .name = "sr1_hwmod", |
| 1279 | .class = &omap34xx_smartreflex_hwmod_class, |
| 1280 | .main_clk = "sr1_fck", |
| 1281 | .vdd_name = "mpu", |
| 1282 | .prcm = { |
| 1283 | .omap2 = { |
| 1284 | .prcm_reg_id = 1, |
| 1285 | .module_bit = OMAP3430_EN_SR1_SHIFT, |
| 1286 | .module_offs = WKUP_MOD, |
| 1287 | .idlest_reg_id = 1, |
| 1288 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, |
| 1289 | }, |
| 1290 | }, |
| 1291 | .slaves = omap3_sr1_slaves, |
| 1292 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), |
| 1293 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | |
| 1294 | CHIP_IS_OMAP3430ES3_0 | |
| 1295 | CHIP_IS_OMAP3430ES3_1), |
| 1296 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
| 1297 | }; |
| 1298 | |
| 1299 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
| 1300 | .name = "sr1_hwmod", |
| 1301 | .class = &omap36xx_smartreflex_hwmod_class, |
| 1302 | .main_clk = "sr1_fck", |
| 1303 | .vdd_name = "mpu", |
| 1304 | .prcm = { |
| 1305 | .omap2 = { |
| 1306 | .prcm_reg_id = 1, |
| 1307 | .module_bit = OMAP3430_EN_SR1_SHIFT, |
| 1308 | .module_offs = WKUP_MOD, |
| 1309 | .idlest_reg_id = 1, |
| 1310 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, |
| 1311 | }, |
| 1312 | }, |
| 1313 | .slaves = omap3_sr1_slaves, |
| 1314 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), |
| 1315 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), |
| 1316 | }; |
| 1317 | |
| 1318 | /* SR2 */ |
| 1319 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { |
| 1320 | &omap3_l4_core__sr2, |
| 1321 | }; |
| 1322 | |
| 1323 | static struct omap_hwmod omap34xx_sr2_hwmod = { |
| 1324 | .name = "sr2_hwmod", |
| 1325 | .class = &omap34xx_smartreflex_hwmod_class, |
| 1326 | .main_clk = "sr2_fck", |
| 1327 | .vdd_name = "core", |
| 1328 | .prcm = { |
| 1329 | .omap2 = { |
| 1330 | .prcm_reg_id = 1, |
| 1331 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
| 1332 | .module_offs = WKUP_MOD, |
| 1333 | .idlest_reg_id = 1, |
| 1334 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
| 1335 | }, |
| 1336 | }, |
| 1337 | .slaves = omap3_sr2_slaves, |
| 1338 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), |
| 1339 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | |
| 1340 | CHIP_IS_OMAP3430ES3_0 | |
| 1341 | CHIP_IS_OMAP3430ES3_1), |
| 1342 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
| 1343 | }; |
| 1344 | |
| 1345 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
| 1346 | .name = "sr2_hwmod", |
| 1347 | .class = &omap36xx_smartreflex_hwmod_class, |
| 1348 | .main_clk = "sr2_fck", |
| 1349 | .vdd_name = "core", |
| 1350 | .prcm = { |
| 1351 | .omap2 = { |
| 1352 | .prcm_reg_id = 1, |
| 1353 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
| 1354 | .module_offs = WKUP_MOD, |
| 1355 | .idlest_reg_id = 1, |
| 1356 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
| 1357 | }, |
| 1358 | }, |
| 1359 | .slaves = omap3_sr2_slaves, |
| 1360 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), |
| 1361 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), |
| 1362 | }; |
| 1363 | |
Charulatha V | 0f616a4 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 1364 | /* l4 core -> mcspi1 interface */ |
| 1365 | static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { |
| 1366 | { |
| 1367 | .pa_start = 0x48098000, |
| 1368 | .pa_end = 0x480980ff, |
| 1369 | .flags = ADDR_TYPE_RT, |
| 1370 | }, |
| 1371 | }; |
| 1372 | |
| 1373 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { |
| 1374 | .master = &omap3xxx_l4_core_hwmod, |
| 1375 | .slave = &omap34xx_mcspi1, |
| 1376 | .clk = "mcspi1_ick", |
| 1377 | .addr = omap34xx_mcspi1_addr_space, |
| 1378 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), |
| 1379 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1380 | }; |
| 1381 | |
| 1382 | /* l4 core -> mcspi2 interface */ |
| 1383 | static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { |
| 1384 | { |
| 1385 | .pa_start = 0x4809a000, |
| 1386 | .pa_end = 0x4809a0ff, |
| 1387 | .flags = ADDR_TYPE_RT, |
| 1388 | }, |
| 1389 | }; |
| 1390 | |
| 1391 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { |
| 1392 | .master = &omap3xxx_l4_core_hwmod, |
| 1393 | .slave = &omap34xx_mcspi2, |
| 1394 | .clk = "mcspi2_ick", |
| 1395 | .addr = omap34xx_mcspi2_addr_space, |
| 1396 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), |
| 1397 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1398 | }; |
| 1399 | |
| 1400 | /* l4 core -> mcspi3 interface */ |
| 1401 | static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { |
| 1402 | { |
| 1403 | .pa_start = 0x480b8000, |
| 1404 | .pa_end = 0x480b80ff, |
| 1405 | .flags = ADDR_TYPE_RT, |
| 1406 | }, |
| 1407 | }; |
| 1408 | |
| 1409 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { |
| 1410 | .master = &omap3xxx_l4_core_hwmod, |
| 1411 | .slave = &omap34xx_mcspi3, |
| 1412 | .clk = "mcspi3_ick", |
| 1413 | .addr = omap34xx_mcspi3_addr_space, |
| 1414 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), |
| 1415 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1416 | }; |
| 1417 | |
| 1418 | /* l4 core -> mcspi4 interface */ |
| 1419 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { |
| 1420 | { |
| 1421 | .pa_start = 0x480ba000, |
| 1422 | .pa_end = 0x480ba0ff, |
| 1423 | .flags = ADDR_TYPE_RT, |
| 1424 | }, |
| 1425 | }; |
| 1426 | |
| 1427 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { |
| 1428 | .master = &omap3xxx_l4_core_hwmod, |
| 1429 | .slave = &omap34xx_mcspi4, |
| 1430 | .clk = "mcspi4_ick", |
| 1431 | .addr = omap34xx_mcspi4_addr_space, |
| 1432 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), |
| 1433 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1434 | }; |
| 1435 | |
| 1436 | /* |
| 1437 | * 'mcspi' class |
| 1438 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 1439 | * bus |
| 1440 | */ |
| 1441 | |
| 1442 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
| 1443 | .rev_offs = 0x0000, |
| 1444 | .sysc_offs = 0x0010, |
| 1445 | .syss_offs = 0x0014, |
| 1446 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1447 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1448 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 1449 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1450 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1451 | }; |
| 1452 | |
| 1453 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
| 1454 | .name = "mcspi", |
| 1455 | .sysc = &omap34xx_mcspi_sysc, |
| 1456 | .rev = OMAP3_MCSPI_REV, |
| 1457 | }; |
| 1458 | |
| 1459 | /* mcspi1 */ |
| 1460 | static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { |
| 1461 | { .name = "irq", .irq = 65 }, |
| 1462 | }; |
| 1463 | |
| 1464 | static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { |
| 1465 | { .name = "tx0", .dma_req = 35 }, |
| 1466 | { .name = "rx0", .dma_req = 36 }, |
| 1467 | { .name = "tx1", .dma_req = 37 }, |
| 1468 | { .name = "rx1", .dma_req = 38 }, |
| 1469 | { .name = "tx2", .dma_req = 39 }, |
| 1470 | { .name = "rx2", .dma_req = 40 }, |
| 1471 | { .name = "tx3", .dma_req = 41 }, |
| 1472 | { .name = "rx3", .dma_req = 42 }, |
| 1473 | }; |
| 1474 | |
| 1475 | static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { |
| 1476 | &omap34xx_l4_core__mcspi1, |
| 1477 | }; |
| 1478 | |
| 1479 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 1480 | .num_chipselect = 4, |
| 1481 | }; |
| 1482 | |
| 1483 | static struct omap_hwmod omap34xx_mcspi1 = { |
| 1484 | .name = "mcspi1", |
| 1485 | .mpu_irqs = omap34xx_mcspi1_mpu_irqs, |
| 1486 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), |
| 1487 | .sdma_reqs = omap34xx_mcspi1_sdma_reqs, |
| 1488 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), |
| 1489 | .main_clk = "mcspi1_fck", |
| 1490 | .prcm = { |
| 1491 | .omap2 = { |
| 1492 | .module_offs = CORE_MOD, |
| 1493 | .prcm_reg_id = 1, |
| 1494 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1495 | .idlest_reg_id = 1, |
| 1496 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, |
| 1497 | }, |
| 1498 | }, |
| 1499 | .slaves = omap34xx_mcspi1_slaves, |
| 1500 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), |
| 1501 | .class = &omap34xx_mcspi_class, |
| 1502 | .dev_attr = &omap_mcspi1_dev_attr, |
| 1503 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1504 | }; |
| 1505 | |
| 1506 | /* mcspi2 */ |
| 1507 | static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { |
| 1508 | { .name = "irq", .irq = 66 }, |
| 1509 | }; |
| 1510 | |
| 1511 | static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { |
| 1512 | { .name = "tx0", .dma_req = 43 }, |
| 1513 | { .name = "rx0", .dma_req = 44 }, |
| 1514 | { .name = "tx1", .dma_req = 45 }, |
| 1515 | { .name = "rx1", .dma_req = 46 }, |
| 1516 | }; |
| 1517 | |
| 1518 | static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { |
| 1519 | &omap34xx_l4_core__mcspi2, |
| 1520 | }; |
| 1521 | |
| 1522 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 1523 | .num_chipselect = 2, |
| 1524 | }; |
| 1525 | |
| 1526 | static struct omap_hwmod omap34xx_mcspi2 = { |
| 1527 | .name = "mcspi2", |
| 1528 | .mpu_irqs = omap34xx_mcspi2_mpu_irqs, |
| 1529 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), |
| 1530 | .sdma_reqs = omap34xx_mcspi2_sdma_reqs, |
| 1531 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), |
| 1532 | .main_clk = "mcspi2_fck", |
| 1533 | .prcm = { |
| 1534 | .omap2 = { |
| 1535 | .module_offs = CORE_MOD, |
| 1536 | .prcm_reg_id = 1, |
| 1537 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1538 | .idlest_reg_id = 1, |
| 1539 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, |
| 1540 | }, |
| 1541 | }, |
| 1542 | .slaves = omap34xx_mcspi2_slaves, |
| 1543 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), |
| 1544 | .class = &omap34xx_mcspi_class, |
| 1545 | .dev_attr = &omap_mcspi2_dev_attr, |
| 1546 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1547 | }; |
| 1548 | |
| 1549 | /* mcspi3 */ |
| 1550 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { |
| 1551 | { .name = "irq", .irq = 91 }, /* 91 */ |
| 1552 | }; |
| 1553 | |
| 1554 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { |
| 1555 | { .name = "tx0", .dma_req = 15 }, |
| 1556 | { .name = "rx0", .dma_req = 16 }, |
| 1557 | { .name = "tx1", .dma_req = 23 }, |
| 1558 | { .name = "rx1", .dma_req = 24 }, |
| 1559 | }; |
| 1560 | |
| 1561 | static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { |
| 1562 | &omap34xx_l4_core__mcspi3, |
| 1563 | }; |
| 1564 | |
| 1565 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
| 1566 | .num_chipselect = 2, |
| 1567 | }; |
| 1568 | |
| 1569 | static struct omap_hwmod omap34xx_mcspi3 = { |
| 1570 | .name = "mcspi3", |
| 1571 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, |
| 1572 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), |
| 1573 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, |
| 1574 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), |
| 1575 | .main_clk = "mcspi3_fck", |
| 1576 | .prcm = { |
| 1577 | .omap2 = { |
| 1578 | .module_offs = CORE_MOD, |
| 1579 | .prcm_reg_id = 1, |
| 1580 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1581 | .idlest_reg_id = 1, |
| 1582 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, |
| 1583 | }, |
| 1584 | }, |
| 1585 | .slaves = omap34xx_mcspi3_slaves, |
| 1586 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), |
| 1587 | .class = &omap34xx_mcspi_class, |
| 1588 | .dev_attr = &omap_mcspi3_dev_attr, |
| 1589 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1590 | }; |
| 1591 | |
| 1592 | /* SPI4 */ |
| 1593 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { |
| 1594 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ |
| 1595 | }; |
| 1596 | |
| 1597 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
| 1598 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ |
| 1599 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ |
| 1600 | }; |
| 1601 | |
| 1602 | static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { |
| 1603 | &omap34xx_l4_core__mcspi4, |
| 1604 | }; |
| 1605 | |
| 1606 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
| 1607 | .num_chipselect = 1, |
| 1608 | }; |
| 1609 | |
| 1610 | static struct omap_hwmod omap34xx_mcspi4 = { |
| 1611 | .name = "mcspi4", |
| 1612 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, |
| 1613 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), |
| 1614 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, |
| 1615 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), |
| 1616 | .main_clk = "mcspi4_fck", |
| 1617 | .prcm = { |
| 1618 | .omap2 = { |
| 1619 | .module_offs = CORE_MOD, |
| 1620 | .prcm_reg_id = 1, |
| 1621 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1622 | .idlest_reg_id = 1, |
| 1623 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, |
| 1624 | }, |
| 1625 | }, |
| 1626 | .slaves = omap34xx_mcspi4_slaves, |
| 1627 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), |
| 1628 | .class = &omap34xx_mcspi_class, |
| 1629 | .dev_attr = &omap_mcspi4_dev_attr, |
| 1630 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 1631 | }; |
| 1632 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1633 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1634 | &omap3xxx_l3_main_hwmod, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1635 | &omap3xxx_l4_core_hwmod, |
| 1636 | &omap3xxx_l4_per_hwmod, |
| 1637 | &omap3xxx_l4_wkup_hwmod, |
| 1638 | &omap3xxx_mpu_hwmod, |
Kevin Hilman | 540064b | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1639 | &omap3xxx_iva_hwmod, |
Varadarajan, Charulatha | 6b667f8 | 2010-09-23 20:02:38 +0530 | [diff] [blame] | 1640 | &omap3xxx_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1641 | &omap3xxx_uart1_hwmod, |
| 1642 | &omap3xxx_uart2_hwmod, |
| 1643 | &omap3xxx_uart3_hwmod, |
| 1644 | &omap3xxx_uart4_hwmod, |
Rajendra Nayak | 4fe20e9 | 2010-09-21 19:37:13 +0530 | [diff] [blame] | 1645 | &omap3xxx_i2c1_hwmod, |
| 1646 | &omap3xxx_i2c2_hwmod, |
| 1647 | &omap3xxx_i2c3_hwmod, |
Thara Gopinath | d344272 | 2010-05-29 22:02:24 +0530 | [diff] [blame] | 1648 | &omap34xx_sr1_hwmod, |
| 1649 | &omap34xx_sr2_hwmod, |
| 1650 | &omap36xx_sr1_hwmod, |
| 1651 | &omap36xx_sr2_hwmod, |
| 1652 | |
Varadarajan, Charulatha | 70034d3 | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 1653 | |
| 1654 | /* gpio class */ |
| 1655 | &omap3xxx_gpio1_hwmod, |
| 1656 | &omap3xxx_gpio2_hwmod, |
| 1657 | &omap3xxx_gpio3_hwmod, |
| 1658 | &omap3xxx_gpio4_hwmod, |
| 1659 | &omap3xxx_gpio5_hwmod, |
| 1660 | &omap3xxx_gpio6_hwmod, |
G, Manjunath Kondaiah | 01438ab | 2010-12-20 18:27:19 -0800 | [diff] [blame] | 1661 | |
| 1662 | /* dma_system class*/ |
| 1663 | &omap3xxx_dma_system_hwmod, |
Charulatha V | 0f616a4 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 1664 | |
| 1665 | /* mcspi class */ |
| 1666 | &omap34xx_mcspi1, |
| 1667 | &omap34xx_mcspi2, |
| 1668 | &omap34xx_mcspi3, |
| 1669 | &omap34xx_mcspi4, |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1670 | NULL, |
| 1671 | }; |
| 1672 | |
| 1673 | int __init omap3xxx_hwmod_init(void) |
| 1674 | { |
| 1675 | return omap_hwmod_init(omap3xxx_hwmods); |
| 1676 | } |