Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 Power Management Routines |
| 3 | * |
| 4 | * Copyright (C) 2006-2008 Nokia Corporation |
| 5 | * Tony Lindgren <tony@atomide.com> |
| 6 | * Jouni Hogander |
| 7 | * |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 8 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 9 | * Rajendra Nayak <rnayak@ti.com> |
| 10 | * |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 11 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 12 | * Richard Woodruff <r-woodruff2@ti.com> |
| 13 | * |
| 14 | * Based on pm.c for omap1 |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/pm.h> |
| 22 | #include <linux/suspend.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/list.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/gpio.h> |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 28 | #include <linux/clk.h> |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 29 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 31 | #include <linux/console.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 32 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 33 | #include <plat/sram.h> |
Paul Walmsley | 1540f214 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 34 | #include "clockdomain.h" |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 35 | #include "powerdomain.h" |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 36 | #include <plat/serial.h> |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 37 | #include <plat/sdrc.h> |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 38 | #include <plat/prcm.h> |
| 39 | #include <plat/gpmc.h> |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 40 | #include <plat/dma.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 41 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 42 | #include <asm/tlbflush.h> |
| 43 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 44 | #include "cm2xxx_3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 45 | #include "cm-regbits-34xx.h" |
| 46 | #include "prm-regbits-34xx.h" |
| 47 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 48 | #include "prm2xxx_3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 49 | #include "pm.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 50 | #include "sdrc.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 51 | #include "control.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 52 | |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 53 | #ifdef CONFIG_SUSPEND |
| 54 | static suspend_state_t suspend_state = PM_SUSPEND_ON; |
| 55 | static inline bool is_suspending(void) |
| 56 | { |
| 57 | return (suspend_state != PM_SUSPEND_ON); |
| 58 | } |
| 59 | #else |
| 60 | static inline bool is_suspending(void) |
| 61 | { |
| 62 | return false; |
| 63 | } |
| 64 | #endif |
| 65 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 66 | /* Scratchpad offsets */ |
Kevin Hilman | de65815 | 2010-10-08 22:43:45 +0000 | [diff] [blame] | 67 | #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 |
| 68 | #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 |
| 69 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 70 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 71 | /* pm34xx errata defined in pm.h */ |
| 72 | u16 pm34xx_errata; |
| 73 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 74 | struct power_state { |
| 75 | struct powerdomain *pwrdm; |
| 76 | u32 next_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 77 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 78 | u32 saved_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 79 | #endif |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 80 | struct list_head node; |
| 81 | }; |
| 82 | |
| 83 | static LIST_HEAD(pwrst_list); |
| 84 | |
| 85 | static void (*_omap_sram_idle)(u32 *addr, int save_state); |
| 86 | |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 87 | static int (*_omap_save_secure_sram)(u32 *addr); |
| 88 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 89 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
| 90 | static struct powerdomain *core_pwrdm, *per_pwrdm; |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 91 | static struct powerdomain *cam_pwrdm; |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 92 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 93 | static inline void omap3_per_save_context(void) |
| 94 | { |
| 95 | omap_gpio_save_context(); |
| 96 | } |
| 97 | |
| 98 | static inline void omap3_per_restore_context(void) |
| 99 | { |
| 100 | omap_gpio_restore_context(); |
| 101 | } |
| 102 | |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 103 | static void omap3_enable_io_chain(void) |
| 104 | { |
| 105 | int timeout = 0; |
| 106 | |
| 107 | if (omap_rev() >= OMAP3430_REV_ES3_1) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 108 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 109 | PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 110 | /* Do a readback to assure write has been done */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 111 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 112 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 113 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 114 | OMAP3430_ST_IO_CHAIN_MASK)) { |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 115 | timeout++; |
| 116 | if (timeout > 1000) { |
| 117 | printk(KERN_ERR "Wake up daisy chain " |
| 118 | "activation failed.\n"); |
| 119 | return; |
| 120 | } |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 121 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
Kevin Hilman | 0b96a3a | 2010-06-09 13:53:09 +0300 | [diff] [blame] | 122 | WKUP_MOD, PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 123 | } |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static void omap3_disable_io_chain(void) |
| 128 | { |
| 129 | if (omap_rev() >= OMAP3430_REV_ES3_1) |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 130 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 131 | PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 132 | } |
| 133 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 134 | static void omap3_core_save_context(void) |
| 135 | { |
Paul Walmsley | 596efe4 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 136 | omap3_ctrl_save_padconf(); |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * Force write last pad into memory, as this can fail in some |
Jean Pihet | 8352129 | 2010-12-18 16:44:46 +0100 | [diff] [blame] | 140 | * cases according to errata 1.157, 1.185 |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 141 | */ |
| 142 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), |
| 143 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); |
| 144 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 145 | /* Save the Interrupt controller context */ |
| 146 | omap_intc_save_context(); |
| 147 | /* Save the GPMC context */ |
| 148 | omap3_gpmc_save_context(); |
| 149 | /* Save the system control module context, padconf already save above*/ |
| 150 | omap3_control_save_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 151 | omap_dma_global_context_save(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | static void omap3_core_restore_context(void) |
| 155 | { |
| 156 | /* Restore the control module context, padconf restored by h/w */ |
| 157 | omap3_control_restore_context(); |
| 158 | /* Restore the GPMC context */ |
| 159 | omap3_gpmc_restore_context(); |
| 160 | /* Restore the interrupt controller context */ |
| 161 | omap_intc_restore_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 162 | omap_dma_global_context_restore(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 163 | } |
| 164 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 165 | /* |
| 166 | * FIXME: This function should be called before entering off-mode after |
| 167 | * OMAP3 secure services have been accessed. Currently it is only called |
| 168 | * once during boot sequence, but this works as we are not using secure |
| 169 | * services. |
| 170 | */ |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 171 | static void omap3_save_secure_ram_context(void) |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 172 | { |
| 173 | u32 ret; |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 174 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 175 | |
| 176 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 177 | /* |
| 178 | * MPU next state must be set to POWER_ON temporarily, |
| 179 | * otherwise the WFI executed inside the ROM code |
| 180 | * will hang the system. |
| 181 | */ |
| 182 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
| 183 | ret = _omap_save_secure_sram((u32 *) |
| 184 | __pa(omap3_secure_ram_storage)); |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 185 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 186 | /* Following is for error tracking, it should not happen */ |
| 187 | if (ret) { |
| 188 | printk(KERN_ERR "save_secure_sram() returns %08x\n", |
| 189 | ret); |
| 190 | while (1) |
| 191 | ; |
| 192 | } |
| 193 | } |
| 194 | } |
| 195 | |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 196 | /* |
| 197 | * PRCM Interrupt Handler Helper Function |
| 198 | * |
| 199 | * The purpose of this function is to clear any wake-up events latched |
| 200 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event |
| 201 | * may occur whilst attempting to clear a PM_WKST_x register and thus |
| 202 | * set another bit in this register. A while loop is used to ensure |
| 203 | * that any peripheral wake-up events occurring while attempting to |
| 204 | * clear the PM_WKST_x are detected and cleared. |
| 205 | */ |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 206 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 207 | { |
Vikram Pandita | 71a8077 | 2009-07-17 19:33:09 -0500 | [diff] [blame] | 208 | u32 wkst, fclk, iclk, clken; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 209 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
| 210 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; |
| 211 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; |
Paul Walmsley | 5d80597 | 2009-07-22 10:18:07 -0700 | [diff] [blame] | 212 | u16 grpsel_off = (regs == 3) ? |
| 213 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 214 | int c = 0; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 215 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 216 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
| 217 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 218 | if (wkst) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 219 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
| 220 | fclk = omap2_cm_read_mod_reg(module, fclk_off); |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 221 | while (wkst) { |
Vikram Pandita | 71a8077 | 2009-07-17 19:33:09 -0500 | [diff] [blame] | 222 | clken = wkst; |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 223 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
Vikram Pandita | 71a8077 | 2009-07-17 19:33:09 -0500 | [diff] [blame] | 224 | /* |
| 225 | * For USBHOST, we don't know whether HOST1 or |
| 226 | * HOST2 woke us up, so enable both f-clocks |
| 227 | */ |
| 228 | if (module == OMAP3430ES2_USBHOST_MOD) |
| 229 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 230 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
| 231 | omap2_prm_write_mod_reg(wkst, module, wkst_off); |
| 232 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 233 | c++; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 234 | } |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 235 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
| 236 | omap2_cm_write_mod_reg(fclk, module, fclk_off); |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 237 | } |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 238 | |
| 239 | return c; |
| 240 | } |
| 241 | |
| 242 | static int _prcm_int_handle_wakeup(void) |
| 243 | { |
| 244 | int c; |
| 245 | |
| 246 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); |
| 247 | c += prcm_clear_mod_irqs(CORE_MOD, 1); |
| 248 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); |
| 249 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 250 | c += prcm_clear_mod_irqs(CORE_MOD, 3); |
| 251 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); |
| 252 | } |
| 253 | |
| 254 | return c; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | /* |
| 258 | * PRCM Interrupt Handler |
| 259 | * |
| 260 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending |
| 261 | * interrupts from the PRCM for the MPU. These bits must be cleared in |
| 262 | * order to clear the PRCM interrupt. The PRCM interrupt handler is |
| 263 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear |
| 264 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU |
| 265 | * register indicates that a wake-up event is pending for the MPU and |
| 266 | * this bit can only be cleared if the all the wake-up events latched |
| 267 | * in the various PM_WKST_x registers have been cleared. The interrupt |
| 268 | * handler is implemented using a do-while loop so that if a wake-up |
| 269 | * event occurred during the processing of the prcm interrupt handler |
| 270 | * (setting a bit in the corresponding PM_WKST_x register and thus |
| 271 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) |
| 272 | * this would be handled. |
| 273 | */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 274 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) |
| 275 | { |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 276 | u32 irqenable_mpu, irqstatus_mpu; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 277 | int c = 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 278 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 279 | irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 280 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 281 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 282 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 283 | irqstatus_mpu &= irqenable_mpu; |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 284 | |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 285 | do { |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 286 | if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | |
| 287 | OMAP3430_IO_ST_MASK)) { |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 288 | c = _prcm_int_handle_wakeup(); |
| 289 | |
| 290 | /* |
| 291 | * Is the MPU PRCM interrupt handler racing with the |
| 292 | * IVA2 PRCM interrupt handler ? |
| 293 | */ |
| 294 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " |
| 295 | "but no wakeup sources are marked\n"); |
| 296 | } else { |
| 297 | /* XXX we need to expand our PRCM interrupt handler */ |
| 298 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " |
| 299 | "no code to handle it (%08x)\n", irqstatus_mpu); |
| 300 | } |
| 301 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 302 | omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 303 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 304 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 305 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
Kevin Hilman | d6290a3 | 2010-04-26 14:59:09 -0700 | [diff] [blame] | 306 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 307 | irqstatus_mpu &= irqenable_mpu; |
| 308 | |
| 309 | } while (irqstatus_mpu); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 310 | |
| 311 | return IRQ_HANDLED; |
| 312 | } |
| 313 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 314 | static void restore_control_register(u32 val) |
| 315 | { |
| 316 | __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); |
| 317 | } |
| 318 | |
| 319 | /* Function to restore the table entry that was modified for enabling MMU */ |
| 320 | static void restore_table_entry(void) |
| 321 | { |
Manjunath Kondaiah G | 4d63bc1 | 2010-10-08 09:56:11 -0700 | [diff] [blame] | 322 | void __iomem *scratchpad_address; |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 323 | u32 previous_value, control_reg_value; |
| 324 | u32 *address; |
| 325 | |
| 326 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); |
| 327 | |
| 328 | /* Get address of entry that was modified */ |
| 329 | address = (u32 *)__raw_readl(scratchpad_address + |
| 330 | OMAP343X_TABLE_ADDRESS_OFFSET); |
| 331 | /* Get the previous value which needs to be restored */ |
| 332 | previous_value = __raw_readl(scratchpad_address + |
| 333 | OMAP343X_TABLE_VALUE_OFFSET); |
| 334 | address = __va(address); |
| 335 | *address = previous_value; |
| 336 | flush_tlb_all(); |
| 337 | control_reg_value = __raw_readl(scratchpad_address |
| 338 | + OMAP343X_CONTROL_REG_VALUE_OFFSET); |
| 339 | /* This will enable caches and prediction */ |
| 340 | restore_control_register(control_reg_value); |
| 341 | } |
| 342 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 343 | void omap_sram_idle(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 344 | { |
| 345 | /* Variable to tell what needs to be saved and restored |
| 346 | * in omap_sram_idle*/ |
| 347 | /* save_state = 0 => Nothing to save and restored */ |
| 348 | /* save_state = 1 => Only L1 and logic lost */ |
| 349 | /* save_state = 2 => Only L2 lost */ |
| 350 | /* save_state = 3 => L1, L2 and logic lost */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 351 | int save_state = 0; |
| 352 | int mpu_next_state = PWRDM_POWER_ON; |
| 353 | int per_next_state = PWRDM_POWER_ON; |
| 354 | int core_next_state = PWRDM_POWER_ON; |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 355 | int per_going_off; |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 356 | int core_prev_state, per_prev_state; |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 357 | u32 sdrc_pwr = 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 358 | |
| 359 | if (!_omap_sram_idle) |
| 360 | return; |
| 361 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 362 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
| 363 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); |
| 364 | pwrdm_clear_all_prev_pwrst(core_pwrdm); |
| 365 | pwrdm_clear_all_prev_pwrst(per_pwrdm); |
| 366 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 367 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
| 368 | switch (mpu_next_state) { |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 369 | case PWRDM_POWER_ON: |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 370 | case PWRDM_POWER_RET: |
| 371 | /* No need to save context */ |
| 372 | save_state = 0; |
| 373 | break; |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 374 | case PWRDM_POWER_OFF: |
| 375 | save_state = 3; |
| 376 | break; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 377 | default: |
| 378 | /* Invalid state */ |
| 379 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); |
| 380 | return; |
| 381 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 382 | pwrdm_pre_transition(); |
| 383 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 384 | /* NEON control */ |
| 385 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 386 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 387 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 388 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 389 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 390 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
Kevin Hilman | d5c47d7 | 2010-08-10 16:04:35 -0700 | [diff] [blame] | 391 | if (omap3_has_io_wakeup() && |
| 392 | (per_next_state < PWRDM_POWER_ON || |
| 393 | core_next_state < PWRDM_POWER_ON)) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 394 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 395 | omap3_enable_io_chain(); |
| 396 | } |
| 397 | |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 398 | /* Block console output in case it is on one of the OMAP UARTs */ |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 399 | if (!is_suspending()) |
| 400 | if (per_next_state < PWRDM_POWER_ON || |
| 401 | core_next_state < PWRDM_POWER_ON) |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 402 | if (!console_trylock()) |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 403 | goto console_still_active; |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 404 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 405 | /* PER */ |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 406 | if (per_next_state < PWRDM_POWER_ON) { |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 407 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 408 | omap_uart_prepare_idle(2); |
Govindraj.R | cd4f1fa | 2010-09-27 20:20:32 +0530 | [diff] [blame] | 409 | omap_uart_prepare_idle(3); |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 410 | omap2_gpio_prepare_for_idle(per_going_off); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 411 | if (per_next_state == PWRDM_POWER_OFF) |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 412 | omap3_per_save_context(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | /* CORE */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 416 | if (core_next_state < PWRDM_POWER_ON) { |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 417 | omap_uart_prepare_idle(0); |
| 418 | omap_uart_prepare_idle(1); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 419 | if (core_next_state == PWRDM_POWER_OFF) { |
| 420 | omap3_core_save_context(); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 421 | omap3_cm_save_context(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 422 | } |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 423 | } |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 424 | |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 425 | omap3_intc_prepare_idle(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 426 | |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 427 | /* |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 428 | * On EMU/HS devices ROM code restores a SRDC value |
| 429 | * from scratchpad which has automatic self refresh on timeout |
Jean Pihet | 8352129 | 2010-12-18 16:44:46 +0100 | [diff] [blame] | 430 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 431 | * Hence store/restore the SDRC_POWER register here. |
| 432 | */ |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 433 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
| 434 | omap_type() != OMAP2_DEVICE_TYPE_GP && |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 435 | core_next_state == PWRDM_POWER_OFF) |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 436 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 437 | |
| 438 | /* |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 439 | * omap3_arm_context is the location where ARM registers |
| 440 | * get saved. The restore path then reads from this |
| 441 | * location and restores them back. |
| 442 | */ |
| 443 | _omap_sram_idle(omap3_arm_context, save_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 444 | cpu_init(); |
| 445 | |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 446 | /* Restore normal SDRC POWER settings */ |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 447 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
| 448 | omap_type() != OMAP2_DEVICE_TYPE_GP && |
| 449 | core_next_state == PWRDM_POWER_OFF) |
| 450 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); |
| 451 | |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 452 | /* Restore table entry modified during MMU restoration */ |
| 453 | if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) |
| 454 | restore_table_entry(); |
| 455 | |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 456 | /* CORE */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 457 | if (core_next_state < PWRDM_POWER_ON) { |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 458 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
| 459 | if (core_prev_state == PWRDM_POWER_OFF) { |
| 460 | omap3_core_restore_context(); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 461 | omap3_cm_restore_context(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 462 | omap3_sram_restore_context(); |
Kalle Jokiniemi | 8a917d2 | 2009-05-13 13:32:11 +0300 | [diff] [blame] | 463 | omap2_sms_restore_context(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 464 | } |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 465 | omap_uart_resume_idle(0); |
| 466 | omap_uart_resume_idle(1); |
| 467 | if (core_next_state == PWRDM_POWER_OFF) |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 468 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 469 | OMAP3430_GR_MOD, |
| 470 | OMAP3_PRM_VOLTCTRL_OFFSET); |
| 471 | } |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 472 | omap3_intc_resume_idle(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 473 | |
| 474 | /* PER */ |
| 475 | if (per_next_state < PWRDM_POWER_ON) { |
| 476 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); |
Kevin Hilman | 43ffcd9 | 2009-01-27 11:09:24 -0800 | [diff] [blame] | 477 | omap2_gpio_resume_after_idle(); |
| 478 | if (per_prev_state == PWRDM_POWER_OFF) |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 479 | omap3_per_restore_context(); |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 480 | omap_uart_resume_idle(2); |
Govindraj.R | cd4f1fa | 2010-09-27 20:20:32 +0530 | [diff] [blame] | 481 | omap_uart_resume_idle(3); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 482 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 483 | |
Kevin Hilman | e83df17 | 2010-12-08 22:40:40 +0000 | [diff] [blame] | 484 | if (!is_suspending()) |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 485 | console_unlock(); |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 486 | |
| 487 | console_still_active: |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 488 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
Kevin Hilman | 58a5559 | 2010-08-16 09:21:19 +0300 | [diff] [blame] | 489 | if (omap3_has_io_wakeup() && |
| 490 | (per_next_state < PWRDM_POWER_ON || |
| 491 | core_next_state < PWRDM_POWER_ON)) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 492 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
| 493 | PM_WKEN); |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 494 | omap3_disable_io_chain(); |
| 495 | } |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 496 | |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 497 | pwrdm_post_transition(); |
| 498 | |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 499 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 500 | } |
| 501 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 502 | int omap3_can_sleep(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 503 | { |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 504 | if (!sleep_while_idle) |
| 505 | return 0; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 506 | if (!omap_uart_can_sleep()) |
| 507 | return 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 508 | return 1; |
| 509 | } |
| 510 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 511 | static void omap3_pm_idle(void) |
| 512 | { |
| 513 | local_irq_disable(); |
| 514 | local_fiq_disable(); |
| 515 | |
| 516 | if (!omap3_can_sleep()) |
| 517 | goto out; |
| 518 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 519 | if (omap_irq_pending() || need_resched()) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 520 | goto out; |
| 521 | |
| 522 | omap_sram_idle(); |
| 523 | |
| 524 | out: |
| 525 | local_fiq_enable(); |
| 526 | local_irq_enable(); |
| 527 | } |
| 528 | |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 529 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 530 | static int omap3_pm_suspend(void) |
| 531 | { |
| 532 | struct power_state *pwrst; |
| 533 | int state, ret = 0; |
| 534 | |
Ari Kauppi | 8e2efde | 2010-03-23 09:04:59 +0200 | [diff] [blame] | 535 | if (wakeup_timer_seconds || wakeup_timer_milliseconds) |
| 536 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds, |
| 537 | wakeup_timer_milliseconds); |
Kevin Hilman | d7814e4 | 2009-10-06 14:30:23 -0700 | [diff] [blame] | 538 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 539 | /* Read current next_pwrsts */ |
| 540 | list_for_each_entry(pwrst, &pwrst_list, node) |
| 541 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
| 542 | /* Set ones wanted by suspend */ |
| 543 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 544 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 545 | goto restore; |
| 546 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) |
| 547 | goto restore; |
| 548 | } |
| 549 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 550 | omap_uart_prepare_suspend(); |
Tero Kristo | 2bbe3af | 2009-10-23 19:03:48 +0300 | [diff] [blame] | 551 | omap3_intc_suspend(); |
| 552 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 553 | omap_sram_idle(); |
| 554 | |
| 555 | restore: |
| 556 | /* Restore next_pwrsts */ |
| 557 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 558 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
| 559 | if (state > pwrst->next_state) { |
| 560 | printk(KERN_INFO "Powerdomain (%s) didn't enter " |
| 561 | "target state %d\n", |
| 562 | pwrst->pwrdm->name, pwrst->next_state); |
| 563 | ret = -1; |
| 564 | } |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 565 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 566 | } |
| 567 | if (ret) |
| 568 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); |
| 569 | else |
| 570 | printk(KERN_INFO "Successfully put all powerdomains " |
| 571 | "to target state\n"); |
| 572 | |
| 573 | return ret; |
| 574 | } |
| 575 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 576 | static int omap3_pm_enter(suspend_state_t unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 577 | { |
| 578 | int ret = 0; |
| 579 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 580 | switch (suspend_state) { |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 581 | case PM_SUSPEND_STANDBY: |
| 582 | case PM_SUSPEND_MEM: |
| 583 | ret = omap3_pm_suspend(); |
| 584 | break; |
| 585 | default: |
| 586 | ret = -EINVAL; |
| 587 | } |
| 588 | |
| 589 | return ret; |
| 590 | } |
| 591 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 592 | /* Hooks to enable / disable UART interrupts during suspend */ |
| 593 | static int omap3_pm_begin(suspend_state_t state) |
| 594 | { |
Jean Pihet | c166381 | 2010-12-09 18:39:58 +0100 | [diff] [blame] | 595 | disable_hlt(); |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 596 | suspend_state = state; |
| 597 | omap_uart_enable_irqs(0); |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static void omap3_pm_end(void) |
| 602 | { |
| 603 | suspend_state = PM_SUSPEND_ON; |
| 604 | omap_uart_enable_irqs(1); |
Jean Pihet | c166381 | 2010-12-09 18:39:58 +0100 | [diff] [blame] | 605 | enable_hlt(); |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 606 | return; |
| 607 | } |
| 608 | |
Lionel Debroux | 2f55ac0 | 2010-11-16 14:14:02 +0100 | [diff] [blame] | 609 | static const struct platform_suspend_ops omap_pm_ops = { |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 610 | .begin = omap3_pm_begin, |
| 611 | .end = omap3_pm_end, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 612 | .enter = omap3_pm_enter, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 613 | .valid = suspend_valid_only_mem, |
| 614 | }; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 615 | #endif /* CONFIG_SUSPEND */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 616 | |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 617 | |
| 618 | /** |
| 619 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into |
| 620 | * retention |
| 621 | * |
| 622 | * In cases where IVA2 is activated by bootcode, it may prevent |
| 623 | * full-chip retention or off-mode because it is not idle. This |
| 624 | * function forces the IVA2 into idle state so it can go |
| 625 | * into retention/off and thus allow full-chip retention/off. |
| 626 | * |
| 627 | **/ |
| 628 | static void __init omap3_iva_idle(void) |
| 629 | { |
| 630 | /* ensure IVA2 clock is disabled */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 631 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 632 | |
| 633 | /* if no clock activity, nothing else to do */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 634 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 635 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
| 636 | return; |
| 637 | |
| 638 | /* Reset IVA2 */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 639 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 640 | OMAP3430_RST2_IVA2_MASK | |
| 641 | OMAP3430_RST3_IVA2_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 642 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 643 | |
| 644 | /* Enable IVA2 clock */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 645 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 646 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 647 | |
| 648 | /* Set IVA2 boot mode to 'idle' */ |
| 649 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, |
| 650 | OMAP343X_CONTROL_IVA2_BOOTMOD); |
| 651 | |
| 652 | /* Un-reset IVA2 */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 653 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 654 | |
| 655 | /* Disable IVA2 clock */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 656 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 657 | |
| 658 | /* Reset IVA2 */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 659 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 660 | OMAP3430_RST2_IVA2_MASK | |
| 661 | OMAP3430_RST3_IVA2_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 662 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 663 | } |
| 664 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 665 | static void __init omap3_d2d_idle(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 666 | { |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 667 | u16 mask, padconf; |
| 668 | |
| 669 | /* In a stand alone OMAP3430 where there is not a stacked |
| 670 | * modem for the D2D Idle Ack and D2D MStandby must be pulled |
| 671 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and |
| 672 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ |
| 673 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ |
| 674 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); |
| 675 | padconf |= mask; |
| 676 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); |
| 677 | |
| 678 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); |
| 679 | padconf |= mask; |
| 680 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); |
| 681 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 682 | /* reset modem */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 683 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 684 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
Abhijit Pagare | 3790300 | 2010-01-26 20:12:51 -0700 | [diff] [blame] | 685 | CORE_MOD, OMAP2_RM_RSTCTRL); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 686 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 687 | } |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 688 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 689 | static void __init prcm_setup_regs(void) |
| 690 | { |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 691 | u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? |
| 692 | OMAP3630_AUTO_UART4_MASK : 0; |
| 693 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
| 694 | OMAP3630_EN_UART4_MASK : 0; |
| 695 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? |
| 696 | OMAP3630_GRPSEL_UART4_MASK : 0; |
| 697 | |
| 698 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 699 | /* XXX Reset all wkdeps. This should be done when initializing |
| 700 | * powerdomains */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 701 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); |
| 702 | omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); |
| 703 | omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); |
| 704 | omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); |
| 705 | omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); |
| 706 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 707 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 708 | omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); |
| 709 | omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 710 | } else |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 711 | omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 712 | |
| 713 | /* |
| 714 | * Enable interface clock autoidle for all modules. |
| 715 | * Note that in the long run this should be done by clockfw |
| 716 | */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 717 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 718 | OMAP3430_AUTO_MODEM_MASK | |
| 719 | OMAP3430ES2_AUTO_MMC3_MASK | |
| 720 | OMAP3430ES2_AUTO_ICR_MASK | |
| 721 | OMAP3430_AUTO_AES2_MASK | |
| 722 | OMAP3430_AUTO_SHA12_MASK | |
| 723 | OMAP3430_AUTO_DES2_MASK | |
| 724 | OMAP3430_AUTO_MMC2_MASK | |
| 725 | OMAP3430_AUTO_MMC1_MASK | |
| 726 | OMAP3430_AUTO_MSPRO_MASK | |
| 727 | OMAP3430_AUTO_HDQ_MASK | |
| 728 | OMAP3430_AUTO_MCSPI4_MASK | |
| 729 | OMAP3430_AUTO_MCSPI3_MASK | |
| 730 | OMAP3430_AUTO_MCSPI2_MASK | |
| 731 | OMAP3430_AUTO_MCSPI1_MASK | |
| 732 | OMAP3430_AUTO_I2C3_MASK | |
| 733 | OMAP3430_AUTO_I2C2_MASK | |
| 734 | OMAP3430_AUTO_I2C1_MASK | |
| 735 | OMAP3430_AUTO_UART2_MASK | |
| 736 | OMAP3430_AUTO_UART1_MASK | |
| 737 | OMAP3430_AUTO_GPT11_MASK | |
| 738 | OMAP3430_AUTO_GPT10_MASK | |
| 739 | OMAP3430_AUTO_MCBSP5_MASK | |
| 740 | OMAP3430_AUTO_MCBSP1_MASK | |
| 741 | OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ |
| 742 | OMAP3430_AUTO_MAILBOXES_MASK | |
| 743 | OMAP3430_AUTO_OMAPCTRL_MASK | |
| 744 | OMAP3430ES1_AUTO_FSHOSTUSB_MASK | |
| 745 | OMAP3430_AUTO_HSOTGUSB_MASK | |
| 746 | OMAP3430_AUTO_SAD2D_MASK | |
| 747 | OMAP3430_AUTO_SSI_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 748 | CORE_MOD, CM_AUTOIDLE1); |
| 749 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 750 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 751 | OMAP3430_AUTO_PKA_MASK | |
| 752 | OMAP3430_AUTO_AES1_MASK | |
| 753 | OMAP3430_AUTO_RNG_MASK | |
| 754 | OMAP3430_AUTO_SHA11_MASK | |
| 755 | OMAP3430_AUTO_DES1_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 756 | CORE_MOD, CM_AUTOIDLE2); |
| 757 | |
| 758 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 759 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 760 | OMAP3430_AUTO_MAD2D_MASK | |
| 761 | OMAP3430ES2_AUTO_USBTLL_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 762 | CORE_MOD, CM_AUTOIDLE3); |
| 763 | } |
| 764 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 765 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 766 | OMAP3430_AUTO_WDT2_MASK | |
| 767 | OMAP3430_AUTO_WDT1_MASK | |
| 768 | OMAP3430_AUTO_GPIO1_MASK | |
| 769 | OMAP3430_AUTO_32KSYNC_MASK | |
| 770 | OMAP3430_AUTO_GPT12_MASK | |
| 771 | OMAP3430_AUTO_GPT1_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 772 | WKUP_MOD, CM_AUTOIDLE); |
| 773 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 774 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 775 | OMAP3430_AUTO_DSS_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 776 | OMAP3430_DSS_MOD, |
| 777 | CM_AUTOIDLE); |
| 778 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 779 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 780 | OMAP3430_AUTO_CAM_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 781 | OMAP3430_CAM_MOD, |
| 782 | CM_AUTOIDLE); |
| 783 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 784 | omap2_cm_write_mod_reg( |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 785 | omap3630_auto_uart4_mask | |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 786 | OMAP3430_AUTO_GPIO6_MASK | |
| 787 | OMAP3430_AUTO_GPIO5_MASK | |
| 788 | OMAP3430_AUTO_GPIO4_MASK | |
| 789 | OMAP3430_AUTO_GPIO3_MASK | |
| 790 | OMAP3430_AUTO_GPIO2_MASK | |
| 791 | OMAP3430_AUTO_WDT3_MASK | |
| 792 | OMAP3430_AUTO_UART3_MASK | |
| 793 | OMAP3430_AUTO_GPT9_MASK | |
| 794 | OMAP3430_AUTO_GPT8_MASK | |
| 795 | OMAP3430_AUTO_GPT7_MASK | |
| 796 | OMAP3430_AUTO_GPT6_MASK | |
| 797 | OMAP3430_AUTO_GPT5_MASK | |
| 798 | OMAP3430_AUTO_GPT4_MASK | |
| 799 | OMAP3430_AUTO_GPT3_MASK | |
| 800 | OMAP3430_AUTO_GPT2_MASK | |
| 801 | OMAP3430_AUTO_MCBSP4_MASK | |
| 802 | OMAP3430_AUTO_MCBSP3_MASK | |
| 803 | OMAP3430_AUTO_MCBSP2_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 804 | OMAP3430_PER_MOD, |
| 805 | CM_AUTOIDLE); |
| 806 | |
| 807 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 808 | omap2_cm_write_mod_reg( |
Paul Walmsley | 2bc4ef7 | 2010-05-18 18:47:24 -0600 | [diff] [blame] | 809 | OMAP3430ES2_AUTO_USBHOST_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 810 | OMAP3430ES2_USBHOST_MOD, |
| 811 | CM_AUTOIDLE); |
| 812 | } |
| 813 | |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 814 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
Tero Kristo | b296c81 | 2009-10-23 19:03:49 +0300 | [diff] [blame] | 815 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 816 | /* |
| 817 | * Set all plls to autoidle. This is needed until autoidle is |
| 818 | * enabled by clockfw |
| 819 | */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 820 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 821 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 822 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 823 | MPU_MOD, |
| 824 | CM_AUTOIDLE2); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 825 | omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 826 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), |
| 827 | PLL_MOD, |
| 828 | CM_AUTOIDLE); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 829 | omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 830 | PLL_MOD, |
| 831 | CM_AUTOIDLE2); |
| 832 | |
| 833 | /* |
| 834 | * Enable control of expternal oscillator through |
| 835 | * sys_clkreq. In the long run clock framework should |
| 836 | * take care of this. |
| 837 | */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 838 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 839 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
| 840 | OMAP3430_GR_MOD, |
| 841 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
| 842 | |
| 843 | /* setup wakup source */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 844 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 845 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 846 | WKUP_MOD, PM_WKEN); |
| 847 | /* No need to write EN_IO, that is always enabled */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 848 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
Paul Walmsley | 275f675 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 849 | OMAP3430_GRPSEL_GPT1_MASK | |
| 850 | OMAP3430_GRPSEL_GPT12_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 851 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
| 852 | /* For some reason IO doesn't generate wakeup event even if |
| 853 | * it is selected to mpu wakeup goup */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 854 | omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 855 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 856 | |
Subramani Venkatesh | b92c572 | 2009-12-22 15:07:50 +0530 | [diff] [blame] | 857 | /* Enable PM_WKEN to support DSS LPR */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 858 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
Subramani Venkatesh | b92c572 | 2009-12-22 15:07:50 +0530 | [diff] [blame] | 859 | OMAP3430_DSS_MOD, PM_WKEN); |
| 860 | |
Kevin Hilman | b427f92 | 2009-10-22 14:48:13 -0700 | [diff] [blame] | 861 | /* Enable wakeups in PER */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 862 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 863 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
Paul Walmsley | 2fd0f75 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 864 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
| 865 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | |
| 866 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | |
| 867 | OMAP3430_EN_MCBSP4_MASK, |
Kevin Hilman | b427f92 | 2009-10-22 14:48:13 -0700 | [diff] [blame] | 868 | OMAP3430_PER_MOD, PM_WKEN); |
Kevin Hilman | eb350f7 | 2009-09-10 15:53:08 +0000 | [diff] [blame] | 869 | /* and allow them to wake up MPU */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 870 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
Govindraj.R | e586368 | 2010-09-27 20:20:25 +0530 | [diff] [blame] | 871 | OMAP3430_GRPSEL_GPIO2_MASK | |
Paul Walmsley | 275f675 | 2010-05-18 18:40:23 -0600 | [diff] [blame] | 872 | OMAP3430_GRPSEL_GPIO3_MASK | |
| 873 | OMAP3430_GRPSEL_GPIO4_MASK | |
| 874 | OMAP3430_GRPSEL_GPIO5_MASK | |
| 875 | OMAP3430_GRPSEL_GPIO6_MASK | |
| 876 | OMAP3430_GRPSEL_UART3_MASK | |
| 877 | OMAP3430_GRPSEL_MCBSP2_MASK | |
| 878 | OMAP3430_GRPSEL_MCBSP3_MASK | |
| 879 | OMAP3430_GRPSEL_MCBSP4_MASK, |
Kevin Hilman | eb350f7 | 2009-09-10 15:53:08 +0000 | [diff] [blame] | 880 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
| 881 | |
Kevin Hilman | d3fd329 | 2009-05-05 16:34:25 -0700 | [diff] [blame] | 882 | /* Don't attach IVA interrupts */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 883 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
| 884 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
| 885 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
| 886 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); |
Kevin Hilman | d3fd329 | 2009-05-05 16:34:25 -0700 | [diff] [blame] | 887 | |
Kevin Hilman | b1340d1 | 2009-04-27 16:14:54 -0700 | [diff] [blame] | 888 | /* Clear any pending 'reset' flags */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 889 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
| 890 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); |
| 891 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); |
| 892 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); |
| 893 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); |
| 894 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); |
| 895 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); |
Kevin Hilman | b1340d1 | 2009-04-27 16:14:54 -0700 | [diff] [blame] | 896 | |
Kevin Hilman | 014c46d | 2009-04-27 07:50:23 -0700 | [diff] [blame] | 897 | /* Clear any pending PRCM interrupts */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 898 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
Kevin Hilman | 014c46d | 2009-04-27 07:50:23 -0700 | [diff] [blame] | 899 | |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 900 | omap3_iva_idle(); |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 901 | omap3_d2d_idle(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 902 | } |
| 903 | |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 904 | void omap3_pm_off_mode_enable(int enable) |
| 905 | { |
| 906 | struct power_state *pwrst; |
| 907 | u32 state; |
| 908 | |
| 909 | if (enable) |
| 910 | state = PWRDM_POWER_OFF; |
| 911 | else |
| 912 | state = PWRDM_POWER_RET; |
| 913 | |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 914 | #ifdef CONFIG_CPU_IDLE |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 915 | /* |
| 916 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot |
| 917 | * enable OFF mode in a stable form for previous revisions, restrict |
| 918 | * instead to RET |
| 919 | */ |
| 920 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) |
| 921 | omap3_cpuidle_update_states(state, PWRDM_POWER_RET); |
| 922 | else |
| 923 | omap3_cpuidle_update_states(state, state); |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 924 | #endif |
| 925 | |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 926 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 927 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
| 928 | pwrst->pwrdm == core_pwrdm && |
| 929 | state == PWRDM_POWER_OFF) { |
| 930 | pwrst->next_state = PWRDM_POWER_RET; |
| 931 | WARN_ONCE(1, |
| 932 | "%s: Core OFF disabled due to errata i583\n", |
| 933 | __func__); |
| 934 | } else { |
| 935 | pwrst->next_state = state; |
| 936 | } |
| 937 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 938 | } |
| 939 | } |
| 940 | |
Tero Kristo | 68d4778 | 2008-11-26 12:26:24 +0200 | [diff] [blame] | 941 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
| 942 | { |
| 943 | struct power_state *pwrst; |
| 944 | |
| 945 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 946 | if (pwrst->pwrdm == pwrdm) |
| 947 | return pwrst->next_state; |
| 948 | } |
| 949 | return -EINVAL; |
| 950 | } |
| 951 | |
| 952 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) |
| 953 | { |
| 954 | struct power_state *pwrst; |
| 955 | |
| 956 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 957 | if (pwrst->pwrdm == pwrdm) { |
| 958 | pwrst->next_state = state; |
| 959 | return 0; |
| 960 | } |
| 961 | } |
| 962 | return -EINVAL; |
| 963 | } |
| 964 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 965 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 966 | { |
| 967 | struct power_state *pwrst; |
| 968 | |
| 969 | if (!pwrdm->pwrsts) |
| 970 | return 0; |
| 971 | |
Ming Lei | d3d381c | 2009-08-22 21:20:26 +0800 | [diff] [blame] | 972 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 973 | if (!pwrst) |
| 974 | return -ENOMEM; |
| 975 | pwrst->pwrdm = pwrdm; |
| 976 | pwrst->next_state = PWRDM_POWER_RET; |
| 977 | list_add(&pwrst->node, &pwrst_list); |
| 978 | |
| 979 | if (pwrdm_has_hdwr_sar(pwrdm)) |
| 980 | pwrdm_enable_hdwr_sar(pwrdm); |
| 981 | |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 982 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 983 | } |
| 984 | |
| 985 | /* |
| 986 | * Enable hw supervised mode for all clockdomains if it's |
| 987 | * supported. Initiate sleep transition for other clockdomains, if |
| 988 | * they are not used |
| 989 | */ |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 990 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 991 | { |
| 992 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
| 993 | omap2_clkdm_allow_idle(clkdm); |
| 994 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
| 995 | atomic_read(&clkdm->usecount) == 0) |
| 996 | omap2_clkdm_sleep(clkdm); |
| 997 | return 0; |
| 998 | } |
| 999 | |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1000 | void omap_push_sram_idle(void) |
| 1001 | { |
| 1002 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, |
| 1003 | omap34xx_cpu_suspend_sz); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1004 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
| 1005 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, |
| 1006 | save_secure_ram_context_sz); |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1007 | } |
| 1008 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1009 | static void __init pm_errata_configure(void) |
| 1010 | { |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1011 | if (cpu_is_omap3630()) { |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 1012 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1013 | /* Enable the l2 cache toggling in sleep logic */ |
| 1014 | enable_omap3630_toggle_l2_on_restore(); |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 1015 | if (omap_rev() < OMAP3630_REV_ES1_2) |
| 1016 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 1017 | } |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1018 | } |
| 1019 | |
Kevin Hilman | 7cc515f | 2009-06-10 09:02:25 -0700 | [diff] [blame] | 1020 | static int __init omap3_pm_init(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1021 | { |
| 1022 | struct power_state *pwrst, *tmp; |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1023 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1024 | int ret; |
| 1025 | |
| 1026 | if (!cpu_is_omap34xx()) |
| 1027 | return -ENODEV; |
| 1028 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 1029 | pm_errata_configure(); |
| 1030 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1031 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); |
| 1032 | |
| 1033 | /* XXX prcm_setup_regs needs to be before enabling hw |
| 1034 | * supervised mode for powerdomains */ |
| 1035 | prcm_setup_regs(); |
| 1036 | |
| 1037 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, |
| 1038 | (irq_handler_t)prcm_interrupt_handler, |
| 1039 | IRQF_DISABLED, "prcm", NULL); |
| 1040 | if (ret) { |
| 1041 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", |
| 1042 | INT_34XX_PRCM_MPU_IRQ); |
| 1043 | goto err1; |
| 1044 | } |
| 1045 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 1046 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1047 | if (ret) { |
| 1048 | printk(KERN_ERR "Failed to setup powerdomains\n"); |
| 1049 | goto err2; |
| 1050 | } |
| 1051 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 1052 | (void) clkdm_for_each(clkdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1053 | |
| 1054 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
| 1055 | if (mpu_pwrdm == NULL) { |
| 1056 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); |
| 1057 | goto err2; |
| 1058 | } |
| 1059 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 1060 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
| 1061 | per_pwrdm = pwrdm_lookup("per_pwrdm"); |
| 1062 | core_pwrdm = pwrdm_lookup("core_pwrdm"); |
Tero Kristo | c16c3f6 | 2008-12-11 16:46:57 +0200 | [diff] [blame] | 1063 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 1064 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1065 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
| 1066 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); |
| 1067 | per_clkdm = clkdm_lookup("per_clkdm"); |
| 1068 | core_clkdm = clkdm_lookup("core_clkdm"); |
| 1069 | |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 1070 | omap_push_sram_idle(); |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 1071 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1072 | suspend_set_ops(&omap_pm_ops); |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 1073 | #endif /* CONFIG_SUSPEND */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1074 | |
| 1075 | pm_idle = omap3_pm_idle; |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 1076 | omap3_idle_init(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1077 | |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 1078 | /* |
| 1079 | * RTA is disabled during initialization as per erratum i608 |
| 1080 | * it is safer to disable RTA by the bootloader, but we would like |
| 1081 | * to be doubly sure here and prevent any mishaps. |
| 1082 | */ |
| 1083 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) |
| 1084 | omap3630_ctrl_disable_rta(); |
| 1085 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 1086 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1087 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
| 1088 | omap3_secure_ram_storage = |
| 1089 | kmalloc(0x803F, GFP_KERNEL); |
| 1090 | if (!omap3_secure_ram_storage) |
| 1091 | printk(KERN_ERR "Memory allocation failed when" |
| 1092 | "allocating for secure sram context\n"); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 1093 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 1094 | local_irq_disable(); |
| 1095 | local_fiq_disable(); |
| 1096 | |
| 1097 | omap_dma_global_context_save(); |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 1098 | omap3_save_secure_ram_context(); |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 1099 | omap_dma_global_context_restore(); |
| 1100 | |
| 1101 | local_irq_enable(); |
| 1102 | local_fiq_enable(); |
| 1103 | } |
| 1104 | |
| 1105 | omap3_save_scratchpad_contents(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 1106 | err1: |
| 1107 | return ret; |
| 1108 | err2: |
| 1109 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); |
| 1110 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
| 1111 | list_del(&pwrst->node); |
| 1112 | kfree(pwrst); |
| 1113 | } |
| 1114 | return ret; |
| 1115 | } |
| 1116 | |
| 1117 | late_initcall(omap3_pm_init); |