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gerrit-public.fairphone.software / kernel / msm-4.9 / 31c203d49ca04e042722d764feec0b80c2afb575 / . / arch / arm / mach-omap2 / clock34xx.h
blob: 3f133a0df08946806161def92ebd2ddc059c0b9b [file] [log] [blame]
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1/*
2 * OMAP3 clock framework
3 *
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]8 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
10 *
11 * Written by Paul Walmsley
12 */
13
14#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
15#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
16
17#include <asm/arch/control.h>
18
19#include "clock.h"
20#include "cm.h"
21#include "cm-regbits-34xx.h"
22#include "prm.h"
23#include "prm-regbits-34xx.h"
24
25static void omap3_dpll_recalc(struct clk *clk);
26static void omap3_clkoutx2_recalc(struct clk *clk);
27
28/*
29 * DPLL1 supplies clock to the MPU.
30 * DPLL2 supplies clock to the IVA2.
31 * DPLL3 supplies CORE domain clocks.
32 * DPLL4 supplies peripheral clocks.
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
34 */
35
36/* PRM CLOCKS */
37
38/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
39static struct clk omap_32k_fck = {
40 .name = "omap_32k_fck",
41 .rate = 32768,
42 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
43 ALWAYS_ENABLED,
44 .recalc = &propagate_rate,
45};
46
47static struct clk secure_32k_fck = {
48 .name = "secure_32k_fck",
49 .rate = 32768,
50 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
51 ALWAYS_ENABLED,
52 .recalc = &propagate_rate,
53};
54
55/* Virtual source clocks for osc_sys_ck */
56static struct clk virt_12m_ck = {
57 .name = "virt_12m_ck",
58 .rate = 12000000,
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
60 ALWAYS_ENABLED,
61 .recalc = &propagate_rate,
62};
63
64static struct clk virt_13m_ck = {
65 .name = "virt_13m_ck",
66 .rate = 13000000,
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
68 ALWAYS_ENABLED,
69 .recalc = &propagate_rate,
70};
71
72static struct clk virt_16_8m_ck = {
73 .name = "virt_16_8m_ck",
74 .rate = 16800000,
75 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
76 ALWAYS_ENABLED,
77 .recalc = &propagate_rate,
78};
79
80static struct clk virt_19_2m_ck = {
81 .name = "virt_19_2m_ck",
82 .rate = 19200000,
83 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
84 ALWAYS_ENABLED,
85 .recalc = &propagate_rate,
86};
87
88static struct clk virt_26m_ck = {
89 .name = "virt_26m_ck",
90 .rate = 26000000,
91 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
92 ALWAYS_ENABLED,
93 .recalc = &propagate_rate,
94};
95
96static struct clk virt_38_4m_ck = {
97 .name = "virt_38_4m_ck",
98 .rate = 38400000,
99 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
100 ALWAYS_ENABLED,
101 .recalc = &propagate_rate,
102};
103
104static const struct clksel_rate osc_sys_12m_rates[] = {
105 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
106 { .div = 0 }
107};
108
109static const struct clksel_rate osc_sys_13m_rates[] = {
110 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
111 { .div = 0 }
112};
113
114static const struct clksel_rate osc_sys_16_8m_rates[] = {
115 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
116 { .div = 0 }
117};
118
119static const struct clksel_rate osc_sys_19_2m_rates[] = {
120 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
121 { .div = 0 }
122};
123
124static const struct clksel_rate osc_sys_26m_rates[] = {
125 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
126 { .div = 0 }
127};
128
129static const struct clksel_rate osc_sys_38_4m_rates[] = {
130 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
131 { .div = 0 }
132};
133
134static const struct clksel osc_sys_clksel[] = {
135 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
136 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
137 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
138 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
139 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
140 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
141 { .parent = NULL },
142};
143
144/* Oscillator clock */
145/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
146static struct clk osc_sys_ck = {
147 .name = "osc_sys_ck",
148 .init = &omap2_init_clksel_parent,
149 .clksel_reg = OMAP3430_PRM_CLKSEL,
150 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
151 .clksel = osc_sys_clksel,
152 /* REVISIT: deal with autoextclkmode? */
153 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
154 ALWAYS_ENABLED,
155 .recalc = &omap2_clksel_recalc,
156};
157
158static const struct clksel_rate div2_rates[] = {
159 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
160 { .div = 2, .val = 2, .flags = RATE_IN_343X },
161 { .div = 0 }
162};
163
164static const struct clksel sys_clksel[] = {
165 { .parent = &osc_sys_ck, .rates = div2_rates },
166 { .parent = NULL }
167};
168
169/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
170/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
171static struct clk sys_ck = {
172 .name = "sys_ck",
173 .parent = &osc_sys_ck,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
176 .clksel_mask = OMAP_SYSCLKDIV_MASK,
177 .clksel = sys_clksel,
178 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
179 .recalc = &omap2_clksel_recalc,
180};
181
182static struct clk sys_altclk = {
183 .name = "sys_altclk",
184 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
185 .recalc = &propagate_rate,
186};
187
188/* Optional external clock input for some McBSPs */
189static struct clk mcbsp_clks = {
190 .name = "mcbsp_clks",
191 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
192 .recalc = &propagate_rate,
193};
194
195/* PRM EXTERNAL CLOCK OUTPUT */
196
197static struct clk sys_clkout1 = {
198 .name = "sys_clkout1",
199 .parent = &osc_sys_ck,
200 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
201 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
202 .flags = CLOCK_IN_OMAP343X,
203 .recalc = &followparent_recalc,
204};
205
206/* DPLLS */
207
208/* CM CLOCKS */
209
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]210static const struct clksel_rate dpll_bypass_rates[] = {
211 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
212 { .div = 0 }
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]213};
214
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]215static const struct clksel_rate dpll_locked_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
217 { .div = 0 }
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]218};
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]240/* DPLL1 */
241/* MPU clock source */
242/* Type: DPLL */
243static const struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
252};
253
254static struct clk dpll1_ck = {
255 .name = "dpll1_ck",
256 .parent = &sys_ck,
257 .dpll_data = &dpll1_dd,
258 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .recalc = &omap3_dpll_recalc,
260};
261
262/*
263 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
264 * DPLL isn't bypassed.
265 */
266static struct clk dpll1_x2_ck = {
267 .name = "dpll1_x2_ck",
268 .parent = &dpll1_ck,
269 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
270 PARENT_CONTROLS_CLOCK,
271 .recalc = &omap3_clkoutx2_recalc,
272};
273
274/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
275static const struct clksel div16_dpll1_x2m2_clksel[] = {
276 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
277 { .parent = NULL }
278};
279
280/*
281 * Does not exist in the TRM - needed to separate the M2 divider from
282 * bypass selection in mpu_ck
283 */
284static struct clk dpll1_x2m2_ck = {
285 .name = "dpll1_x2m2_ck",
286 .parent = &dpll1_x2_ck,
287 .init = &omap2_init_clksel_parent,
288 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
289 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
290 .clksel = div16_dpll1_x2m2_clksel,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
292 PARENT_CONTROLS_CLOCK,
293 .recalc = &omap2_clksel_recalc,
294};
295
296/* DPLL2 */
297/* IVA2 clock source */
298/* Type: DPLL */
299
300static const struct dpll_data dpll2_dd = {
301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
309};
310
311static struct clk dpll2_ck = {
312 .name = "dpll2_ck",
313 .parent = &sys_ck,
314 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
316 .recalc = &omap3_dpll_recalc,
317};
318
319static const struct clksel div16_dpll2_m2x2_clksel[] = {
320 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
321 { .parent = NULL }
322};
323
324/*
325 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
326 * or CLKOUTX2. CLKOUT seems most plausible.
327 */
328static struct clk dpll2_m2_ck = {
329 .name = "dpll2_m2_ck",
330 .parent = &dpll2_ck,
331 .init = &omap2_init_clksel_parent,
332 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
333 OMAP3430_CM_CLKSEL2_PLL),
334 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
335 .clksel = div16_dpll2_m2x2_clksel,
336 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
337 PARENT_CONTROLS_CLOCK,
338 .recalc = &omap2_clksel_recalc,
339};
340
341/* DPLL3 */
342/* Source clock for all interfaces and for some device fclks */
343/* Type: DPLL */
344static const struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
348 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
349 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
353};
354
355static struct clk dpll3_ck = {
356 .name = "dpll3_ck",
357 .parent = &sys_ck,
358 .dpll_data = &dpll3_dd,
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
360 .recalc = &omap3_dpll_recalc,
361};
362
363/*
364 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
365 * DPLL isn't bypassed
366 */
367static struct clk dpll3_x2_ck = {
368 .name = "dpll3_x2_ck",
369 .parent = &dpll3_ck,
370 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
371 PARENT_CONTROLS_CLOCK,
372 .recalc = &omap3_clkoutx2_recalc,
373};
374
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]375static const struct clksel_rate div31_dpll3_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
377 { .div = 2, .val = 2, .flags = RATE_IN_343X },
378 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
379 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
380 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
381 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
382 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
383 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
384 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
385 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
386 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
387 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
388 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
389 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
390 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
391 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
392 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
393 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
394 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
395 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
396 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
397 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
398 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
399 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
400 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
401 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
402 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
403 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
404 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
405 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
406 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
407 { .div = 0 },
408};
409
410static const struct clksel div31_dpll3m2_clksel[] = {
411 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
412 { .parent = NULL }
413};
414
415/*
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]416 * DPLL3 output M2
417 * REVISIT: This DPLL output divider must be changed in SRAM, so until
418 * that code is ready, this should remain a 'read-only' clksel clock.
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]419 */
420static struct clk dpll3_m2_ck = {
421 .name = "dpll3_m2_ck",
422 .parent = &dpll3_ck,
423 .init = &omap2_init_clksel_parent,
424 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
425 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
426 .clksel = div31_dpll3m2_clksel,
427 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
428 PARENT_CONTROLS_CLOCK,
429 .recalc = &omap2_clksel_recalc,
430};
431
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]432static const struct clksel core_ck_clksel[] = {
433 { .parent = &sys_ck, .rates = dpll_bypass_rates },
434 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
435 { .parent = NULL }
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]436};
437
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]438static struct clk core_ck = {
439 .name = "core_ck",
440 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK,
443 .clksel = core_ck_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]446 .recalc = &omap2_clksel_recalc,
447};
448
449static const struct clksel dpll3_m2x2_ck_clksel[] = {
450 { .parent = &sys_ck, .rates = dpll_bypass_rates },
451 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
452 { .parent = NULL }
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]453};
454
455static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]457 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK,
460 .clksel = dpll3_m2x2_ck_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]463 .recalc = &omap2_clksel_recalc,
464};
465
466/* The PWRDN bit is apparently only available on 3430ES2 and above */
467static const struct clksel div16_dpll3_clksel[] = {
468 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
469 { .parent = NULL }
470};
471
472/* This virtual clock is the source for dpll3_m3x2_ck */
473static struct clk dpll3_m3_ck = {
474 .name = "dpll3_m3_ck",
475 .parent = &dpll3_ck,
476 .init = &omap2_init_clksel_parent,
477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
478 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
479 .clksel = div16_dpll3_clksel,
480 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
481 PARENT_CONTROLS_CLOCK,
482 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]483};
484
485/* The PWRDN bit is apparently only available on 3430ES2 and above */
486static struct clk dpll3_m3x2_ck = {
487 .name = "dpll3_m3x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]488 .parent = &dpll3_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]489 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
490 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
491 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]492 .recalc = &omap3_clkoutx2_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]493};
494
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]495static const struct clksel emu_core_alwon_ck_clksel[] = {
496 { .parent = &sys_ck, .rates = dpll_bypass_rates },
497 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]498 { .parent = NULL }
499};
500
501static struct clk emu_core_alwon_ck = {
502 .name = "emu_core_alwon_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]503 .parent = &dpll3_m3x2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]504 .init = &omap2_init_clksel_parent,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK,
507 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]511};
512
513/* DPLL4 */
514/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
515/* Type: DPLL */
516static const struct dpll_data dpll4_dd = {
517 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
518 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
525};
526
527static struct clk dpll4_ck = {
528 .name = "dpll4_ck",
529 .parent = &sys_ck,
530 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
532 .recalc = &omap3_dpll_recalc,
533};
534
535/*
536 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]537 * DPLL isn't bypassed --
538 * XXX does this serve any downstream clocks?
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]539 */
540static struct clk dpll4_x2_ck = {
541 .name = "dpll4_x2_ck",
542 .parent = &dpll4_ck,
543 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
544 PARENT_CONTROLS_CLOCK,
545 .recalc = &omap3_clkoutx2_recalc,
546};
547
548static const struct clksel div16_dpll4_clksel[] = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]549 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]550 { .parent = NULL }
551};
552
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]553/* This virtual clock is the source for dpll4_m2x2_ck */
554static struct clk dpll4_m2_ck = {
555 .name = "dpll4_m2_ck",
556 .parent = &dpll4_ck,
557 .init = &omap2_init_clksel_parent,
558 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
559 .clksel_mask = OMAP3430_DIV_96M_MASK,
560 .clksel = div16_dpll4_clksel,
561 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
562 PARENT_CONTROLS_CLOCK,
563 .recalc = &omap2_clksel_recalc,
564};
565
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]566/* The PWRDN bit is apparently only available on 3430ES2 and above */
567static struct clk dpll4_m2x2_ck = {
568 .name = "dpll4_m2x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]569 .parent = &dpll4_m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]570 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]572 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]573 .recalc = &omap3_clkoutx2_recalc,
574};
575
576static const struct clksel omap_96m_alwon_fck_clksel[] = {
577 { .parent = &sys_ck, .rates = dpll_bypass_rates },
578 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
579 { .parent = NULL }
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]580};
581
582static struct clk omap_96m_alwon_fck = {
583 .name = "omap_96m_alwon_fck",
584 .parent = &dpll4_m2x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]585 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
588 .clksel = omap_96m_alwon_fck_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]591 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]592};
593
594static struct clk omap_96m_fck = {
595 .name = "omap_96m_fck",
596 .parent = &omap_96m_alwon_fck,
597 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
598 PARENT_CONTROLS_CLOCK,
599 .recalc = &followparent_recalc,
600};
601
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]602static const struct clksel cm_96m_fck_clksel[] = {
603 { .parent = &sys_ck, .rates = dpll_bypass_rates },
604 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
605 { .parent = NULL }
606};
607
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]608static struct clk cm_96m_fck = {
609 .name = "cm_96m_fck",
610 .parent = &dpll4_m2x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]611 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
614 .clksel = cm_96m_fck_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]617 .recalc = &omap2_clksel_recalc,
618};
619
620/* This virtual clock is the source for dpll4_m3x2_ck */
621static struct clk dpll4_m3_ck = {
622 .name = "dpll4_m3_ck",
623 .parent = &dpll4_ck,
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
627 .clksel = div16_dpll4_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]631};
632
633/* The PWRDN bit is apparently only available on 3430ES2 and above */
634static struct clk dpll4_m3x2_ck = {
635 .name = "dpll4_m3x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]636 .parent = &dpll4_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]637 .init = &omap2_init_clksel_parent,
638 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
639 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]640 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]641 .recalc = &omap3_clkoutx2_recalc,
642};
643
644static const struct clksel virt_omap_54m_fck_clksel[] = {
645 { .parent = &sys_ck, .rates = dpll_bypass_rates },
646 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
647 { .parent = NULL }
648};
649
650static struct clk virt_omap_54m_fck = {
651 .name = "virt_omap_54m_fck",
652 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
656 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]659 .recalc = &omap2_clksel_recalc,
660};
661
662static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
663 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
664 { .div = 0 }
665};
666
667static const struct clksel_rate omap_54m_alt_rates[] = {
668 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
669 { .div = 0 }
670};
671
672static const struct clksel omap_54m_clksel[] = {
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]673 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]674 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
675 { .parent = NULL }
676};
677
678static struct clk omap_54m_fck = {
679 .name = "omap_54m_fck",
680 .init = &omap2_init_clksel_parent,
681 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
682 .clksel_mask = OMAP3430_SOURCE_54M,
683 .clksel = omap_54m_clksel,
684 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
685 PARENT_CONTROLS_CLOCK,
686 .recalc = &omap2_clksel_recalc,
687};
688
689static const struct clksel_rate omap_48m_96md2_rates[] = {
690 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
691 { .div = 0 }
692};
693
694static const struct clksel_rate omap_48m_alt_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
696 { .div = 0 }
697};
698
699static const struct clksel omap_48m_clksel[] = {
700 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
701 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
702 { .parent = NULL }
703};
704
705static struct clk omap_48m_fck = {
706 .name = "omap_48m_fck",
707 .init = &omap2_init_clksel_parent,
708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
709 .clksel_mask = OMAP3430_SOURCE_48M,
710 .clksel = omap_48m_clksel,
711 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
712 PARENT_CONTROLS_CLOCK,
713 .recalc = &omap2_clksel_recalc,
714};
715
716static struct clk omap_12m_fck = {
717 .name = "omap_12m_fck",
718 .parent = &omap_48m_fck,
719 .fixed_div = 4,
720 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
721 PARENT_CONTROLS_CLOCK,
722 .recalc = &omap2_fixed_divisor_recalc,
723};
724
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]725/* This virstual clock is the source for dpll4_m4x2_ck */
726static struct clk dpll4_m4_ck = {
727 .name = "dpll4_m4_ck",
728 .parent = &dpll4_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]729 .init = &omap2_init_clksel_parent,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
731 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
732 .clksel = div16_dpll4_clksel,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
734 PARENT_CONTROLS_CLOCK,
735 .recalc = &omap2_clksel_recalc,
736};
737
738/* The PWRDN bit is apparently only available on 3430ES2 and above */
739static struct clk dpll4_m4x2_ck = {
740 .name = "dpll4_m4x2_ck",
741 .parent = &dpll4_m4_ck,
742 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
743 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]745 .recalc = &omap3_clkoutx2_recalc,
746};
747
748/* This virtual clock is the source for dpll4_m5x2_ck */
749static struct clk dpll4_m5_ck = {
750 .name = "dpll4_m5_ck",
751 .parent = &dpll4_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
755 .clksel = div16_dpll4_clksel,
756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
757 PARENT_CONTROLS_CLOCK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]758 .recalc = &omap2_clksel_recalc,
759};
760
761/* The PWRDN bit is apparently only available on 3430ES2 and above */
762static struct clk dpll4_m5x2_ck = {
763 .name = "dpll4_m5x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]764 .parent = &dpll4_m5_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]765 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
766 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]768 .recalc = &omap3_clkoutx2_recalc,
769};
770
771/* This virtual clock is the source for dpll4_m6x2_ck */
772static struct clk dpll4_m6_ck = {
773 .name = "dpll4_m6_ck",
774 .parent = &dpll4_ck,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
778 .clksel = div16_dpll4_clksel,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]781 .recalc = &omap2_clksel_recalc,
782};
783
784/* The PWRDN bit is apparently only available on 3430ES2 and above */
785static struct clk dpll4_m6x2_ck = {
786 .name = "dpll4_m6x2_ck",
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]787 .parent = &dpll4_m6_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]788 .init = &omap2_init_clksel_parent,
789 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
790 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]791 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]792 .recalc = &omap3_clkoutx2_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]793};
794
795static struct clk emu_per_alwon_ck = {
796 .name = "emu_per_alwon_ck",
797 .parent = &dpll4_m6x2_ck,
798 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
799 PARENT_CONTROLS_CLOCK,
800 .recalc = &followparent_recalc,
801};
802
803/* DPLL5 */
804/* Supplies 120MHz clock, USIM source clock */
805/* Type: DPLL */
806/* 3430ES2 only */
807static const struct dpll_data dpll5_dd = {
808 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
809 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
816};
817
818static struct clk dpll5_ck = {
819 .name = "dpll5_ck",
820 .parent = &sys_ck,
821 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
823 ALWAYS_ENABLED,
824 .recalc = &omap3_dpll_recalc,
825};
826
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]827static const struct clksel div16_dpll5_clksel[] = {
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]828 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
829 { .parent = NULL }
830};
831
832static struct clk dpll5_m2_ck = {
833 .name = "dpll5_m2_ck",
834 .parent = &dpll5_ck,
835 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]838 .clksel = div16_dpll5_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
840 .recalc = &omap2_clksel_recalc,
841};
842
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]843static const struct clksel omap_120m_fck_clksel[] = {
844 { .parent = &sys_ck, .rates = dpll_bypass_rates },
845 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
846 { .parent = NULL }
847};
848
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]849static struct clk omap_120m_fck = {
850 .name = "omap_120m_fck",
851 .parent = &dpll5_m2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]852 .init = &omap2_init_clksel_parent,
853 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
854 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
855 .clksel = omap_120m_fck_clksel,
856 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
857 PARENT_CONTROLS_CLOCK,
858 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]859};
860
861/* CM EXTERNAL CLOCK OUTPUTS */
862
863static const struct clksel_rate clkout2_src_core_rates[] = {
864 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
865 { .div = 0 }
866};
867
868static const struct clksel_rate clkout2_src_sys_rates[] = {
869 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
870 { .div = 0 }
871};
872
873static const struct clksel_rate clkout2_src_96m_rates[] = {
874 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
875 { .div = 0 }
876};
877
878static const struct clksel_rate clkout2_src_54m_rates[] = {
879 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
880 { .div = 0 }
881};
882
883static const struct clksel clkout2_src_clksel[] = {
884 { .parent = &core_ck, .rates = clkout2_src_core_rates },
885 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
886 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
887 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
888 { .parent = NULL }
889};
890
891static struct clk clkout2_src_ck = {
892 .name = "clkout2_src_ck",
893 .init = &omap2_init_clksel_parent,
894 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
895 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
896 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
897 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
898 .clksel = clkout2_src_clksel,
899 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
900 .recalc = &omap2_clksel_recalc,
901};
902
903static const struct clksel_rate sys_clkout2_rates[] = {
904 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
905 { .div = 2, .val = 1, .flags = RATE_IN_343X },
906 { .div = 4, .val = 2, .flags = RATE_IN_343X },
907 { .div = 8, .val = 3, .flags = RATE_IN_343X },
908 { .div = 16, .val = 4, .flags = RATE_IN_343X },
909 { .div = 0 },
910};
911
912static const struct clksel sys_clkout2_clksel[] = {
913 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
914 { .parent = NULL },
915};
916
917static struct clk sys_clkout2 = {
918 .name = "sys_clkout2",
919 .init = &omap2_init_clksel_parent,
920 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
921 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
922 .clksel = sys_clkout2_clksel,
923 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
924 .recalc = &omap2_clksel_recalc,
925};
926
927/* CM OUTPUT CLOCKS */
928
929static struct clk corex2_fck = {
930 .name = "corex2_fck",
931 .parent = &dpll3_m2x2_ck,
932 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
933 PARENT_CONTROLS_CLOCK,
934 .recalc = &followparent_recalc,
935};
936
937/* DPLL power domain clock controls */
938
939static const struct clksel div2_core_clksel[] = {
940 { .parent = &core_ck, .rates = div2_rates },
941 { .parent = NULL }
942};
943
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]944/*
945 * REVISIT: Are these in DPLL power domain or CM power domain? docs
946 * may be inconsistent here?
947 */
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]948static struct clk dpll1_fck = {
949 .name = "dpll1_fck",
950 .parent = &core_ck,
951 .init = &omap2_init_clksel_parent,
952 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
953 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
954 .clksel = div2_core_clksel,
955 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
956 PARENT_CONTROLS_CLOCK,
957 .recalc = &omap2_clksel_recalc,
958};
959
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]960/*
961 * MPU clksel:
962 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
963 * derives from the high-frequency bypass clock originating from DPLL3,
964 * called 'dpll1_fck'
965 */
966static const struct clksel mpu_clksel[] = {
967 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
968 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
969 { .parent = NULL }
970};
971
972static struct clk mpu_ck = {
973 .name = "mpu_ck",
974 .parent = &dpll1_x2m2_ck,
975 .init = &omap2_init_clksel_parent,
976 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
977 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
978 .clksel = mpu_clksel,
979 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
980 PARENT_CONTROLS_CLOCK,
981 .recalc = &omap2_clksel_recalc,
982};
983
984/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
985static const struct clksel_rate arm_fck_rates[] = {
986 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
987 { .div = 2, .val = 1, .flags = RATE_IN_343X },
988 { .div = 0 },
989};
990
991static const struct clksel arm_fck_clksel[] = {
992 { .parent = &mpu_ck, .rates = arm_fck_rates },
993 { .parent = NULL }
994};
995
996static struct clk arm_fck = {
997 .name = "arm_fck",
998 .parent = &mpu_ck,
999 .init = &omap2_init_clksel_parent,
1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1001 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1002 .clksel = arm_fck_clksel,
1003 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1004 PARENT_CONTROLS_CLOCK,
1005 .recalc = &omap2_clksel_recalc,
1006};
1007
1008/*
1009 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1010 * although it is referenced - so this is a guess
1011 */
1012static struct clk emu_mpu_alwon_ck = {
1013 .name = "emu_mpu_alwon_ck",
1014 .parent = &mpu_ck,
1015 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1016 PARENT_CONTROLS_CLOCK,
1017 .recalc = &followparent_recalc,
1018};
1019
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1020static struct clk dpll2_fck = {
1021 .name = "dpll2_fck",
1022 .parent = &core_ck,
1023 .init = &omap2_init_clksel_parent,
1024 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1025 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1026 .clksel = div2_core_clksel,
1027 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1028 PARENT_CONTROLS_CLOCK,
1029 .recalc = &omap2_clksel_recalc,
1030};
1031
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1032/*
1033 * IVA2 clksel:
1034 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1035 * derives from the high-frequency bypass clock originating from DPLL3,
1036 * called 'dpll2_fck'
1037 */
1038
1039static const struct clksel iva2_clksel[] = {
1040 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1041 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1042 { .parent = NULL }
1043};
1044
1045static struct clk iva2_ck = {
1046 .name = "iva2_ck",
1047 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent,
Hiroshi DOYU31c203d2008-04-01 10:11:22 +0300[diff] [blame^]1049 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1050 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1051 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1052 OMAP3430_CM_IDLEST_PLL),
1053 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1054 .clksel = iva2_clksel,
Hiroshi DOYU31c203d2008-04-01 10:11:22 +0300[diff] [blame^]1055 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1056 .recalc = &omap2_clksel_recalc,
1057};
1058
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1059/* Common interface clocks */
1060
1061static struct clk l3_ick = {
1062 .name = "l3_ick",
1063 .parent = &core_ck,
1064 .init = &omap2_init_clksel_parent,
1065 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1066 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1067 .clksel = div2_core_clksel,
1068 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1069 PARENT_CONTROLS_CLOCK,
1070 .recalc = &omap2_clksel_recalc,
1071};
1072
1073static const struct clksel div2_l3_clksel[] = {
1074 { .parent = &l3_ick, .rates = div2_rates },
1075 { .parent = NULL }
1076};
1077
1078static struct clk l4_ick = {
1079 .name = "l4_ick",
1080 .parent = &l3_ick,
1081 .init = &omap2_init_clksel_parent,
1082 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1084 .clksel = div2_l3_clksel,
1085 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1086 PARENT_CONTROLS_CLOCK,
1087 .recalc = &omap2_clksel_recalc,
1088
1089};
1090
1091static const struct clksel div2_l4_clksel[] = {
1092 { .parent = &l4_ick, .rates = div2_rates },
1093 { .parent = NULL }
1094};
1095
1096static struct clk rm_ick = {
1097 .name = "rm_ick",
1098 .parent = &l4_ick,
1099 .init = &omap2_init_clksel_parent,
1100 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1101 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1102 .clksel = div2_l4_clksel,
1103 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1104 .recalc = &omap2_clksel_recalc,
1105};
1106
1107/* GFX power domain */
1108
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1109/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1110
1111static const struct clksel gfx_l3_clksel[] = {
1112 { .parent = &l3_ick, .rates = gfx_l3_rates },
1113 { .parent = NULL }
1114};
1115
1116static struct clk gfx_l3_fck = {
1117 .name = "gfx_l3_fck",
1118 .parent = &l3_ick,
1119 .init = &omap2_init_clksel_parent,
1120 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1121 .enable_bit = OMAP_EN_GFX_SHIFT,
1122 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1123 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1124 .clksel = gfx_l3_clksel,
1125 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1126 .recalc = &omap2_clksel_recalc,
1127};
1128
1129static struct clk gfx_l3_ick = {
1130 .name = "gfx_l3_ick",
1131 .parent = &l3_ick,
1132 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1133 .enable_bit = OMAP_EN_GFX_SHIFT,
1134 .flags = CLOCK_IN_OMAP3430ES1,
1135 .recalc = &followparent_recalc,
1136};
1137
1138static struct clk gfx_cg1_ck = {
1139 .name = "gfx_cg1_ck",
1140 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1141 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1142 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1143 .flags = CLOCK_IN_OMAP3430ES1,
1144 .recalc = &followparent_recalc,
1145};
1146
1147static struct clk gfx_cg2_ck = {
1148 .name = "gfx_cg2_ck",
1149 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1150 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1151 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1152 .flags = CLOCK_IN_OMAP3430ES1,
1153 .recalc = &followparent_recalc,
1154};
1155
1156/* SGX power domain - 3430ES2 only */
1157
1158static const struct clksel_rate sgx_core_rates[] = {
1159 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1160 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1161 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1162 { .div = 0 },
1163};
1164
1165static const struct clksel_rate sgx_96m_rates[] = {
1166 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1167 { .div = 0 },
1168};
1169
1170static const struct clksel sgx_clksel[] = {
1171 { .parent = &core_ck, .rates = sgx_core_rates },
1172 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1173 { .parent = NULL },
1174};
1175
1176static struct clk sgx_fck = {
1177 .name = "sgx_fck",
1178 .init = &omap2_init_clksel_parent,
1179 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1180 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1181 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1182 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1183 .clksel = sgx_clksel,
1184 .flags = CLOCK_IN_OMAP3430ES2,
1185 .recalc = &omap2_clksel_recalc,
1186};
1187
1188static struct clk sgx_ick = {
1189 .name = "sgx_ick",
1190 .parent = &l3_ick,
1191 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1192 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1193 .flags = CLOCK_IN_OMAP3430ES2,
1194 .recalc = &followparent_recalc,
1195};
1196
1197/* CORE power domain */
1198
1199static struct clk d2d_26m_fck = {
1200 .name = "d2d_26m_fck",
1201 .parent = &sys_ck,
1202 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1203 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1204 .flags = CLOCK_IN_OMAP3430ES1,
1205 .recalc = &followparent_recalc,
1206};
1207
1208static const struct clksel omap343x_gpt_clksel[] = {
1209 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1210 { .parent = &sys_ck, .rates = gpt_sys_rates },
1211 { .parent = NULL}
1212};
1213
1214static struct clk gpt10_fck = {
1215 .name = "gpt10_fck",
1216 .parent = &sys_ck,
1217 .init = &omap2_init_clksel_parent,
1218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1219 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1220 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1221 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1222 .clksel = omap343x_gpt_clksel,
1223 .flags = CLOCK_IN_OMAP343X,
1224 .recalc = &omap2_clksel_recalc,
1225};
1226
1227static struct clk gpt11_fck = {
1228 .name = "gpt11_fck",
1229 .parent = &sys_ck,
1230 .init = &omap2_init_clksel_parent,
1231 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1232 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1233 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1234 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1235 .clksel = omap343x_gpt_clksel,
1236 .flags = CLOCK_IN_OMAP343X,
1237 .recalc = &omap2_clksel_recalc,
1238};
1239
1240static struct clk cpefuse_fck = {
1241 .name = "cpefuse_fck",
1242 .parent = &sys_ck,
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1244 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1245 .flags = CLOCK_IN_OMAP3430ES2,
1246 .recalc = &followparent_recalc,
1247};
1248
1249static struct clk ts_fck = {
1250 .name = "ts_fck",
1251 .parent = &omap_32k_fck,
1252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1253 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1254 .flags = CLOCK_IN_OMAP3430ES2,
1255 .recalc = &followparent_recalc,
1256};
1257
1258static struct clk usbtll_fck = {
1259 .name = "usbtll_fck",
1260 .parent = &omap_120m_fck,
1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1262 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1263 .flags = CLOCK_IN_OMAP3430ES2,
1264 .recalc = &followparent_recalc,
1265};
1266
1267/* CORE 96M FCLK-derived clocks */
1268
1269static struct clk core_96m_fck = {
1270 .name = "core_96m_fck",
1271 .parent = &omap_96m_fck,
1272 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1273 PARENT_CONTROLS_CLOCK,
1274 .recalc = &followparent_recalc,
1275};
1276
1277static struct clk mmchs3_fck = {
1278 .name = "mmchs_fck",
1279 .id = 3,
1280 .parent = &core_96m_fck,
1281 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1282 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1283 .flags = CLOCK_IN_OMAP3430ES2,
1284 .recalc = &followparent_recalc,
1285};
1286
1287static struct clk mmchs2_fck = {
1288 .name = "mmchs_fck",
1289 .id = 2,
1290 .parent = &core_96m_fck,
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1292 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1293 .flags = CLOCK_IN_OMAP343X,
1294 .recalc = &followparent_recalc,
1295};
1296
1297static struct clk mspro_fck = {
1298 .name = "mspro_fck",
1299 .parent = &core_96m_fck,
1300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1301 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1302 .flags = CLOCK_IN_OMAP343X,
1303 .recalc = &followparent_recalc,
1304};
1305
1306static struct clk mmchs1_fck = {
1307 .name = "mmchs_fck",
1308 .id = 1,
1309 .parent = &core_96m_fck,
1310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1311 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1312 .flags = CLOCK_IN_OMAP343X,
1313 .recalc = &followparent_recalc,
1314};
1315
1316static struct clk i2c3_fck = {
1317 .name = "i2c_fck",
1318 .id = 3,
1319 .parent = &core_96m_fck,
1320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1321 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1322 .flags = CLOCK_IN_OMAP343X,
1323 .recalc = &followparent_recalc,
1324};
1325
1326static struct clk i2c2_fck = {
1327 .name = "i2c_fck",
1328 .id = 2,
1329 .parent = &core_96m_fck,
1330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1331 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1332 .flags = CLOCK_IN_OMAP343X,
1333 .recalc = &followparent_recalc,
1334};
1335
1336static struct clk i2c1_fck = {
1337 .name = "i2c_fck",
1338 .id = 1,
1339 .parent = &core_96m_fck,
1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1342 .flags = CLOCK_IN_OMAP343X,
1343 .recalc = &followparent_recalc,
1344};
1345
1346/*
1347 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1348 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1349 */
1350static const struct clksel_rate common_mcbsp_96m_rates[] = {
1351 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1352 { .div = 0 }
1353};
1354
1355static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1356 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1357 { .div = 0 }
1358};
1359
1360static const struct clksel mcbsp_15_clksel[] = {
1361 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1362 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1363 { .parent = NULL }
1364};
1365
1366static struct clk mcbsp5_fck = {
1367 .name = "mcbsp5_fck",
1368 .init = &omap2_init_clksel_parent,
1369 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1371 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1372 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1373 .clksel = mcbsp_15_clksel,
1374 .flags = CLOCK_IN_OMAP343X,
1375 .recalc = &omap2_clksel_recalc,
1376};
1377
1378static struct clk mcbsp1_fck = {
1379 .name = "mcbsp1_fck",
1380 .init = &omap2_init_clksel_parent,
1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1382 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1383 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1384 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1385 .clksel = mcbsp_15_clksel,
1386 .flags = CLOCK_IN_OMAP343X,
1387 .recalc = &omap2_clksel_recalc,
1388};
1389
1390/* CORE_48M_FCK-derived clocks */
1391
1392static struct clk core_48m_fck = {
1393 .name = "core_48m_fck",
1394 .parent = &omap_48m_fck,
1395 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1396 PARENT_CONTROLS_CLOCK,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk mcspi4_fck = {
1401 .name = "mcspi_fck",
1402 .id = 4,
1403 .parent = &core_48m_fck,
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1406 .flags = CLOCK_IN_OMAP343X,
1407 .recalc = &followparent_recalc,
1408};
1409
1410static struct clk mcspi3_fck = {
1411 .name = "mcspi_fck",
1412 .id = 3,
1413 .parent = &core_48m_fck,
1414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1415 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1416 .flags = CLOCK_IN_OMAP343X,
1417 .recalc = &followparent_recalc,
1418};
1419
1420static struct clk mcspi2_fck = {
1421 .name = "mcspi_fck",
1422 .id = 2,
1423 .parent = &core_48m_fck,
1424 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1425 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1426 .flags = CLOCK_IN_OMAP343X,
1427 .recalc = &followparent_recalc,
1428};
1429
1430static struct clk mcspi1_fck = {
1431 .name = "mcspi_fck",
1432 .id = 1,
1433 .parent = &core_48m_fck,
1434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1435 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1436 .flags = CLOCK_IN_OMAP343X,
1437 .recalc = &followparent_recalc,
1438};
1439
1440static struct clk uart2_fck = {
1441 .name = "uart2_fck",
1442 .parent = &core_48m_fck,
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1445 .flags = CLOCK_IN_OMAP343X,
1446 .recalc = &followparent_recalc,
1447};
1448
1449static struct clk uart1_fck = {
1450 .name = "uart1_fck",
1451 .parent = &core_48m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1454 .flags = CLOCK_IN_OMAP343X,
1455 .recalc = &followparent_recalc,
1456};
1457
1458static struct clk fshostusb_fck = {
1459 .name = "fshostusb_fck",
1460 .parent = &core_48m_fck,
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1463 .flags = CLOCK_IN_OMAP3430ES1,
1464 .recalc = &followparent_recalc,
1465};
1466
1467/* CORE_12M_FCK based clocks */
1468
1469static struct clk core_12m_fck = {
1470 .name = "core_12m_fck",
1471 .parent = &omap_12m_fck,
1472 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1473 PARENT_CONTROLS_CLOCK,
1474 .recalc = &followparent_recalc,
1475};
1476
1477static struct clk hdq_fck = {
1478 .name = "hdq_fck",
1479 .parent = &core_12m_fck,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1481 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1482 .flags = CLOCK_IN_OMAP343X,
1483 .recalc = &followparent_recalc,
1484};
1485
1486/* DPLL3-derived clock */
1487
1488static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1489 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1490 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1491 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1492 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1493 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1494 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1495 { .div = 0 }
1496};
1497
1498static const struct clksel ssi_ssr_clksel[] = {
1499 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1500 { .parent = NULL }
1501};
1502
1503static struct clk ssi_ssr_fck = {
1504 .name = "ssi_ssr_fck",
1505 .init = &omap2_init_clksel_parent,
1506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1508 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1509 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1510 .clksel = ssi_ssr_clksel,
1511 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1512 .recalc = &omap2_clksel_recalc,
1513};
1514
1515static struct clk ssi_sst_fck = {
1516 .name = "ssi_sst_fck",
1517 .parent = &ssi_ssr_fck,
1518 .fixed_div = 2,
1519 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1520 .recalc = &omap2_fixed_divisor_recalc,
1521};
1522
1523
1524
1525/* CORE_L3_ICK based clocks */
1526
1527static struct clk core_l3_ick = {
1528 .name = "core_l3_ick",
1529 .parent = &l3_ick,
1530 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1531 PARENT_CONTROLS_CLOCK,
1532 .recalc = &followparent_recalc,
1533};
1534
1535static struct clk hsotgusb_ick = {
1536 .name = "hsotgusb_ick",
1537 .parent = &core_l3_ick,
1538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1539 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1540 .flags = CLOCK_IN_OMAP343X,
1541 .recalc = &followparent_recalc,
1542};
1543
1544static struct clk sdrc_ick = {
1545 .name = "sdrc_ick",
1546 .parent = &core_l3_ick,
1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1548 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1550 .recalc = &followparent_recalc,
1551};
1552
1553static struct clk gpmc_fck = {
1554 .name = "gpmc_fck",
1555 .parent = &core_l3_ick,
1556 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1557 ENABLE_ON_INIT,
1558 .recalc = &followparent_recalc,
1559};
1560
1561/* SECURITY_L3_ICK based clocks */
1562
1563static struct clk security_l3_ick = {
1564 .name = "security_l3_ick",
1565 .parent = &l3_ick,
1566 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1567 PARENT_CONTROLS_CLOCK,
1568 .recalc = &followparent_recalc,
1569};
1570
1571static struct clk pka_ick = {
1572 .name = "pka_ick",
1573 .parent = &security_l3_ick,
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1575 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1576 .flags = CLOCK_IN_OMAP343X,
1577 .recalc = &followparent_recalc,
1578};
1579
1580/* CORE_L4_ICK based clocks */
1581
1582static struct clk core_l4_ick = {
1583 .name = "core_l4_ick",
1584 .parent = &l4_ick,
1585 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1586 PARENT_CONTROLS_CLOCK,
1587 .recalc = &followparent_recalc,
1588};
1589
1590static struct clk usbtll_ick = {
1591 .name = "usbtll_ick",
1592 .parent = &core_l4_ick,
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1594 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1595 .flags = CLOCK_IN_OMAP3430ES2,
1596 .recalc = &followparent_recalc,
1597};
1598
1599static struct clk mmchs3_ick = {
1600 .name = "mmchs_ick",
1601 .id = 3,
1602 .parent = &core_l4_ick,
1603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1604 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1605 .flags = CLOCK_IN_OMAP3430ES2,
1606 .recalc = &followparent_recalc,
1607};
1608
1609/* Intersystem Communication Registers - chassis mode only */
1610static struct clk icr_ick = {
1611 .name = "icr_ick",
1612 .parent = &core_l4_ick,
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1615 .flags = CLOCK_IN_OMAP343X,
1616 .recalc = &followparent_recalc,
1617};
1618
1619static struct clk aes2_ick = {
1620 .name = "aes2_ick",
1621 .parent = &core_l4_ick,
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1624 .flags = CLOCK_IN_OMAP343X,
1625 .recalc = &followparent_recalc,
1626};
1627
1628static struct clk sha12_ick = {
1629 .name = "sha12_ick",
1630 .parent = &core_l4_ick,
1631 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1632 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1633 .flags = CLOCK_IN_OMAP343X,
1634 .recalc = &followparent_recalc,
1635};
1636
1637static struct clk des2_ick = {
1638 .name = "des2_ick",
1639 .parent = &core_l4_ick,
1640 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1641 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1642 .flags = CLOCK_IN_OMAP343X,
1643 .recalc = &followparent_recalc,
1644};
1645
1646static struct clk mmchs2_ick = {
1647 .name = "mmchs_ick",
1648 .id = 2,
1649 .parent = &core_l4_ick,
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1652 .flags = CLOCK_IN_OMAP343X,
1653 .recalc = &followparent_recalc,
1654};
1655
1656static struct clk mmchs1_ick = {
1657 .name = "mmchs_ick",
1658 .id = 1,
1659 .parent = &core_l4_ick,
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1661 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1662 .flags = CLOCK_IN_OMAP343X,
1663 .recalc = &followparent_recalc,
1664};
1665
1666static struct clk mspro_ick = {
1667 .name = "mspro_ick",
1668 .parent = &core_l4_ick,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1671 .flags = CLOCK_IN_OMAP343X,
1672 .recalc = &followparent_recalc,
1673};
1674
1675static struct clk hdq_ick = {
1676 .name = "hdq_ick",
1677 .parent = &core_l4_ick,
1678 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1679 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1680 .flags = CLOCK_IN_OMAP343X,
1681 .recalc = &followparent_recalc,
1682};
1683
1684static struct clk mcspi4_ick = {
1685 .name = "mcspi_ick",
1686 .id = 4,
1687 .parent = &core_l4_ick,
1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1690 .flags = CLOCK_IN_OMAP343X,
1691 .recalc = &followparent_recalc,
1692};
1693
1694static struct clk mcspi3_ick = {
1695 .name = "mcspi_ick",
1696 .id = 3,
1697 .parent = &core_l4_ick,
1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1700 .flags = CLOCK_IN_OMAP343X,
1701 .recalc = &followparent_recalc,
1702};
1703
1704static struct clk mcspi2_ick = {
1705 .name = "mcspi_ick",
1706 .id = 2,
1707 .parent = &core_l4_ick,
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1709 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1710 .flags = CLOCK_IN_OMAP343X,
1711 .recalc = &followparent_recalc,
1712};
1713
1714static struct clk mcspi1_ick = {
1715 .name = "mcspi_ick",
1716 .id = 1,
1717 .parent = &core_l4_ick,
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1719 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1720 .flags = CLOCK_IN_OMAP343X,
1721 .recalc = &followparent_recalc,
1722};
1723
1724static struct clk i2c3_ick = {
1725 .name = "i2c_ick",
1726 .id = 3,
1727 .parent = &core_l4_ick,
1728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1729 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1730 .flags = CLOCK_IN_OMAP343X,
1731 .recalc = &followparent_recalc,
1732};
1733
1734static struct clk i2c2_ick = {
1735 .name = "i2c_ick",
1736 .id = 2,
1737 .parent = &core_l4_ick,
1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1740 .flags = CLOCK_IN_OMAP343X,
1741 .recalc = &followparent_recalc,
1742};
1743
1744static struct clk i2c1_ick = {
1745 .name = "i2c_ick",
1746 .id = 1,
1747 .parent = &core_l4_ick,
1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1749 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1750 .flags = CLOCK_IN_OMAP343X,
1751 .recalc = &followparent_recalc,
1752};
1753
1754static struct clk uart2_ick = {
1755 .name = "uart2_ick",
1756 .parent = &core_l4_ick,
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1759 .flags = CLOCK_IN_OMAP343X,
1760 .recalc = &followparent_recalc,
1761};
1762
1763static struct clk uart1_ick = {
1764 .name = "uart1_ick",
1765 .parent = &core_l4_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1768 .flags = CLOCK_IN_OMAP343X,
1769 .recalc = &followparent_recalc,
1770};
1771
1772static struct clk gpt11_ick = {
1773 .name = "gpt11_ick",
1774 .parent = &core_l4_ick,
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1777 .flags = CLOCK_IN_OMAP343X,
1778 .recalc = &followparent_recalc,
1779};
1780
1781static struct clk gpt10_ick = {
1782 .name = "gpt10_ick",
1783 .parent = &core_l4_ick,
1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1785 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1786 .flags = CLOCK_IN_OMAP343X,
1787 .recalc = &followparent_recalc,
1788};
1789
1790static struct clk mcbsp5_ick = {
1791 .name = "mcbsp5_ick",
1792 .parent = &core_l4_ick,
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1795 .flags = CLOCK_IN_OMAP343X,
1796 .recalc = &followparent_recalc,
1797};
1798
1799static struct clk mcbsp1_ick = {
1800 .name = "mcbsp1_ick",
1801 .parent = &core_l4_ick,
1802 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1804 .flags = CLOCK_IN_OMAP343X,
1805 .recalc = &followparent_recalc,
1806};
1807
1808static struct clk fac_ick = {
1809 .name = "fac_ick",
1810 .parent = &core_l4_ick,
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1813 .flags = CLOCK_IN_OMAP3430ES1,
1814 .recalc = &followparent_recalc,
1815};
1816
1817static struct clk mailboxes_ick = {
1818 .name = "mailboxes_ick",
1819 .parent = &core_l4_ick,
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1822 .flags = CLOCK_IN_OMAP343X,
1823 .recalc = &followparent_recalc,
1824};
1825
1826static struct clk omapctrl_ick = {
1827 .name = "omapctrl_ick",
1828 .parent = &core_l4_ick,
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1831 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1832 .recalc = &followparent_recalc,
1833};
1834
1835/* SSI_L4_ICK based clocks */
1836
1837static struct clk ssi_l4_ick = {
1838 .name = "ssi_l4_ick",
1839 .parent = &l4_ick,
1840 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1841 .recalc = &followparent_recalc,
1842};
1843
1844static struct clk ssi_ick = {
1845 .name = "ssi_ick",
1846 .parent = &ssi_l4_ick,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1849 .flags = CLOCK_IN_OMAP343X,
1850 .recalc = &followparent_recalc,
1851};
1852
1853/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1854 * but l4_ick makes more sense to me */
1855
1856static const struct clksel usb_l4_clksel[] = {
1857 { .parent = &l4_ick, .rates = div2_rates },
1858 { .parent = NULL },
1859};
1860
1861static struct clk usb_l4_ick = {
1862 .name = "usb_l4_ick",
1863 .parent = &l4_ick,
1864 .init = &omap2_init_clksel_parent,
1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1867 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1868 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1869 .clksel = usb_l4_clksel,
1870 .flags = CLOCK_IN_OMAP3430ES1,
1871 .recalc = &omap2_clksel_recalc,
1872};
1873
1874/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1875
1876/* SECURITY_L4_ICK2 based clocks */
1877
1878static struct clk security_l4_ick2 = {
1879 .name = "security_l4_ick2",
1880 .parent = &l4_ick,
1881 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1882 PARENT_CONTROLS_CLOCK,
1883 .recalc = &followparent_recalc,
1884};
1885
1886static struct clk aes1_ick = {
1887 .name = "aes1_ick",
1888 .parent = &security_l4_ick2,
1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1890 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1891 .flags = CLOCK_IN_OMAP343X,
1892 .recalc = &followparent_recalc,
1893};
1894
1895static struct clk rng_ick = {
1896 .name = "rng_ick",
1897 .parent = &security_l4_ick2,
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1899 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1900 .flags = CLOCK_IN_OMAP343X,
1901 .recalc = &followparent_recalc,
1902};
1903
1904static struct clk sha11_ick = {
1905 .name = "sha11_ick",
1906 .parent = &security_l4_ick2,
1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1908 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1909 .flags = CLOCK_IN_OMAP343X,
1910 .recalc = &followparent_recalc,
1911};
1912
1913static struct clk des1_ick = {
1914 .name = "des1_ick",
1915 .parent = &security_l4_ick2,
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1917 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1918 .flags = CLOCK_IN_OMAP343X,
1919 .recalc = &followparent_recalc,
1920};
1921
1922/* DSS */
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1923static const struct clksel dss1_alwon_fck_clksel[] = {
1924 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1925 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1926 { .parent = NULL }
1927};
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1928
1929static struct clk dss1_alwon_fck = {
1930 .name = "dss1_alwon_fck",
1931 .parent = &dpll4_m4x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1932 .init = &omap2_init_clksel_parent,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1933 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1934 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1935 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1936 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1937 .clksel = dss1_alwon_fck_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1938 .flags = CLOCK_IN_OMAP343X,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1939 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1940};
1941
1942static struct clk dss_tv_fck = {
1943 .name = "dss_tv_fck",
1944 .parent = &omap_54m_fck,
1945 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1946 .enable_bit = OMAP3430_EN_TV_SHIFT,
1947 .flags = CLOCK_IN_OMAP343X,
1948 .recalc = &followparent_recalc,
1949};
1950
1951static struct clk dss_96m_fck = {
1952 .name = "dss_96m_fck",
1953 .parent = &omap_96m_fck,
1954 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1955 .enable_bit = OMAP3430_EN_TV_SHIFT,
1956 .flags = CLOCK_IN_OMAP343X,
1957 .recalc = &followparent_recalc,
1958};
1959
1960static struct clk dss2_alwon_fck = {
1961 .name = "dss2_alwon_fck",
1962 .parent = &sys_ck,
1963 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1964 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1965 .flags = CLOCK_IN_OMAP343X,
1966 .recalc = &followparent_recalc,
1967};
1968
1969static struct clk dss_ick = {
1970 /* Handles both L3 and L4 clocks */
1971 .name = "dss_ick",
1972 .parent = &l4_ick,
1973 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1974 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1975 .flags = CLOCK_IN_OMAP343X,
1976 .recalc = &followparent_recalc,
1977};
1978
1979/* CAM */
1980
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1981static const struct clksel cam_mclk_clksel[] = {
1982 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1983 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1984 { .parent = NULL }
1985};
1986
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1987static struct clk cam_mclk = {
1988 .name = "cam_mclk",
1989 .parent = &dpll4_m5x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1990 .init = &omap2_init_clksel_parent,
1991 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1992 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1993 .clksel = cam_mclk_clksel,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1994 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1995 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1996 .flags = CLOCK_IN_OMAP343X,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]1997 .recalc = &omap2_clksel_recalc,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]1998};
1999
2000static struct clk cam_l3_ick = {
2001 .name = "cam_l3_ick",
2002 .parent = &l3_ick,
2003 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2004 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2005 .flags = CLOCK_IN_OMAP343X,
2006 .recalc = &followparent_recalc,
2007};
2008
2009static struct clk cam_l4_ick = {
2010 .name = "cam_l4_ick",
2011 .parent = &l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2013 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2014 .flags = CLOCK_IN_OMAP343X,
2015 .recalc = &followparent_recalc,
2016};
2017
2018/* USBHOST - 3430ES2 only */
2019
2020static struct clk usbhost_120m_fck = {
2021 .name = "usbhost_120m_fck",
2022 .parent = &omap_120m_fck,
2023 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2024 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2025 .flags = CLOCK_IN_OMAP3430ES2,
2026 .recalc = &followparent_recalc,
2027};
2028
2029static struct clk usbhost_48m_fck = {
2030 .name = "usbhost_48m_fck",
2031 .parent = &omap_48m_fck,
2032 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2033 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2034 .flags = CLOCK_IN_OMAP3430ES2,
2035 .recalc = &followparent_recalc,
2036};
2037
2038static struct clk usbhost_l3_ick = {
2039 .name = "usbhost_l3_ick",
2040 .parent = &l3_ick,
2041 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2042 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2043 .flags = CLOCK_IN_OMAP3430ES2,
2044 .recalc = &followparent_recalc,
2045};
2046
2047static struct clk usbhost_l4_ick = {
2048 .name = "usbhost_l4_ick",
2049 .parent = &l4_ick,
2050 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2051 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2052 .flags = CLOCK_IN_OMAP3430ES2,
2053 .recalc = &followparent_recalc,
2054};
2055
2056static struct clk usbhost_sar_fck = {
2057 .name = "usbhost_sar_fck",
2058 .parent = &osc_sys_ck,
2059 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2060 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2061 .flags = CLOCK_IN_OMAP3430ES2,
2062 .recalc = &followparent_recalc,
2063};
2064
2065/* WKUP */
2066
2067static const struct clksel_rate usim_96m_rates[] = {
2068 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2069 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2070 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2071 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2072 { .div = 0 },
2073};
2074
2075static const struct clksel_rate usim_120m_rates[] = {
2076 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2077 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2078 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2079 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2080 { .div = 0 },
2081};
2082
2083static const struct clksel usim_clksel[] = {
2084 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2085 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2086 { .parent = &sys_ck, .rates = div2_rates },
2087 { .parent = NULL },
2088};
2089
2090/* 3430ES2 only */
2091static struct clk usim_fck = {
2092 .name = "usim_fck",
2093 .init = &omap2_init_clksel_parent,
2094 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2095 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2096 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2097 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2098 .clksel = usim_clksel,
2099 .flags = CLOCK_IN_OMAP3430ES2,
2100 .recalc = &omap2_clksel_recalc,
2101};
2102
2103static struct clk gpt1_fck = {
2104 .name = "gpt1_fck",
2105 .init = &omap2_init_clksel_parent,
2106 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2107 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2108 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2109 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2110 .clksel = omap343x_gpt_clksel,
2111 .flags = CLOCK_IN_OMAP343X,
2112 .recalc = &omap2_clksel_recalc,
2113};
2114
2115static struct clk wkup_32k_fck = {
2116 .name = "wkup_32k_fck",
2117 .parent = &omap_32k_fck,
2118 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2119 .recalc = &followparent_recalc,
2120};
2121
2122static struct clk gpio1_fck = {
2123 .name = "gpio1_fck",
2124 .parent = &wkup_32k_fck,
2125 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2126 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2127 .flags = CLOCK_IN_OMAP343X,
2128 .recalc = &followparent_recalc,
2129};
2130
2131static struct clk wdt2_fck = {
2132 .name = "wdt2_fck",
2133 .parent = &wkup_32k_fck,
2134 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2135 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2136 .flags = CLOCK_IN_OMAP343X,
2137 .recalc = &followparent_recalc,
2138};
2139
2140static struct clk wkup_l4_ick = {
2141 .name = "wkup_l4_ick",
2142 .parent = &sys_ck,
2143 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2144 .recalc = &followparent_recalc,
2145};
2146
2147/* 3430ES2 only */
2148/* Never specifically named in the TRM, so we have to infer a likely name */
2149static struct clk usim_ick = {
2150 .name = "usim_ick",
2151 .parent = &wkup_l4_ick,
2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2154 .flags = CLOCK_IN_OMAP3430ES2,
2155 .recalc = &followparent_recalc,
2156};
2157
2158static struct clk wdt2_ick = {
2159 .name = "wdt2_ick",
2160 .parent = &wkup_l4_ick,
2161 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2162 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2163 .flags = CLOCK_IN_OMAP343X,
2164 .recalc = &followparent_recalc,
2165};
2166
2167static struct clk wdt1_ick = {
2168 .name = "wdt1_ick",
2169 .parent = &wkup_l4_ick,
2170 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2171 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2172 .flags = CLOCK_IN_OMAP343X,
2173 .recalc = &followparent_recalc,
2174};
2175
2176static struct clk gpio1_ick = {
2177 .name = "gpio1_ick",
2178 .parent = &wkup_l4_ick,
2179 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2180 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2181 .flags = CLOCK_IN_OMAP343X,
2182 .recalc = &followparent_recalc,
2183};
2184
2185static struct clk omap_32ksync_ick = {
2186 .name = "omap_32ksync_ick",
2187 .parent = &wkup_l4_ick,
2188 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2189 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2190 .flags = CLOCK_IN_OMAP343X,
2191 .recalc = &followparent_recalc,
2192};
2193
2194static struct clk gpt12_ick = {
2195 .name = "gpt12_ick",
2196 .parent = &wkup_l4_ick,
2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2198 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2199 .flags = CLOCK_IN_OMAP343X,
2200 .recalc = &followparent_recalc,
2201};
2202
2203static struct clk gpt1_ick = {
2204 .name = "gpt1_ick",
2205 .parent = &wkup_l4_ick,
2206 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2207 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2208 .flags = CLOCK_IN_OMAP343X,
2209 .recalc = &followparent_recalc,
2210};
2211
2212
2213
2214/* PER clock domain */
2215
2216static struct clk per_96m_fck = {
2217 .name = "per_96m_fck",
2218 .parent = &omap_96m_alwon_fck,
2219 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2220 PARENT_CONTROLS_CLOCK,
2221 .recalc = &followparent_recalc,
2222};
2223
2224static struct clk per_48m_fck = {
2225 .name = "per_48m_fck",
2226 .parent = &omap_48m_fck,
2227 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2228 PARENT_CONTROLS_CLOCK,
2229 .recalc = &followparent_recalc,
2230};
2231
2232static struct clk uart3_fck = {
2233 .name = "uart3_fck",
2234 .parent = &per_48m_fck,
2235 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2236 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2237 .flags = CLOCK_IN_OMAP343X,
2238 .recalc = &followparent_recalc,
2239};
2240
2241static struct clk gpt2_fck = {
2242 .name = "gpt2_fck",
2243 .init = &omap2_init_clksel_parent,
2244 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2245 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2246 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2247 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2248 .clksel = omap343x_gpt_clksel,
2249 .flags = CLOCK_IN_OMAP343X,
2250 .recalc = &omap2_clksel_recalc,
2251};
2252
2253static struct clk gpt3_fck = {
2254 .name = "gpt3_fck",
2255 .init = &omap2_init_clksel_parent,
2256 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2257 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2258 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2259 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2260 .clksel = omap343x_gpt_clksel,
2261 .flags = CLOCK_IN_OMAP343X,
2262 .recalc = &omap2_clksel_recalc,
2263};
2264
2265static struct clk gpt4_fck = {
2266 .name = "gpt4_fck",
2267 .init = &omap2_init_clksel_parent,
2268 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2269 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2270 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2271 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2272 .clksel = omap343x_gpt_clksel,
2273 .flags = CLOCK_IN_OMAP343X,
2274 .recalc = &omap2_clksel_recalc,
2275};
2276
2277static struct clk gpt5_fck = {
2278 .name = "gpt5_fck",
2279 .init = &omap2_init_clksel_parent,
2280 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2281 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2282 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2283 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2284 .clksel = omap343x_gpt_clksel,
2285 .flags = CLOCK_IN_OMAP343X,
2286 .recalc = &omap2_clksel_recalc,
2287};
2288
2289static struct clk gpt6_fck = {
2290 .name = "gpt6_fck",
2291 .init = &omap2_init_clksel_parent,
2292 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2293 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2294 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2295 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2296 .clksel = omap343x_gpt_clksel,
2297 .flags = CLOCK_IN_OMAP343X,
2298 .recalc = &omap2_clksel_recalc,
2299};
2300
2301static struct clk gpt7_fck = {
2302 .name = "gpt7_fck",
2303 .init = &omap2_init_clksel_parent,
2304 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2305 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2306 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2307 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2308 .clksel = omap343x_gpt_clksel,
2309 .flags = CLOCK_IN_OMAP343X,
2310 .recalc = &omap2_clksel_recalc,
2311};
2312
2313static struct clk gpt8_fck = {
2314 .name = "gpt8_fck",
2315 .init = &omap2_init_clksel_parent,
2316 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2317 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2318 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2319 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2320 .clksel = omap343x_gpt_clksel,
2321 .flags = CLOCK_IN_OMAP343X,
2322 .recalc = &omap2_clksel_recalc,
2323};
2324
2325static struct clk gpt9_fck = {
2326 .name = "gpt9_fck",
2327 .init = &omap2_init_clksel_parent,
2328 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2329 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2330 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2331 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2332 .clksel = omap343x_gpt_clksel,
2333 .flags = CLOCK_IN_OMAP343X,
2334 .recalc = &omap2_clksel_recalc,
2335};
2336
2337static struct clk per_32k_alwon_fck = {
2338 .name = "per_32k_alwon_fck",
2339 .parent = &omap_32k_fck,
2340 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2341 .recalc = &followparent_recalc,
2342};
2343
2344static struct clk gpio6_fck = {
2345 .name = "gpio6_fck",
2346 .parent = &per_32k_alwon_fck,
2347 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +0200[diff] [blame]2348 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2349 .flags = CLOCK_IN_OMAP343X,
2350 .recalc = &followparent_recalc,
2351};
2352
2353static struct clk gpio5_fck = {
2354 .name = "gpio5_fck",
2355 .parent = &per_32k_alwon_fck,
2356 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +0200[diff] [blame]2357 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2358 .flags = CLOCK_IN_OMAP343X,
2359 .recalc = &followparent_recalc,
2360};
2361
2362static struct clk gpio4_fck = {
2363 .name = "gpio4_fck",
2364 .parent = &per_32k_alwon_fck,
2365 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +0200[diff] [blame]2366 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2367 .flags = CLOCK_IN_OMAP343X,
2368 .recalc = &followparent_recalc,
2369};
2370
2371static struct clk gpio3_fck = {
2372 .name = "gpio3_fck",
2373 .parent = &per_32k_alwon_fck,
2374 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +0200[diff] [blame]2375 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2376 .flags = CLOCK_IN_OMAP343X,
2377 .recalc = &followparent_recalc,
2378};
2379
2380static struct clk gpio2_fck = {
2381 .name = "gpio2_fck",
2382 .parent = &per_32k_alwon_fck,
2383 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
Jouni Höganderc3aa044a2008-03-28 14:57:50 +0200[diff] [blame]2384 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2385 .flags = CLOCK_IN_OMAP343X,
2386 .recalc = &followparent_recalc,
2387};
2388
2389static struct clk wdt3_fck = {
2390 .name = "wdt3_fck",
2391 .parent = &per_32k_alwon_fck,
2392 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2393 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2394 .flags = CLOCK_IN_OMAP343X,
2395 .recalc = &followparent_recalc,
2396};
2397
2398static struct clk per_l4_ick = {
2399 .name = "per_l4_ick",
2400 .parent = &l4_ick,
2401 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2402 PARENT_CONTROLS_CLOCK,
2403 .recalc = &followparent_recalc,
2404};
2405
2406static struct clk gpio6_ick = {
2407 .name = "gpio6_ick",
2408 .parent = &per_l4_ick,
2409 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2410 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2411 .flags = CLOCK_IN_OMAP343X,
2412 .recalc = &followparent_recalc,
2413};
2414
2415static struct clk gpio5_ick = {
2416 .name = "gpio5_ick",
2417 .parent = &per_l4_ick,
2418 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2419 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2420 .flags = CLOCK_IN_OMAP343X,
2421 .recalc = &followparent_recalc,
2422};
2423
2424static struct clk gpio4_ick = {
2425 .name = "gpio4_ick",
2426 .parent = &per_l4_ick,
2427 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2428 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2429 .flags = CLOCK_IN_OMAP343X,
2430 .recalc = &followparent_recalc,
2431};
2432
2433static struct clk gpio3_ick = {
2434 .name = "gpio3_ick",
2435 .parent = &per_l4_ick,
2436 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2437 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2438 .flags = CLOCK_IN_OMAP343X,
2439 .recalc = &followparent_recalc,
2440};
2441
2442static struct clk gpio2_ick = {
2443 .name = "gpio2_ick",
2444 .parent = &per_l4_ick,
2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2446 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2447 .flags = CLOCK_IN_OMAP343X,
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk wdt3_ick = {
2452 .name = "wdt3_ick",
2453 .parent = &per_l4_ick,
2454 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2455 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2456 .flags = CLOCK_IN_OMAP343X,
2457 .recalc = &followparent_recalc,
2458};
2459
2460static struct clk uart3_ick = {
2461 .name = "uart3_ick",
2462 .parent = &per_l4_ick,
2463 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2464 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2465 .flags = CLOCK_IN_OMAP343X,
2466 .recalc = &followparent_recalc,
2467};
2468
2469static struct clk gpt9_ick = {
2470 .name = "gpt9_ick",
2471 .parent = &per_l4_ick,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2473 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2474 .flags = CLOCK_IN_OMAP343X,
2475 .recalc = &followparent_recalc,
2476};
2477
2478static struct clk gpt8_ick = {
2479 .name = "gpt8_ick",
2480 .parent = &per_l4_ick,
2481 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2482 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2483 .flags = CLOCK_IN_OMAP343X,
2484 .recalc = &followparent_recalc,
2485};
2486
2487static struct clk gpt7_ick = {
2488 .name = "gpt7_ick",
2489 .parent = &per_l4_ick,
2490 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2491 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2492 .flags = CLOCK_IN_OMAP343X,
2493 .recalc = &followparent_recalc,
2494};
2495
2496static struct clk gpt6_ick = {
2497 .name = "gpt6_ick",
2498 .parent = &per_l4_ick,
2499 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2500 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2501 .flags = CLOCK_IN_OMAP343X,
2502 .recalc = &followparent_recalc,
2503};
2504
2505static struct clk gpt5_ick = {
2506 .name = "gpt5_ick",
2507 .parent = &per_l4_ick,
2508 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2509 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2510 .flags = CLOCK_IN_OMAP343X,
2511 .recalc = &followparent_recalc,
2512};
2513
2514static struct clk gpt4_ick = {
2515 .name = "gpt4_ick",
2516 .parent = &per_l4_ick,
2517 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2518 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2519 .flags = CLOCK_IN_OMAP343X,
2520 .recalc = &followparent_recalc,
2521};
2522
2523static struct clk gpt3_ick = {
2524 .name = "gpt3_ick",
2525 .parent = &per_l4_ick,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2527 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2528 .flags = CLOCK_IN_OMAP343X,
2529 .recalc = &followparent_recalc,
2530};
2531
2532static struct clk gpt2_ick = {
2533 .name = "gpt2_ick",
2534 .parent = &per_l4_ick,
2535 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2536 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2537 .flags = CLOCK_IN_OMAP343X,
2538 .recalc = &followparent_recalc,
2539};
2540
2541static struct clk mcbsp2_ick = {
2542 .name = "mcbsp2_ick",
2543 .parent = &per_l4_ick,
2544 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2545 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2546 .flags = CLOCK_IN_OMAP343X,
2547 .recalc = &followparent_recalc,
2548};
2549
2550static struct clk mcbsp3_ick = {
2551 .name = "mcbsp3_ick",
2552 .parent = &per_l4_ick,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2554 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2555 .flags = CLOCK_IN_OMAP343X,
2556 .recalc = &followparent_recalc,
2557};
2558
2559static struct clk mcbsp4_ick = {
2560 .name = "mcbsp4_ick",
2561 .parent = &per_l4_ick,
2562 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2563 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2564 .flags = CLOCK_IN_OMAP343X,
2565 .recalc = &followparent_recalc,
2566};
2567
2568static const struct clksel mcbsp_234_clksel[] = {
2569 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2570 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2571 { .parent = NULL }
2572};
2573
2574static struct clk mcbsp2_fck = {
2575 .name = "mcbsp2_fck",
2576 .init = &omap2_init_clksel_parent,
2577 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2579 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2580 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2581 .clksel = mcbsp_234_clksel,
2582 .flags = CLOCK_IN_OMAP343X,
2583 .recalc = &omap2_clksel_recalc,
2584};
2585
2586static struct clk mcbsp3_fck = {
2587 .name = "mcbsp3_fck",
2588 .init = &omap2_init_clksel_parent,
2589 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2591 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2592 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2593 .clksel = mcbsp_234_clksel,
2594 .flags = CLOCK_IN_OMAP343X,
2595 .recalc = &omap2_clksel_recalc,
2596};
2597
2598static struct clk mcbsp4_fck = {
2599 .name = "mcbsp4_fck",
2600 .init = &omap2_init_clksel_parent,
2601 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2602 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2603 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2604 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2605 .clksel = mcbsp_234_clksel,
2606 .flags = CLOCK_IN_OMAP343X,
2607 .recalc = &omap2_clksel_recalc,
2608};
2609
2610/* EMU clocks */
2611
2612/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2613
2614static const struct clksel_rate emu_src_sys_rates[] = {
2615 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2616 { .div = 0 },
2617};
2618
2619static const struct clksel_rate emu_src_core_rates[] = {
2620 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2621 { .div = 0 },
2622};
2623
2624static const struct clksel_rate emu_src_per_rates[] = {
2625 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2626 { .div = 0 },
2627};
2628
2629static const struct clksel_rate emu_src_mpu_rates[] = {
2630 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2631 { .div = 0 },
2632};
2633
2634static const struct clksel emu_src_clksel[] = {
2635 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2636 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2637 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2638 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2639 { .parent = NULL },
2640};
2641
2642/*
2643 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2644 * to switch the source of some of the EMU clocks.
2645 * XXX Are there CLKEN bits for these EMU clks?
2646 */
2647static struct clk emu_src_ck = {
2648 .name = "emu_src_ck",
2649 .init = &omap2_init_clksel_parent,
2650 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2651 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2652 .clksel = emu_src_clksel,
2653 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2654 .recalc = &omap2_clksel_recalc,
2655};
2656
2657static const struct clksel_rate pclk_emu_rates[] = {
2658 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2659 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2660 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2661 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2662 { .div = 0 },
2663};
2664
2665static const struct clksel pclk_emu_clksel[] = {
2666 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2667 { .parent = NULL },
2668};
2669
2670static struct clk pclk_fck = {
2671 .name = "pclk_fck",
2672 .init = &omap2_init_clksel_parent,
2673 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2674 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2675 .clksel = pclk_emu_clksel,
2676 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2677 .recalc = &omap2_clksel_recalc,
2678};
2679
2680static const struct clksel_rate pclkx2_emu_rates[] = {
2681 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2682 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2683 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2684 { .div = 0 },
2685};
2686
2687static const struct clksel pclkx2_emu_clksel[] = {
2688 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2689 { .parent = NULL },
2690};
2691
2692static struct clk pclkx2_fck = {
2693 .name = "pclkx2_fck",
2694 .init = &omap2_init_clksel_parent,
2695 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2696 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2697 .clksel = pclkx2_emu_clksel,
2698 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2699 .recalc = &omap2_clksel_recalc,
2700};
2701
2702static const struct clksel atclk_emu_clksel[] = {
2703 { .parent = &emu_src_ck, .rates = div2_rates },
2704 { .parent = NULL },
2705};
2706
2707static struct clk atclk_fck = {
2708 .name = "atclk_fck",
2709 .init = &omap2_init_clksel_parent,
2710 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2711 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2712 .clksel = atclk_emu_clksel,
2713 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2714 .recalc = &omap2_clksel_recalc,
2715};
2716
2717static struct clk traceclk_src_fck = {
2718 .name = "traceclk_src_fck",
2719 .init = &omap2_init_clksel_parent,
2720 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2721 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2722 .clksel = emu_src_clksel,
2723 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2724 .recalc = &omap2_clksel_recalc,
2725};
2726
2727static const struct clksel_rate traceclk_rates[] = {
2728 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2729 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2730 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2731 { .div = 0 },
2732};
2733
2734static const struct clksel traceclk_clksel[] = {
2735 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2736 { .parent = NULL },
2737};
2738
2739static struct clk traceclk_fck = {
2740 .name = "traceclk_fck",
2741 .init = &omap2_init_clksel_parent,
2742 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2743 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2744 .clksel = traceclk_clksel,
2745 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2746 .recalc = &omap2_clksel_recalc,
2747};
2748
2749/* SR clocks */
2750
2751/* SmartReflex fclk (VDD1) */
2752static struct clk sr1_fck = {
2753 .name = "sr1_fck",
2754 .parent = &sys_ck,
2755 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2756 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2757 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2758 .recalc = &followparent_recalc,
2759};
2760
2761/* SmartReflex fclk (VDD2) */
2762static struct clk sr2_fck = {
2763 .name = "sr2_fck",
2764 .parent = &sys_ck,
2765 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2766 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2768 .recalc = &followparent_recalc,
2769};
2770
2771static struct clk sr_l4_ick = {
2772 .name = "sr_l4_ick",
2773 .parent = &l4_ick,
2774 .flags = CLOCK_IN_OMAP343X,
2775 .recalc = &followparent_recalc,
2776};
2777
2778/* SECURE_32K_FCK clocks */
2779
2780static struct clk gpt12_fck = {
2781 .name = "gpt12_fck",
2782 .parent = &secure_32k_fck,
2783 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2784 .recalc = &followparent_recalc,
2785};
2786
2787static struct clk wdt1_fck = {
2788 .name = "wdt1_fck",
2789 .parent = &secure_32k_fck,
2790 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2791 .recalc = &followparent_recalc,
2792};
2793
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2794static struct clk *onchip_34xx_clks[] __initdata = {
2795 &omap_32k_fck,
2796 &virt_12m_ck,
2797 &virt_13m_ck,
2798 &virt_16_8m_ck,
2799 &virt_19_2m_ck,
2800 &virt_26m_ck,
2801 &virt_38_4m_ck,
2802 &osc_sys_ck,
2803 &sys_ck,
2804 &sys_altclk,
2805 &mcbsp_clks,
2806 &sys_clkout1,
2807 &dpll1_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2808 &dpll1_x2_ck,
2809 &dpll1_x2m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2810 &dpll2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2811 &dpll2_m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2812 &dpll3_ck,
2813 &core_ck,
2814 &dpll3_x2_ck,
2815 &dpll3_m2_ck,
2816 &dpll3_m2x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2817 &dpll3_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2818 &dpll3_m3x2_ck,
2819 &emu_core_alwon_ck,
2820 &dpll4_ck,
2821 &dpll4_x2_ck,
2822 &omap_96m_alwon_fck,
2823 &omap_96m_fck,
2824 &cm_96m_fck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2825 &virt_omap_54m_fck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2826 &omap_54m_fck,
2827 &omap_48m_fck,
2828 &omap_12m_fck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2829 &dpll4_m2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2830 &dpll4_m2x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2831 &dpll4_m3_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2832 &dpll4_m3x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2833 &dpll4_m4_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2834 &dpll4_m4x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2835 &dpll4_m5_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2836 &dpll4_m5x2_ck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2837 &dpll4_m6_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2838 &dpll4_m6x2_ck,
2839 &emu_per_alwon_ck,
2840 &dpll5_ck,
2841 &dpll5_m2_ck,
2842 &omap_120m_fck,
2843 &clkout2_src_ck,
2844 &sys_clkout2,
2845 &corex2_fck,
2846 &dpll1_fck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2847 &mpu_ck,
2848 &arm_fck,
2849 &emu_mpu_alwon_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2850 &dpll2_fck,
Roman Tereshonkov3760d312008-03-13 21:35:09 +0200[diff] [blame]2851 &iva2_ck,
Paul Walmsleyb045d082008-03-18 11:24:28 +0200[diff] [blame]2852 &l3_ick,
2853 &l4_ick,
2854 &rm_ick,
2855 &gfx_l3_fck,
2856 &gfx_l3_ick,
2857 &gfx_cg1_ck,
2858 &gfx_cg2_ck,
2859 &sgx_fck,
2860 &sgx_ick,
2861 &d2d_26m_fck,
2862 &gpt10_fck,
2863 &gpt11_fck,
2864 &cpefuse_fck,
2865 &ts_fck,
2866 &usbtll_fck,
2867 &core_96m_fck,
2868 &mmchs3_fck,
2869 &mmchs2_fck,
2870 &mspro_fck,
2871 &mmchs1_fck,
2872 &i2c3_fck,
2873 &i2c2_fck,
2874 &i2c1_fck,
2875 &mcbsp5_fck,
2876 &mcbsp1_fck,
2877 &core_48m_fck,
2878 &mcspi4_fck,
2879 &mcspi3_fck,
2880 &mcspi2_fck,
2881 &mcspi1_fck,
2882 &uart2_fck,
2883 &uart1_fck,
2884 &fshostusb_fck,
2885 &core_12m_fck,
2886 &hdq_fck,
2887 &ssi_ssr_fck,
2888 &ssi_sst_fck,
2889 &core_l3_ick,
2890 &hsotgusb_ick,
2891 &sdrc_ick,
2892 &gpmc_fck,
2893 &security_l3_ick,
2894 &pka_ick,
2895 &core_l4_ick,
2896 &usbtll_ick,
2897 &mmchs3_ick,
2898 &icr_ick,
2899 &aes2_ick,
2900 &sha12_ick,
2901 &des2_ick,
2902 &mmchs2_ick,
2903 &mmchs1_ick,
2904 &mspro_ick,
2905 &hdq_ick,
2906 &mcspi4_ick,
2907 &mcspi3_ick,
2908 &mcspi2_ick,
2909 &mcspi1_ick,
2910 &i2c3_ick,
2911 &i2c2_ick,
2912 &i2c1_ick,
2913 &uart2_ick,
2914 &uart1_ick,
2915 &gpt11_ick,
2916 &gpt10_ick,
2917 &mcbsp5_ick,
2918 &mcbsp1_ick,
2919 &fac_ick,
2920 &mailboxes_ick,
2921 &omapctrl_ick,
2922 &ssi_l4_ick,
2923 &ssi_ick,
2924 &usb_l4_ick,
2925 &security_l4_ick2,
2926 &aes1_ick,
2927 &rng_ick,
2928 &sha11_ick,
2929 &des1_ick,
2930 &dss1_alwon_fck,
2931 &dss_tv_fck,
2932 &dss_96m_fck,
2933 &dss2_alwon_fck,
2934 &dss_ick,
2935 &cam_mclk,
2936 &cam_l3_ick,
2937 &cam_l4_ick,
2938 &usbhost_120m_fck,
2939 &usbhost_48m_fck,
2940 &usbhost_l3_ick,
2941 &usbhost_l4_ick,
2942 &usbhost_sar_fck,
2943 &usim_fck,
2944 &gpt1_fck,
2945 &wkup_32k_fck,
2946 &gpio1_fck,
2947 &wdt2_fck,
2948 &wkup_l4_ick,
2949 &usim_ick,
2950 &wdt2_ick,
2951 &wdt1_ick,
2952 &gpio1_ick,
2953 &omap_32ksync_ick,
2954 &gpt12_ick,
2955 &gpt1_ick,
2956 &per_96m_fck,
2957 &per_48m_fck,
2958 &uart3_fck,
2959 &gpt2_fck,
2960 &gpt3_fck,
2961 &gpt4_fck,
2962 &gpt5_fck,
2963 &gpt6_fck,
2964 &gpt7_fck,
2965 &gpt8_fck,
2966 &gpt9_fck,
2967 &per_32k_alwon_fck,
2968 &gpio6_fck,
2969 &gpio5_fck,
2970 &gpio4_fck,
2971 &gpio3_fck,
2972 &gpio2_fck,
2973 &wdt3_fck,
2974 &per_l4_ick,
2975 &gpio6_ick,
2976 &gpio5_ick,
2977 &gpio4_ick,
2978 &gpio3_ick,
2979 &gpio2_ick,
2980 &wdt3_ick,
2981 &uart3_ick,
2982 &gpt9_ick,
2983 &gpt8_ick,
2984 &gpt7_ick,
2985 &gpt6_ick,
2986 &gpt5_ick,
2987 &gpt4_ick,
2988 &gpt3_ick,
2989 &gpt2_ick,
2990 &mcbsp2_ick,
2991 &mcbsp3_ick,
2992 &mcbsp4_ick,
2993 &mcbsp2_fck,
2994 &mcbsp3_fck,
2995 &mcbsp4_fck,
2996 &emu_src_ck,
2997 &pclk_fck,
2998 &pclkx2_fck,
2999 &atclk_fck,
3000 &traceclk_src_fck,
3001 &traceclk_fck,
3002 &sr1_fck,
3003 &sr2_fck,
3004 &sr_l4_ick,
3005 &secure_32k_fck,
3006 &gpt12_fck,
3007 &wdt1_fck,
3008};
3009
3010#endif