arch/arm/boot/dts/imx6q-sabrelite.dts

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx6q.dtsi"

/ {
	model = "Freescale i.MX6 Quad SABRE Lite Board";
	compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";

	memory {
		reg = <0x10000000 0x40000000>;
	};

	regulators {
		compatible = "simple-bus";

		reg_2p5v: 2p5v {
			compatible = "regulator-fixed";
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: 3p3v {
			compatible = "regulator-fixed";
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_usb_otg_vbus: usb_otg_vbus {
			compatible = "regulator-fixed";
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 0>;
			enable-active-high;
		};
	};

	sound {
		compatible = "fsl,imx6q-sabrelite-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6q-sabrelite-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};
};

&audmux {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux_1>;
};

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio3 19 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_1>;
	status = "okay";

	flash: m25p80@0 {
		compatible = "sst,sst25vf016b";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet_1>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 23 0>;
	status = "okay";
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1_1>;

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	hog {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
				MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x80000000
				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
				MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
				MX6QDL_PAD_EIM_D23__GPIO3_IO23	0x80000000
			>;
		};
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&sata {
	status = "okay";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_1>;
};

&usbh1 {
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg_1>;
	disable-over-current;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3_2>;
	cd-gpios = <&gpio7 0 0>;
	wp-gpios = <&gpio7 1 0>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4_2>;
	cd-gpios = <&gpio2 6 0>;
	wp-gpios = <&gpio2 7 0>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};