blob: 93e9f7e0b7ad22bdd1d0a096902bf80d8cd2be2d [file] [log] [blame]
Stephen Boydc4464072012-09-05 12:28:58 -07001/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8960 CDP";
7 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
8 interrupt-parent = <&intc>;
9
10 intc: interrupt-controller@2000000 {
11 compatible = "qcom,msm-qgic2";
12 interrupt-controller;
13 #interrupt-cells = <3>;
14 reg = < 0x02000000 0x1000 >,
15 < 0x02002000 0x1000 >;
16 };
17
Stephen Boydeebdb0c2013-03-14 20:31:38 -070018 timer@200a000 {
19 compatible = "qcom,kpss-timer", "qcom,msm-timer";
20 interrupts = <1 1 0x301>,
21 <1 2 0x301>,
22 <1 3 0x301>;
23 reg = <0x0200a000 0x100>;
24 clock-frequency = <27000000>,
25 <32768>;
Stephen Boydc4464072012-09-05 12:28:58 -070026 cpu-offset = <0x80000>;
27 };
28
Rohit Vaswania39a9f72013-06-18 18:53:31 -070029 msmgpio: gpio@800000 {
Rohit Vaswani43f68442013-06-10 15:50:21 -070030 compatible = "qcom,msm-gpio";
31 gpio-controller;
32 #gpio-cells = <2>;
33 ngpio = <150>;
34 interrupts = <0 32 0x4>;
35 interrupt-controller;
36 #interrupt-cells = <2>;
Rohit Vaswania39a9f72013-06-18 18:53:31 -070037 reg = <0x800000 0x4000>;
Rohit Vaswani43f68442013-06-10 15:50:21 -070038 };
39
David Brownf333c132013-06-17 13:39:38 -070040 serial@16440000 {
Stephen Boyd9dfe59f12013-08-28 13:32:41 -070041 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
Stephen Boydc4464072012-09-05 12:28:58 -070042 reg = <0x16440000 0x1000>,
43 <0x16400000 0x1000>;
44 interrupts = <0 154 0x0>;
45 };
David Brown97f00f72013-03-12 11:41:50 -070046
47 qcom,ssbi@500000 {
48 compatible = "qcom,ssbi";
49 reg = <0x500000 0x1000>;
50 qcom,controller-type = "pmic-arbiter";
51 };
Stephen Boydc4464072012-09-05 12:28:58 -070052};