Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include <drm/drmP.h> |
| 28 | #include <drm/drm_crtc.h> |
| 29 | #include <drm/drm_edid.h> |
| 30 | #include <drm/i915_drm.h> |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 31 | #include <drm/drm_panel.h> |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 32 | #include <linux/slab.h> |
| 33 | #include <video/mipi_display.h> |
| 34 | #include <asm/intel-mid.h> |
| 35 | #include <video/mipi_display.h> |
| 36 | #include "i915_drv.h" |
| 37 | #include "intel_drv.h" |
| 38 | #include "intel_dsi.h" |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 39 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 40 | struct vbt_panel { |
| 41 | struct drm_panel panel; |
| 42 | struct intel_dsi *intel_dsi; |
| 43 | }; |
| 44 | |
| 45 | static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) |
| 46 | { |
| 47 | return container_of(panel, struct vbt_panel, panel); |
| 48 | } |
| 49 | |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 50 | #define MIPI_TRANSFER_MODE_SHIFT 0 |
| 51 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 |
| 52 | #define MIPI_PORT_SHIFT 3 |
| 53 | |
| 54 | #define PREPARE_CNT_MAX 0x3F |
| 55 | #define EXIT_ZERO_CNT_MAX 0x3F |
| 56 | #define CLK_ZERO_CNT_MAX 0xFF |
| 57 | #define TRAIL_CNT_MAX 0x1F |
| 58 | |
| 59 | #define NS_KHZ_RATIO 1000000 |
| 60 | |
Jani Nikula | b0c91cd | 2016-04-05 22:30:49 +0300 | [diff] [blame] | 61 | /* base offsets for gpio pads */ |
| 62 | #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 |
| 63 | #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 |
| 64 | #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 |
| 65 | #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 |
| 66 | #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 |
| 67 | #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 |
| 68 | #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 |
| 69 | #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 |
| 70 | #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 |
| 71 | #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 |
| 72 | #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 |
| 73 | #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 |
| 74 | |
| 75 | #define VLV_GPIO_PCONF0(base_offset) (base_offset) |
| 76 | #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 77 | |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 78 | struct gpio_map { |
Jani Nikula | b0c91cd | 2016-04-05 22:30:49 +0300 | [diff] [blame] | 79 | u16 base_offset; |
| 80 | bool init; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 81 | }; |
| 82 | |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 83 | static struct gpio_map vlv_gpio_table[] = { |
Jani Nikula | b0c91cd | 2016-04-05 22:30:49 +0300 | [diff] [blame] | 84 | { VLV_GPIO_NC_0_HV_DDI0_HPD }, |
| 85 | { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, |
| 86 | { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, |
| 87 | { VLV_GPIO_NC_3_PANEL0_VDDEN }, |
| 88 | { VLV_GPIO_NC_4_PANEL0_BKLTEN }, |
| 89 | { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, |
| 90 | { VLV_GPIO_NC_6_HV_DDI1_HPD }, |
| 91 | { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, |
| 92 | { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, |
| 93 | { VLV_GPIO_NC_9_PANEL1_VDDEN }, |
| 94 | { VLV_GPIO_NC_10_PANEL1_BKLTEN }, |
| 95 | { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 96 | }; |
| 97 | |
Jani Nikula | a0a6d4f | 2016-04-26 13:27:40 +0300 | [diff] [blame] | 98 | #define CHV_GPIO_IDX_START_N 0 |
| 99 | #define CHV_GPIO_IDX_START_E 73 |
| 100 | #define CHV_GPIO_IDX_START_SW 100 |
| 101 | #define CHV_GPIO_IDX_START_SE 198 |
| 102 | |
| 103 | #define CHV_VBT_MAX_PINS_PER_FMLY 15 |
| 104 | |
| 105 | #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) |
| 106 | #define CHV_GPIO_GPIOEN (1 << 15) |
| 107 | #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) |
| 108 | #define CHV_GPIO_GPIOCFG_GPO (1 << 8) |
| 109 | #define CHV_GPIO_GPIOCFG_GPI (2 << 8) |
| 110 | #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) |
| 111 | #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) |
| 112 | |
| 113 | #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) |
| 114 | #define CHV_GPIO_CFGLOCK (1 << 31) |
| 115 | |
Gaurav K Singh | 8f4d268 | 2014-12-04 10:58:48 +0530 | [diff] [blame] | 116 | static inline enum port intel_dsi_seq_port_to_port(u8 port) |
| 117 | { |
| 118 | return port ? PORT_C : PORT_A; |
| 119 | } |
| 120 | |
Jani Nikula | 5b48ca0 | 2015-01-16 14:27:21 +0200 | [diff] [blame] | 121 | static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, |
| 122 | const u8 *data) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 123 | { |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 124 | struct mipi_dsi_device *dsi_device; |
| 125 | u8 type, flags, seq_port; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 126 | u16 len; |
Gaurav K Singh | 8f4d268 | 2014-12-04 10:58:48 +0530 | [diff] [blame] | 127 | enum port port; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 128 | |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 129 | flags = *data++; |
| 130 | type = *data++; |
| 131 | |
| 132 | len = *((u16 *) data); |
| 133 | data += 2; |
| 134 | |
| 135 | seq_port = (flags >> MIPI_PORT_SHIFT) & 3; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 136 | |
Gaurav K Singh | f915084 | 2014-12-10 22:07:40 +0530 | [diff] [blame] | 137 | /* For DSI single link on Port A & C, the seq_port value which is |
| 138 | * parsed from Sequence Block#53 of VBT has been set to 0 |
| 139 | * Now, read/write of packets for the DSI single link on Port A and |
| 140 | * Port C will based on the DVO port from VBT block 2. |
| 141 | */ |
| 142 | if (intel_dsi->ports == (1 << PORT_C)) |
| 143 | port = PORT_C; |
| 144 | else |
| 145 | port = intel_dsi_seq_port_to_port(seq_port); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 146 | |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 147 | dsi_device = intel_dsi->dsi_hosts[port]->device; |
| 148 | if (!dsi_device) { |
| 149 | DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); |
| 150 | goto out; |
| 151 | } |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 152 | |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 153 | if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) |
| 154 | dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; |
| 155 | else |
| 156 | dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; |
| 157 | |
| 158 | dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 159 | |
| 160 | switch (type) { |
| 161 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 162 | mipi_dsi_generic_write(dsi_device, NULL, 0); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 163 | break; |
| 164 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 165 | mipi_dsi_generic_write(dsi_device, data, 1); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 166 | break; |
| 167 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 168 | mipi_dsi_generic_write(dsi_device, data, 2); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 169 | break; |
| 170 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: |
| 171 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: |
| 172 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: |
| 173 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); |
| 174 | break; |
| 175 | case MIPI_DSI_GENERIC_LONG_WRITE: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 176 | mipi_dsi_generic_write(dsi_device, data, len); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 177 | break; |
| 178 | case MIPI_DSI_DCS_SHORT_WRITE: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 179 | mipi_dsi_dcs_write_buffer(dsi_device, data, 1); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 180 | break; |
| 181 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 182 | mipi_dsi_dcs_write_buffer(dsi_device, data, 2); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 183 | break; |
| 184 | case MIPI_DSI_DCS_READ: |
| 185 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); |
| 186 | break; |
| 187 | case MIPI_DSI_DCS_LONG_WRITE: |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 188 | mipi_dsi_dcs_write_buffer(dsi_device, data, len); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 189 | break; |
Shobhit Kumar | b5fbcd98 | 2014-05-27 19:23:46 +0530 | [diff] [blame] | 190 | } |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 191 | |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 192 | out: |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 193 | data += len; |
| 194 | |
| 195 | return data; |
| 196 | } |
| 197 | |
Jani Nikula | 5b48ca0 | 2015-01-16 14:27:21 +0200 | [diff] [blame] | 198 | static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 199 | { |
Jani Nikula | 5b48ca0 | 2015-01-16 14:27:21 +0200 | [diff] [blame] | 200 | u32 delay = *((const u32 *) data); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 201 | |
| 202 | usleep_range(delay, delay + 10); |
| 203 | data += 4; |
| 204 | |
| 205 | return data; |
| 206 | } |
| 207 | |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 208 | static void vlv_exec_gpio(struct drm_i915_private *dev_priv, |
| 209 | u8 gpio_source, u8 gpio_index, bool value) |
| 210 | { |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 211 | struct gpio_map *map; |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 212 | u16 pconf0, padval; |
| 213 | u32 tmp; |
| 214 | u8 port; |
| 215 | |
| 216 | if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { |
| 217 | DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); |
| 218 | return; |
| 219 | } |
| 220 | |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 221 | map = &vlv_gpio_table[gpio_index]; |
| 222 | |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 223 | if (dev_priv->vbt.dsi.seq_version >= 3) { |
Jani Nikula | 4b541ef | 2016-04-26 13:27:39 +0300 | [diff] [blame] | 224 | /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ |
| 225 | port = IOSF_PORT_GPIO_NC; |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 226 | } else { |
| 227 | if (gpio_source == 0) { |
| 228 | port = IOSF_PORT_GPIO_NC; |
| 229 | } else if (gpio_source == 1) { |
Jani Nikula | 060d4c3 | 2016-04-07 17:26:18 +0300 | [diff] [blame] | 230 | DRM_DEBUG_KMS("SC gpio not supported\n"); |
| 231 | return; |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 232 | } else { |
| 233 | DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); |
| 234 | return; |
| 235 | } |
| 236 | } |
| 237 | |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 238 | pconf0 = VLV_GPIO_PCONF0(map->base_offset); |
| 239 | padval = VLV_GPIO_PAD_VAL(map->base_offset); |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 240 | |
| 241 | mutex_lock(&dev_priv->sb_lock); |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 242 | if (!map->init) { |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 243 | /* FIXME: remove constant below */ |
| 244 | vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); |
Jani Nikula | b13d8e2 | 2016-04-07 16:36:54 +0300 | [diff] [blame] | 245 | map->init = true; |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 246 | } |
| 247 | |
| 248 | tmp = 0x4 | value; |
| 249 | vlv_iosf_sb_write(dev_priv, port, padval, tmp); |
| 250 | mutex_unlock(&dev_priv->sb_lock); |
| 251 | } |
| 252 | |
Jani Nikula | a0a6d4f | 2016-04-26 13:27:40 +0300 | [diff] [blame] | 253 | static void chv_exec_gpio(struct drm_i915_private *dev_priv, |
| 254 | u8 gpio_source, u8 gpio_index, bool value) |
| 255 | { |
| 256 | u16 cfg0, cfg1; |
| 257 | u16 family_num; |
| 258 | u8 port; |
| 259 | |
| 260 | if (dev_priv->vbt.dsi.seq_version >= 3) { |
| 261 | if (gpio_index >= CHV_GPIO_IDX_START_SE) { |
| 262 | /* XXX: it's unclear whether 255->57 is part of SE. */ |
| 263 | gpio_index -= CHV_GPIO_IDX_START_SE; |
| 264 | port = CHV_IOSF_PORT_GPIO_SE; |
| 265 | } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { |
| 266 | gpio_index -= CHV_GPIO_IDX_START_SW; |
| 267 | port = CHV_IOSF_PORT_GPIO_SW; |
| 268 | } else if (gpio_index >= CHV_GPIO_IDX_START_E) { |
| 269 | gpio_index -= CHV_GPIO_IDX_START_E; |
| 270 | port = CHV_IOSF_PORT_GPIO_E; |
| 271 | } else { |
| 272 | port = CHV_IOSF_PORT_GPIO_N; |
| 273 | } |
| 274 | } else { |
| 275 | /* XXX: The spec is unclear about CHV GPIO on seq v2 */ |
| 276 | if (gpio_source != 0) { |
| 277 | DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); |
| 278 | return; |
| 279 | } |
| 280 | |
| 281 | if (gpio_index >= CHV_GPIO_IDX_START_E) { |
| 282 | DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n", |
| 283 | gpio_index); |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | port = CHV_IOSF_PORT_GPIO_N; |
| 288 | } |
| 289 | |
| 290 | family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; |
| 291 | gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; |
| 292 | |
| 293 | cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); |
| 294 | cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); |
| 295 | |
| 296 | mutex_lock(&dev_priv->sb_lock); |
| 297 | vlv_iosf_sb_write(dev_priv, port, cfg1, 0); |
| 298 | vlv_iosf_sb_write(dev_priv, port, cfg0, |
Hans de Goede | 6cb4179 | 2016-12-01 21:29:09 +0100 | [diff] [blame] | 299 | CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | |
| 300 | CHV_GPIO_GPIOTXSTATE(value)); |
Jani Nikula | a0a6d4f | 2016-04-26 13:27:40 +0300 | [diff] [blame] | 301 | mutex_unlock(&dev_priv->sb_lock); |
| 302 | } |
| 303 | |
Jani Nikula | 5b48ca0 | 2015-01-16 14:27:21 +0200 | [diff] [blame] | 304 | static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 305 | { |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 306 | struct drm_device *dev = intel_dsi->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 307 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 308 | u8 gpio_source, gpio_index; |
| 309 | bool value; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 310 | |
Jani Nikula | 96afef1 | 2016-02-04 18:52:47 +0200 | [diff] [blame] | 311 | if (dev_priv->vbt.dsi.seq_version >= 3) |
| 312 | data++; |
| 313 | |
Jani Nikula | e37788f | 2016-03-18 13:11:09 +0200 | [diff] [blame] | 314 | gpio_index = *data++; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 315 | |
Jani Nikula | 1d96a4a | 2016-03-18 13:11:10 +0200 | [diff] [blame] | 316 | /* gpio source in sequence v2 only */ |
| 317 | if (dev_priv->vbt.dsi.seq_version == 2) |
| 318 | gpio_source = (*data >> 1) & 3; |
| 319 | else |
| 320 | gpio_source = 0; |
| 321 | |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 322 | /* pull up/down */ |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 323 | value = *data++ & 1; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 324 | |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 325 | if (IS_VALLEYVIEW(dev_priv)) |
| 326 | vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value); |
Jani Nikula | a0a6d4f | 2016-04-26 13:27:40 +0300 | [diff] [blame] | 327 | else if (IS_CHERRYVIEW(dev_priv)) |
| 328 | chv_exec_gpio(dev_priv, gpio_source, gpio_index, value); |
Jani Nikula | 515d07d | 2016-04-05 22:30:50 +0300 | [diff] [blame] | 329 | else |
Jani Nikula | 96afef1 | 2016-02-04 18:52:47 +0200 | [diff] [blame] | 330 | DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); |
Jani Nikula | 96afef1 | 2016-02-04 18:52:47 +0200 | [diff] [blame] | 331 | |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 332 | return data; |
| 333 | } |
| 334 | |
Jani Nikula | 29bbdcb | 2016-01-11 15:29:08 +0200 | [diff] [blame] | 335 | static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data) |
| 336 | { |
| 337 | return data + *(data + 6) + 7; |
| 338 | } |
| 339 | |
Jani Nikula | 5b48ca0 | 2015-01-16 14:27:21 +0200 | [diff] [blame] | 340 | typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, |
| 341 | const u8 *data); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 342 | static const fn_mipi_elem_exec exec_elem[] = { |
Jani Nikula | 28c7284 | 2015-12-21 15:10:59 +0200 | [diff] [blame] | 343 | [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, |
| 344 | [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, |
| 345 | [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, |
Jani Nikula | 29bbdcb | 2016-01-11 15:29:08 +0200 | [diff] [blame] | 346 | [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip, |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | /* |
| 350 | * MIPI Sequence from VBT #53 parsing logic |
| 351 | * We have already separated each seqence during bios parsing |
| 352 | * Following is generic execution function for any sequence |
| 353 | */ |
| 354 | |
| 355 | static const char * const seq_name[] = { |
Jani Nikula | 5cda0d2 | 2015-12-21 15:10:58 +0200 | [diff] [blame] | 356 | [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", |
| 357 | [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", |
| 358 | [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", |
| 359 | [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", |
| 360 | [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", |
Jani Nikula | bc95ce7 | 2016-01-05 17:08:17 +0200 | [diff] [blame] | 361 | [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", |
| 362 | [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", |
| 363 | [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", |
| 364 | [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", |
| 365 | [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", |
| 366 | [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 367 | }; |
| 368 | |
Jani Nikula | 5cda0d2 | 2015-12-21 15:10:58 +0200 | [diff] [blame] | 369 | static const char *sequence_name(enum mipi_seq seq_id) |
| 370 | { |
| 371 | if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) |
| 372 | return seq_name[seq_id]; |
| 373 | else |
| 374 | return "(unknown)"; |
| 375 | } |
| 376 | |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 377 | static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 378 | { |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 379 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); |
| 380 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; |
Jani Nikula | 2a33d93 | 2016-01-11 15:15:02 +0200 | [diff] [blame] | 381 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 382 | const u8 *data; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 383 | fn_mipi_elem_exec mipi_elem_exec; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 384 | |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 385 | if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 386 | return; |
| 387 | |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 388 | data = dev_priv->vbt.dsi.sequence[seq_id]; |
| 389 | if (!data) { |
| 390 | DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n", |
| 391 | seq_id, sequence_name(seq_id)); |
| 392 | return; |
| 393 | } |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 394 | |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 395 | WARN_ON(*data != seq_id); |
| 396 | |
| 397 | DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", |
| 398 | seq_id, sequence_name(seq_id)); |
| 399 | |
| 400 | /* Skip Sequence Byte. */ |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 401 | data++; |
| 402 | |
Jani Nikula | 2a33d93 | 2016-01-11 15:15:02 +0200 | [diff] [blame] | 403 | /* Skip Size of Sequence. */ |
| 404 | if (dev_priv->vbt.dsi.seq_version >= 3) |
| 405 | data += 4; |
| 406 | |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 407 | while (1) { |
Jani Nikula | 28c7284 | 2015-12-21 15:10:59 +0200 | [diff] [blame] | 408 | u8 operation_byte = *data++; |
Jani Nikula | 4079578 | 2016-01-05 17:06:48 +0200 | [diff] [blame] | 409 | u8 operation_size = 0; |
| 410 | |
| 411 | if (operation_byte == MIPI_SEQ_ELEM_END) |
| 412 | break; |
| 413 | |
| 414 | if (operation_byte < ARRAY_SIZE(exec_elem)) |
| 415 | mipi_elem_exec = exec_elem[operation_byte]; |
| 416 | else |
| 417 | mipi_elem_exec = NULL; |
| 418 | |
| 419 | /* Size of Operation. */ |
| 420 | if (dev_priv->vbt.dsi.seq_version >= 3) |
| 421 | operation_size = *data++; |
| 422 | |
| 423 | if (mipi_elem_exec) { |
| 424 | data = mipi_elem_exec(intel_dsi, data); |
| 425 | } else if (operation_size) { |
| 426 | /* We have size, skip. */ |
| 427 | DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", |
| 428 | operation_byte); |
| 429 | data += operation_size; |
| 430 | } else { |
| 431 | /* No size, can't skip without parsing. */ |
Jani Nikula | 28c7284 | 2015-12-21 15:10:59 +0200 | [diff] [blame] | 432 | DRM_ERROR("Unsupported MIPI operation byte %u\n", |
| 433 | operation_byte); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 434 | return; |
| 435 | } |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 436 | } |
| 437 | } |
| 438 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 439 | static int vbt_panel_prepare(struct drm_panel *panel) |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 440 | { |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 441 | generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET); |
| 442 | generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 443 | |
| 444 | return 0; |
| 445 | } |
| 446 | |
| 447 | static int vbt_panel_unprepare(struct drm_panel *panel) |
| 448 | { |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 449 | generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 450 | |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | static int vbt_panel_enable(struct drm_panel *panel) |
| 455 | { |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 456 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | static int vbt_panel_disable(struct drm_panel *panel) |
| 462 | { |
Jani Nikula | c67fed8 | 2015-12-21 15:11:06 +0200 | [diff] [blame] | 463 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 464 | |
| 465 | return 0; |
| 466 | } |
| 467 | |
| 468 | static int vbt_panel_get_modes(struct drm_panel *panel) |
| 469 | { |
| 470 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); |
| 471 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; |
| 472 | struct drm_device *dev = intel_dsi->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 473 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 474 | struct drm_display_mode *mode; |
| 475 | |
| 476 | if (!panel->connector) |
| 477 | return 0; |
| 478 | |
| 479 | mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
| 480 | if (!mode) |
| 481 | return 0; |
| 482 | |
| 483 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 484 | |
| 485 | drm_mode_probed_add(panel->connector, mode); |
| 486 | |
| 487 | return 1; |
| 488 | } |
| 489 | |
| 490 | static const struct drm_panel_funcs vbt_panel_funcs = { |
| 491 | .disable = vbt_panel_disable, |
| 492 | .unprepare = vbt_panel_unprepare, |
| 493 | .prepare = vbt_panel_prepare, |
| 494 | .enable = vbt_panel_enable, |
| 495 | .get_modes = vbt_panel_get_modes, |
| 496 | }; |
| 497 | |
| 498 | struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) |
| 499 | { |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 500 | struct drm_device *dev = intel_dsi->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 501 | struct drm_i915_private *dev_priv = to_i915(dev); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 502 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; |
| 503 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; |
| 504 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 505 | struct vbt_panel *vbt_panel; |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 506 | u32 bpp; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 507 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; |
| 508 | u32 ui_num, ui_den; |
| 509 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; |
| 510 | u32 ths_prepare_ns, tclk_trail_ns; |
| 511 | u32 tclk_prepare_clkzero, ths_prepare_hszero; |
| 512 | u32 lp_to_hs_switch, hs_to_lp_switch; |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 513 | u32 pclk, computed_ddr; |
| 514 | u16 burst_mode_ratio; |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 515 | enum port port; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 516 | |
| 517 | DRM_DEBUG_KMS("\n"); |
| 518 | |
| 519 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; |
| 520 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; |
| 521 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; |
Ramalingam C | 43367ec | 2016-04-07 14:36:06 +0530 | [diff] [blame] | 522 | intel_dsi->pixel_format = |
| 523 | pixel_format_from_register_bits( |
| 524 | mipi_config->videomode_color_format << 7); |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 525 | bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
| 526 | |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 527 | intel_dsi->dual_link = mipi_config->dual_link; |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 528 | intel_dsi->pixel_overlap = mipi_config->pixel_overlap; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 529 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
| 530 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; |
| 531 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; |
| 532 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; |
| 533 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; |
| 534 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; |
| 535 | intel_dsi->init_count = mipi_config->master_init_timer; |
| 536 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; |
Shobhit Kumar | b5fbcd98 | 2014-05-27 19:23:46 +0530 | [diff] [blame] | 537 | intel_dsi->video_frmt_cfg_bits = |
| 538 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 539 | |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 540 | pclk = mode->clock; |
| 541 | |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 542 | /* In dual link mode each port needs half of pixel clock */ |
| 543 | if (intel_dsi->dual_link) { |
| 544 | pclk = pclk / 2; |
| 545 | |
| 546 | /* we can enable pixel_overlap if needed by panel. In this |
| 547 | * case we need to increase the pixelclock for extra pixels |
| 548 | */ |
| 549 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
| 550 | pclk += DIV_ROUND_UP(mode->vtotal * |
| 551 | intel_dsi->pixel_overlap * |
| 552 | 60, 1000); |
| 553 | } |
| 554 | } |
| 555 | |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 556 | /* Burst Mode Ratio |
| 557 | * Target ddr frequency from VBT / non burst ddr freq |
| 558 | * multiply by 100 to preserve remainder |
| 559 | */ |
| 560 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
| 561 | if (mipi_config->target_burst_mode_freq) { |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 562 | computed_ddr = (pclk * bpp) / intel_dsi->lane_count; |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 563 | |
| 564 | if (mipi_config->target_burst_mode_freq < |
| 565 | computed_ddr) { |
| 566 | DRM_ERROR("Burst mode freq is less than computed\n"); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 567 | return NULL; |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | burst_mode_ratio = DIV_ROUND_UP( |
| 571 | mipi_config->target_burst_mode_freq * 100, |
| 572 | computed_ddr); |
| 573 | |
| 574 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); |
| 575 | } else { |
| 576 | DRM_ERROR("Burst mode target is not set\n"); |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 577 | return NULL; |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 578 | } |
| 579 | } else |
| 580 | burst_mode_ratio = 100; |
| 581 | |
| 582 | intel_dsi->burst_mode_ratio = burst_mode_ratio; |
| 583 | intel_dsi->pclk = pclk; |
| 584 | |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 585 | bitrate = (pclk * bpp) / intel_dsi->lane_count; |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 586 | |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 587 | switch (intel_dsi->escape_clk_div) { |
| 588 | case 0: |
| 589 | tlpx_ns = 50; |
| 590 | break; |
| 591 | case 1: |
| 592 | tlpx_ns = 100; |
| 593 | break; |
| 594 | |
| 595 | case 2: |
| 596 | tlpx_ns = 200; |
| 597 | break; |
| 598 | default: |
| 599 | tlpx_ns = 50; |
| 600 | break; |
| 601 | } |
| 602 | |
| 603 | switch (intel_dsi->lane_count) { |
| 604 | case 1: |
| 605 | case 2: |
| 606 | extra_byte_count = 2; |
| 607 | break; |
| 608 | case 3: |
| 609 | extra_byte_count = 4; |
| 610 | break; |
| 611 | case 4: |
| 612 | default: |
| 613 | extra_byte_count = 3; |
| 614 | break; |
| 615 | } |
| 616 | |
| 617 | /* |
| 618 | * ui(s) = 1/f [f in hz] |
| 619 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) |
| 620 | */ |
| 621 | |
| 622 | /* in Kbps */ |
| 623 | ui_num = NS_KHZ_RATIO; |
| 624 | ui_den = bitrate; |
| 625 | |
| 626 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; |
| 627 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; |
| 628 | |
| 629 | /* |
| 630 | * B060 |
| 631 | * LP byte clock = TLPX/ (8UI) |
| 632 | */ |
| 633 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); |
| 634 | |
| 635 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) |
| 636 | * |
| 637 | * Since txddrclkhs_i is 2xUI, all the count values programmed in |
| 638 | * DPHY param register are divided by 2 |
| 639 | * |
| 640 | * prepare count |
| 641 | */ |
Shobhit Kumar | b5fbcd98 | 2014-05-27 19:23:46 +0530 | [diff] [blame] | 642 | ths_prepare_ns = max(mipi_config->ths_prepare, |
| 643 | mipi_config->tclk_prepare); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 644 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
| 645 | |
| 646 | /* exit zero count */ |
| 647 | exit_zero_cnt = DIV_ROUND_UP( |
| 648 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, |
| 649 | ui_num * 2 |
| 650 | ); |
| 651 | |
| 652 | /* |
Chris Wilson | ebe69dd | 2016-07-02 15:36:03 +0100 | [diff] [blame] | 653 | * Exit zero is unified val ths_zero and ths_exit |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 654 | * minimum value for ths_exit = 110ns |
| 655 | * min (exit_zero_cnt * 2) = 110/UI |
| 656 | * exit_zero_cnt = 55/UI |
| 657 | */ |
Chris Wilson | ebe69dd | 2016-07-02 15:36:03 +0100 | [diff] [blame] | 658 | if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) |
| 659 | exit_zero_cnt += 1; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 660 | |
| 661 | /* clk zero count */ |
| 662 | clk_zero_cnt = DIV_ROUND_UP( |
| 663 | (tclk_prepare_clkzero - ths_prepare_ns) |
| 664 | * ui_den, 2 * ui_num); |
| 665 | |
| 666 | /* trail count */ |
| 667 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); |
| 668 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); |
| 669 | |
| 670 | if (prepare_cnt > PREPARE_CNT_MAX || |
| 671 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || |
| 672 | clk_zero_cnt > CLK_ZERO_CNT_MAX || |
| 673 | trail_cnt > TRAIL_CNT_MAX) |
| 674 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); |
| 675 | |
| 676 | if (prepare_cnt > PREPARE_CNT_MAX) |
| 677 | prepare_cnt = PREPARE_CNT_MAX; |
| 678 | |
| 679 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) |
| 680 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; |
| 681 | |
| 682 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) |
| 683 | clk_zero_cnt = CLK_ZERO_CNT_MAX; |
| 684 | |
| 685 | if (trail_cnt > TRAIL_CNT_MAX) |
| 686 | trail_cnt = TRAIL_CNT_MAX; |
| 687 | |
| 688 | /* B080 */ |
| 689 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | |
| 690 | clk_zero_cnt << 8 | prepare_cnt; |
| 691 | |
| 692 | /* |
| 693 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 |
| 694 | * + 10UI + Extra Byte Count |
| 695 | * |
| 696 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count |
| 697 | * Extra Byte Count is calculated according to number of lanes. |
| 698 | * High Low Switch Count is the Max of LP to HS and |
| 699 | * HS to LP switch count |
| 700 | * |
| 701 | */ |
| 702 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); |
| 703 | |
| 704 | /* B044 */ |
| 705 | /* FIXME: |
| 706 | * The comment above does not match with the code */ |
| 707 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + |
| 708 | exit_zero_cnt * 2 + 10, 8); |
| 709 | |
| 710 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); |
| 711 | |
| 712 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); |
| 713 | intel_dsi->hs_to_lp_count += extra_byte_count; |
| 714 | |
| 715 | /* B088 */ |
| 716 | /* LP -> HS for clock lanes |
| 717 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + |
| 718 | * extra byte count |
| 719 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * |
| 720 | * 2(in UI) + extra byte count |
| 721 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / |
| 722 | * 8 + extra byte count |
| 723 | */ |
| 724 | intel_dsi->clk_lp_to_hs_count = |
| 725 | DIV_ROUND_UP( |
| 726 | 4 * tlpx_ui + prepare_cnt * 2 + |
| 727 | clk_zero_cnt * 2, |
| 728 | 8); |
| 729 | |
| 730 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; |
| 731 | |
| 732 | /* HS->LP for Clock Lanes |
| 733 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + |
| 734 | * Extra byte count |
| 735 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count |
| 736 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + |
| 737 | * Extra byte count |
| 738 | */ |
| 739 | intel_dsi->clk_hs_to_lp_count = |
| 740 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, |
| 741 | 8); |
| 742 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; |
| 743 | |
| 744 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); |
| 745 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? |
| 746 | "disabled" : "enabled"); |
| 747 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 748 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
| 749 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); |
| 750 | else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) |
| 751 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); |
| 752 | else |
| 753 | DRM_DEBUG_KMS("Dual link: NONE\n"); |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 754 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
| 755 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); |
| 756 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); |
| 757 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); |
| 758 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); |
| 759 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); |
| 760 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); |
| 761 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); |
| 762 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); |
| 763 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); |
| 764 | DRM_DEBUG_KMS("BTA %s\n", |
| 765 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? |
| 766 | "disabled" : "enabled"); |
| 767 | |
| 768 | /* delays in VBT are in unit of 100us, so need to convert |
| 769 | * here in ms |
| 770 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ |
| 771 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; |
| 772 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; |
| 773 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; |
| 774 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; |
| 775 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; |
| 776 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 777 | /* This is cheating a bit with the cleanup. */ |
| 778 | vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL); |
Insu Yun | 62ab420 | 2015-12-30 10:59:29 -0500 | [diff] [blame] | 779 | if (!vbt_panel) |
| 780 | return NULL; |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 781 | |
| 782 | vbt_panel->intel_dsi = intel_dsi; |
| 783 | drm_panel_init(&vbt_panel->panel); |
| 784 | vbt_panel->panel.funcs = &vbt_panel_funcs; |
| 785 | drm_panel_add(&vbt_panel->panel); |
| 786 | |
Jani Nikula | 759d10c | 2015-01-16 14:27:24 +0200 | [diff] [blame] | 787 | /* a regular driver would get the device in probe */ |
| 788 | for_each_dsi_port(port, intel_dsi->ports) { |
| 789 | mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); |
| 790 | } |
| 791 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 792 | return &vbt_panel->panel; |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 793 | } |