David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "OLEDB: %s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/regmap.h> |
| 22 | #include <linux/spmi.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/regulator/driver.h> |
| 25 | #include <linux/regulator/machine.h> |
| 26 | #include <linux/regulator/of_regulator.h> |
| 27 | |
| 28 | #define QPNP_OLEDB_REGULATOR_DRIVER_NAME "qcom,qpnp-oledb-regulator" |
| 29 | #define OLEDB_VOUT_STEP_MV 100 |
| 30 | #define OLEDB_VOUT_MIN_MV 5000 |
| 31 | #define OLEDB_VOUT_MAX_MV 8100 |
| 32 | #define OLEDB_VOUT_HW_DEFAULT 6400 |
| 33 | |
| 34 | #define OLEDB_MODULE_RDY 0x45 |
| 35 | #define OLEDB_MODULE_RDY_BIT BIT(7) |
| 36 | |
| 37 | #define OLEDB_MODULE_ENABLE 0x46 |
| 38 | #define OLEDB_MODULE_ENABLE_BIT BIT(7) |
| 39 | |
| 40 | #define OLEDB_EXT_PIN_CTL 0x47 |
| 41 | #define OLEDB_EXT_PIN_CTL_BIT BIT(7) |
| 42 | |
| 43 | #define OLEDB_SWIRE_CONTROL 0x48 |
| 44 | #define OLEDB_EN_SWIRE_VOUT_UPD_BIT BIT(6) |
| 45 | #define OLEDB_EN_SWIRE_PD_UPD_BIT BIT(7) |
| 46 | |
| 47 | #define OLEDB_VOUT_PGM 0x49 |
| 48 | #define OLEDB_VOUT_PGM_MASK GENMASK(4, 0) |
| 49 | |
| 50 | #define OLEDB_VOUT_DEFAULT 0x4A |
| 51 | #define OLEDB_VOUT_DEFAULT_MASK GENMASK(4, 0) |
| 52 | |
| 53 | #define OLEDB_PD_CTL 0x4B |
| 54 | |
| 55 | #define OLEDB_ILIM_NFET 0x4E |
| 56 | #define OLEDB_ILIMIT_NFET_MASK GENMASK(2, 0) |
| 57 | |
| 58 | #define OLEDB_BIAS_GEN_WARMUP_DELAY 0x52 |
| 59 | #define OLEDB_BIAS_GEN_WARMUP_DELAY_MASK GENMASK(1, 0) |
| 60 | |
| 61 | #define OLEDB_SHORT_PROTECT 0x59 |
| 62 | #define OLEDB_ENABLE_SC_DETECTION_BIT BIT(7) |
| 63 | #define OLEDB_DBNC_SHORT_DETECTION_MASK GENMASK(1, 0) |
| 64 | |
| 65 | #define OLEDB_FAST_PRECHARGE 0x5A |
| 66 | #define OLEDB_FAST_PRECHG_PPULSE_EN_BIT BIT(7) |
| 67 | #define OLEDB_DBNC_PRECHARGE_MASK GENMASK(5, 4) |
| 68 | #define OLEDB_DBNC_PRECHARGE_SHIFT 4 |
| 69 | #define OLEDB_PRECHARGE_PULSE_PERIOD_MASK GENMASK(3, 2) |
| 70 | #define OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT 2 |
| 71 | #define OLEDB_PRECHARGE_PULSE_TON_MASK GENMASK(1, 0) |
| 72 | |
| 73 | #define OLEDB_EN_PSM 0x5B |
| 74 | #define OLEDB_PSM_ENABLE_BIT BIT(7) |
| 75 | |
| 76 | #define OLEDB_PSM_CTL 0x5C |
| 77 | #define OLEDB_PSM_HYSTERYSIS_CTL_BIT BIT(3) |
| 78 | #define OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT 3 |
| 79 | #define OLEDB_VREF_PSM_MASK GENMASK(2, 0) |
| 80 | |
| 81 | #define OLEDB_PFM_CTL 0x5D |
| 82 | #define OLEDB_PFM_ENABLE_BIT BIT(7) |
| 83 | #define OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK BIT(4) |
| 84 | #define OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT 4 |
| 85 | #define OLEDB_PFM_CURR_LIMIT_MASK GENMASK(3, 2) |
| 86 | #define OLEDB_PFM_CURR_LIMIT_SHIFT 2 |
| 87 | #define OLEDB_PFM_OFF_TIME_NS_MASK GENMASK(1, 0) |
| 88 | |
| 89 | #define OLEDB_NLIMIT 0x64 |
| 90 | #define OLEDB_ENABLE_NLIMIT_BIT BIT(7) |
| 91 | #define OLEDB_ENABLE_NLIMIT_BIT_SHIFT 7 |
| 92 | #define OLEDB_NLIMIT_PGM_MASK GENMASK(1, 0) |
| 93 | |
| 94 | #define OLEDB_PSM_HYS_CTRL_MIN 13 |
| 95 | #define OLEDB_PSM_HYS_CTRL_MAX 26 |
| 96 | |
| 97 | #define OLEDB_PFM_HYS_CTRL_MIN 13 |
| 98 | #define OLEDB_PFM_HYS_CTRL_MAX 26 |
| 99 | |
| 100 | #define OLEDB_PFM_OFF_TIME_MIN 110 |
| 101 | #define OLEDB_PFM_OFF_TIME_MAX 480 |
| 102 | |
| 103 | #define OLEDB_PRECHG_TIME_MIN 1 |
| 104 | #define OLEDB_PRECHG_TIME_MAX 8 |
| 105 | |
| 106 | #define OLEDB_PRECHG_PULSE_PERIOD_MIN 3 |
| 107 | #define OLEDB_PRECHG_PULSE_PERIOD_MAX 12 |
| 108 | |
| 109 | #define OLEDB_MIN_SC_DBNC_TIME_FSW 2 |
| 110 | #define OLEDB_MAX_SC_DBNC_TIME_FSW 16 |
| 111 | |
| 112 | #define OLEDB_PRECHG_PULSE_ON_TIME_MIN 1200 |
| 113 | #define OLEDB_PRECHG_PULSE_ON_TIME_MAX 3000 |
| 114 | |
| 115 | #define PSM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1) |
| 116 | #define PFM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1) |
| 117 | #define PFM_OFF_TIME_NS_TO_VAL(val_ns) ((val_ns/110) - 1) |
| 118 | #define PRECHG_DEBOUNCE_TIME_MS_TO_VAL(val_ms) ((val_ms/2) - \ |
| 119 | (val_ms/8)) |
| 120 | #define PRECHG_PULSE_PERIOD_US_TO_VAL(val_us) ((val_us/3) - 1) |
| 121 | #define PRECHG_PULSE_ON_TIME_NS_TO_VAL(val_ns) (val_ns/600 - 2) |
| 122 | #define SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL(val) ((val/4) - (val/16)) |
| 123 | |
| 124 | struct qpnp_oledb_psm_ctl { |
| 125 | int psm_enable; |
| 126 | int psm_hys_ctl; |
| 127 | int psm_vref; |
| 128 | }; |
| 129 | |
| 130 | struct qpnp_oledb_pfm_ctl { |
| 131 | int pfm_enable; |
| 132 | int pfm_hys_ctl; |
| 133 | int pfm_curr_limit; |
| 134 | int pfm_off_time; |
| 135 | }; |
| 136 | |
| 137 | struct qpnp_oledb_fast_precharge_ctl { |
| 138 | int fast_prechg_ppulse_en; |
| 139 | int prechg_debounce_time; |
| 140 | int prechg_pulse_period; |
| 141 | int prechg_pulse_on_time; |
| 142 | }; |
| 143 | |
| 144 | struct qpnp_oledb { |
| 145 | struct platform_device *pdev; |
| 146 | struct device *dev; |
| 147 | struct regmap *regmap; |
| 148 | struct regulator_desc rdesc; |
| 149 | struct regulator_dev *rdev; |
| 150 | struct qpnp_oledb_psm_ctl psm_ctl; |
| 151 | struct qpnp_oledb_pfm_ctl pfm_ctl; |
| 152 | struct qpnp_oledb_fast_precharge_ctl fast_prechg_ctl; |
| 153 | |
| 154 | u32 base; |
| 155 | u8 mod_enable; |
| 156 | u8 ext_pinctl_state; |
| 157 | int current_voltage; |
| 158 | int default_voltage; |
| 159 | int vout_mv; |
| 160 | int warmup_delay; |
| 161 | int peak_curr_limit; |
| 162 | int pd_ctl; |
| 163 | int negative_curr_limit; |
| 164 | int nlimit_enable; |
| 165 | int sc_en; |
| 166 | int sc_dbnc_time; |
| 167 | bool swire_control; |
| 168 | bool ext_pin_control; |
| 169 | bool dynamic_ext_pinctl_config; |
| 170 | bool pbs_control; |
| 171 | }; |
| 172 | |
| 173 | static const u16 oledb_warmup_dly_ns[] = {6700, 13300, 26700, 53400}; |
| 174 | static const u16 oledb_peak_curr_limit_ma[] = {115, 265, 415, 570, |
| 175 | 720, 870, 1020, 1170}; |
| 176 | static const u16 oledb_psm_vref_mv[] = {440, 510, 580, 650, 715, |
| 177 | 780, 850, 920}; |
| 178 | static const u16 oledb_pfm_curr_limit_ma[] = {130, 200, 270, 340}; |
| 179 | static const u16 oledb_nlimit_ma[] = {170, 300, 420, 550}; |
| 180 | |
| 181 | static int qpnp_oledb_read(struct qpnp_oledb *oledb, u32 address, |
| 182 | u8 *val, int count) |
| 183 | { |
| 184 | int rc = 0; |
| 185 | struct platform_device *pdev = oledb->pdev; |
| 186 | |
| 187 | rc = regmap_bulk_read(oledb->regmap, address, val, count); |
| 188 | if (rc) |
| 189 | pr_err("Failed to read address=0x%02x sid=0x%02x rc=%d\n", |
| 190 | address, to_spmi_device(pdev->dev.parent)->usid, rc); |
| 191 | |
| 192 | return rc; |
| 193 | } |
| 194 | |
| 195 | static int qpnp_oledb_masked_write(struct qpnp_oledb *oledb, |
| 196 | u32 address, u8 mask, u8 val) |
| 197 | { |
| 198 | int rc; |
| 199 | |
| 200 | rc = regmap_update_bits(oledb->regmap, address, mask, val); |
| 201 | if (rc < 0) |
| 202 | pr_err("Failed to write address 0x%04X, rc = %d\n", |
| 203 | address, rc); |
| 204 | else |
| 205 | pr_debug("Wrote 0x%02X to addr 0x%04X\n", |
| 206 | val, address); |
| 207 | |
| 208 | return rc; |
| 209 | } |
| 210 | |
| 211 | static int qpnp_oledb_write(struct qpnp_oledb *oledb, u16 address, u8 *val, |
| 212 | int count) |
| 213 | { |
| 214 | int rc = 0; |
| 215 | struct platform_device *pdev = oledb->pdev; |
| 216 | |
| 217 | rc = regmap_bulk_write(oledb->regmap, address, val, count); |
| 218 | if (rc) |
| 219 | pr_err("Failed to write address=0x%02x sid=0x%02x rc=%d\n", |
| 220 | address, to_spmi_device(pdev->dev.parent)->usid, rc); |
| 221 | else |
| 222 | pr_debug("Wrote 0x%02X to addr 0x%04X\n", |
| 223 | *val, address); |
| 224 | |
| 225 | return 0; |
| 226 | } |
| 227 | |
| 228 | static int qpnp_oledb_regulator_enable(struct regulator_dev *rdev) |
| 229 | { |
| 230 | int rc = 0; |
| 231 | u8 val = 0; |
| 232 | |
| 233 | struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); |
| 234 | |
| 235 | if (oledb->ext_pin_control) { |
| 236 | rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL, |
| 237 | &val, 1); |
| 238 | if (rc < 0) { |
| 239 | pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc); |
| 240 | return rc; |
| 241 | } |
| 242 | |
| 243 | /* |
| 244 | * Enable ext-pin-ctl after display-supply is turned on. |
| 245 | * This is to avoid glitches on the external pin. |
| 246 | */ |
| 247 | if (!(val & OLEDB_EXT_PIN_CTL_BIT) && |
| 248 | oledb->dynamic_ext_pinctl_config) { |
| 249 | val = OLEDB_EXT_PIN_CTL_BIT; |
| 250 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 251 | OLEDB_EXT_PIN_CTL, &val, 1); |
| 252 | if (rc < 0) { |
| 253 | pr_err("Failed to write EXT_PIN_CTL rc=%d\n", |
| 254 | rc); |
| 255 | return rc; |
| 256 | } |
| 257 | } |
| 258 | pr_debug("ext-pin-ctrl mode enabled\n"); |
| 259 | } else { |
| 260 | val = OLEDB_MODULE_ENABLE_BIT; |
| 261 | rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_MODULE_ENABLE, |
| 262 | &val, 1); |
| 263 | if (rc < 0) { |
| 264 | pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc); |
| 265 | return rc; |
| 266 | } |
| 267 | |
| 268 | ndelay(oledb->warmup_delay); |
| 269 | pr_debug("register-control mode, module enabled\n"); |
| 270 | } |
| 271 | |
| 272 | oledb->mod_enable = true; |
| 273 | if (oledb->pbs_control) { |
| 274 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 275 | OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT | |
| 276 | OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0); |
| 277 | if (rc < 0) |
| 278 | pr_err("Failed to write SWIRE_CTL for pbs mode rc=%d\n", |
| 279 | rc); |
| 280 | } |
| 281 | |
| 282 | return rc; |
| 283 | } |
| 284 | |
| 285 | static int qpnp_oledb_regulator_disable(struct regulator_dev *rdev) |
| 286 | { |
| 287 | int rc = 0; |
| 288 | |
| 289 | struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); |
| 290 | |
| 291 | /* |
| 292 | * Disable ext-pin-ctl after display-supply is turned off. This is to |
| 293 | * avoid glitches on the external pin. |
| 294 | */ |
| 295 | if (oledb->ext_pin_control) { |
| 296 | if (oledb->dynamic_ext_pinctl_config) { |
| 297 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 298 | OLEDB_EXT_PIN_CTL, OLEDB_EXT_PIN_CTL_BIT, 0); |
| 299 | if (rc < 0) { |
| 300 | pr_err("Failed to write EXT_PIN_CTL rc=%d\n", |
| 301 | rc); |
| 302 | return rc; |
| 303 | } |
| 304 | } |
| 305 | pr_debug("ext-pin-ctrl mode disabled\n"); |
| 306 | } else { |
| 307 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 308 | OLEDB_MODULE_ENABLE, |
| 309 | OLEDB_MODULE_ENABLE_BIT, 0); |
| 310 | if (rc < 0) { |
| 311 | pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc); |
| 312 | return rc; |
| 313 | } |
| 314 | pr_debug("Register-control mode, module disabled\n"); |
| 315 | } |
| 316 | |
| 317 | oledb->mod_enable = false; |
| 318 | |
| 319 | return rc; |
| 320 | } |
| 321 | |
| 322 | static int qpnp_oledb_regulator_is_enabled(struct regulator_dev *rdev) |
| 323 | { |
| 324 | struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); |
| 325 | |
| 326 | return oledb->mod_enable; |
| 327 | } |
| 328 | |
| 329 | static int qpnp_oledb_regulator_set_voltage(struct regulator_dev *rdev, |
| 330 | int min_uV, int max_uV, unsigned int *selector) |
| 331 | { |
| 332 | u8 val; |
| 333 | int rc = 0; |
| 334 | |
| 335 | struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); |
| 336 | |
| 337 | if (oledb->swire_control) |
| 338 | return 0; |
| 339 | |
| 340 | val = DIV_ROUND_UP(min_uV - OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV); |
| 341 | |
| 342 | rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_VOUT_PGM, |
| 343 | &val, 1); |
| 344 | if (rc < 0) { |
| 345 | pr_err("Failed to write VOUT_PGM rc=%d\n", rc); |
| 346 | return rc; |
| 347 | } |
| 348 | |
| 349 | oledb->current_voltage = min_uV; |
| 350 | pr_debug("register-control mode, current voltage %d\n", |
| 351 | oledb->current_voltage); |
| 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
| 356 | static int qpnp_oledb_regulator_get_voltage(struct regulator_dev *rdev) |
| 357 | { |
| 358 | struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); |
| 359 | |
| 360 | if (oledb->swire_control) |
| 361 | return 0; |
| 362 | |
| 363 | return oledb->current_voltage; |
| 364 | } |
| 365 | |
| 366 | static struct regulator_ops qpnp_oledb_ops = { |
| 367 | .enable = qpnp_oledb_regulator_enable, |
| 368 | .disable = qpnp_oledb_regulator_disable, |
| 369 | .is_enabled = qpnp_oledb_regulator_is_enabled, |
| 370 | .set_voltage = qpnp_oledb_regulator_set_voltage, |
| 371 | .get_voltage = qpnp_oledb_regulator_get_voltage, |
| 372 | }; |
| 373 | |
| 374 | static int qpnp_oledb_register_regulator(struct qpnp_oledb *oledb) |
| 375 | { |
| 376 | int rc = 0; |
| 377 | struct platform_device *pdev = oledb->pdev; |
| 378 | struct regulator_init_data *init_data; |
| 379 | struct regulator_desc *rdesc = &oledb->rdesc; |
| 380 | struct regulator_config cfg = {}; |
| 381 | |
| 382 | init_data = of_get_regulator_init_data(&pdev->dev, |
| 383 | pdev->dev.of_node, rdesc); |
| 384 | if (!init_data) { |
| 385 | pr_err("Unable to get OLEDB regulator init data\n"); |
| 386 | return -ENOMEM; |
| 387 | } |
| 388 | |
| 389 | if (init_data->constraints.name) { |
| 390 | rdesc->owner = THIS_MODULE; |
| 391 | rdesc->type = REGULATOR_VOLTAGE; |
| 392 | rdesc->ops = &qpnp_oledb_ops; |
| 393 | rdesc->name = init_data->constraints.name; |
| 394 | |
| 395 | cfg.dev = &pdev->dev; |
| 396 | cfg.init_data = init_data; |
| 397 | cfg.driver_data = oledb; |
| 398 | cfg.of_node = pdev->dev.of_node; |
| 399 | |
| 400 | if (of_get_property(pdev->dev.of_node, "parent-supply", |
| 401 | NULL)) |
| 402 | init_data->supply_regulator = "parent"; |
| 403 | |
| 404 | init_data->constraints.valid_ops_mask |
| 405 | |= REGULATOR_CHANGE_VOLTAGE | |
| 406 | REGULATOR_CHANGE_STATUS; |
| 407 | |
| 408 | oledb->rdev = devm_regulator_register(oledb->dev, rdesc, &cfg); |
| 409 | if (IS_ERR(oledb->rdev)) { |
| 410 | rc = PTR_ERR(oledb->rdev); |
| 411 | oledb->rdev = NULL; |
| 412 | pr_err("Unable to register OLEDB regulator, rc = %d\n", |
| 413 | rc); |
| 414 | return rc; |
| 415 | } |
| 416 | } else { |
| 417 | pr_err("OLEDB regulator name missing\n"); |
| 418 | return -EINVAL; |
| 419 | } |
| 420 | |
| 421 | return 0; |
| 422 | } |
| 423 | |
| 424 | static int qpnp_oledb_get_curr_voltage(struct qpnp_oledb *oledb, |
| 425 | u16 *current_voltage) |
| 426 | { |
| 427 | int rc = 0; |
| 428 | u8 val; |
| 429 | |
| 430 | if (!(oledb->mod_enable || oledb->ext_pinctl_state)) { |
| 431 | rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_VOUT_DEFAULT, |
| 432 | &val, 1); |
| 433 | if (rc < 0) { |
| 434 | pr_err("Failed to read VOUT_DEFAULT rc=%d\n", rc); |
| 435 | return rc; |
| 436 | } |
| 437 | } else { |
| 438 | rc = qpnp_oledb_read(oledb, oledb->base + |
| 439 | OLEDB_VOUT_PGM, &val, 1); |
| 440 | if (rc < 0) { |
| 441 | pr_err("Failed to read VOUT_PGM rc=%d\n", rc); |
| 442 | return rc; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | *current_voltage = (val * OLEDB_VOUT_STEP_MV) + OLEDB_VOUT_MIN_MV; |
| 447 | |
| 448 | return rc; |
| 449 | } |
| 450 | |
| 451 | static int qpnp_oledb_init_nlimit(struct qpnp_oledb *oledb) |
| 452 | { |
| 453 | int rc = 0, i = 0; |
| 454 | u32 val, mask = 0; |
| 455 | |
| 456 | if (oledb->nlimit_enable != -EINVAL) { |
| 457 | val = oledb->nlimit_enable << |
| 458 | OLEDB_ENABLE_NLIMIT_BIT_SHIFT; |
| 459 | mask = OLEDB_ENABLE_NLIMIT_BIT; |
| 460 | if (oledb->negative_curr_limit != -EINVAL) { |
| 461 | for (i = 0; i < ARRAY_SIZE(oledb_nlimit_ma); i++) { |
| 462 | if (oledb->negative_curr_limit == |
| 463 | oledb_nlimit_ma[i]) |
| 464 | break; |
| 465 | } |
| 466 | val |= i; |
| 467 | mask |= OLEDB_NLIMIT_PGM_MASK; |
| 468 | } |
| 469 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 470 | OLEDB_NLIMIT, mask, val); |
| 471 | if (rc < 0) |
| 472 | pr_err("Failed to write NLIMT rc=%d\n", rc); |
| 473 | } |
| 474 | |
| 475 | return rc; |
| 476 | } |
| 477 | |
| 478 | static int qpnp_oledb_init_psm(struct qpnp_oledb *oledb) |
| 479 | { |
| 480 | int rc = 0, i = 0; |
| 481 | u32 val = 0, mask = 0, temp = 0; |
| 482 | struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl; |
| 483 | |
| 484 | if (psm_ctl->psm_enable == -EINVAL) |
| 485 | return rc; |
| 486 | |
| 487 | if (psm_ctl->psm_enable) { |
| 488 | val = OLEDB_PSM_ENABLE_BIT; |
| 489 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 490 | OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, val); |
| 491 | if (rc < 0) { |
| 492 | pr_err("Failed to write PSM_EN rc=%d\n", rc); |
| 493 | return rc; |
| 494 | } |
| 495 | |
| 496 | val = 0; |
| 497 | if (psm_ctl->psm_vref != -EINVAL) { |
| 498 | for (i = 0; i < ARRAY_SIZE(oledb_psm_vref_mv); i++) { |
| 499 | if (psm_ctl->psm_vref == |
| 500 | oledb_psm_vref_mv[i]) |
| 501 | break; |
| 502 | } |
| 503 | val = i; |
| 504 | mask = OLEDB_VREF_PSM_MASK; |
| 505 | } |
| 506 | |
| 507 | if (psm_ctl->psm_hys_ctl != -EINVAL) { |
| 508 | temp = PSM_HYSTERYSIS_MV_TO_VAL(psm_ctl->psm_hys_ctl); |
| 509 | val |= (temp << OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT); |
| 510 | mask |= OLEDB_PSM_HYSTERYSIS_CTL_BIT; |
| 511 | } |
| 512 | if (val) { |
| 513 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 514 | OLEDB_PSM_CTL, mask, val); |
| 515 | if (rc < 0) |
| 516 | pr_err("Failed to write PSM_CTL rc=%d\n", rc); |
| 517 | } |
| 518 | } else { |
| 519 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 520 | OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, 0); |
| 521 | if (rc < 0) |
| 522 | pr_err("Failed to write PSM_CTL rc=%d\n", rc); |
| 523 | } |
| 524 | |
| 525 | return rc; |
| 526 | } |
| 527 | |
| 528 | static int qpnp_oledb_init_pfm(struct qpnp_oledb *oledb) |
| 529 | { |
| 530 | int rc = 0, i = 0; |
| 531 | u32 val = 0, temp = 0, mask = 0; |
| 532 | struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl; |
| 533 | |
| 534 | if (pfm_ctl->pfm_enable == -EINVAL) |
| 535 | return rc; |
| 536 | |
| 537 | if (pfm_ctl->pfm_enable) { |
| 538 | mask = val = OLEDB_PFM_ENABLE_BIT; |
| 539 | if (pfm_ctl->pfm_hys_ctl != -EINVAL) { |
| 540 | temp = PFM_HYSTERYSIS_MV_TO_VAL(pfm_ctl->pfm_hys_ctl); |
| 541 | val |= temp << |
| 542 | OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT; |
| 543 | mask |= OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK; |
| 544 | } |
| 545 | |
| 546 | if (pfm_ctl->pfm_curr_limit != -EINVAL) { |
| 547 | for (i = 0; i < ARRAY_SIZE(oledb_pfm_curr_limit_ma); |
| 548 | i++) { |
| 549 | if (pfm_ctl->pfm_curr_limit == |
| 550 | oledb_pfm_curr_limit_ma[i]) |
| 551 | break; |
| 552 | } |
| 553 | val |= (i << OLEDB_PFM_CURR_LIMIT_SHIFT); |
| 554 | mask |= OLEDB_PFM_CURR_LIMIT_MASK; |
| 555 | } |
| 556 | |
| 557 | if (pfm_ctl->pfm_off_time != -EINVAL) { |
| 558 | val |= PFM_OFF_TIME_NS_TO_VAL(pfm_ctl->pfm_off_time); |
| 559 | mask |= OLEDB_PFM_OFF_TIME_NS_MASK; |
| 560 | } |
| 561 | |
| 562 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 563 | OLEDB_PFM_CTL, mask, val); |
| 564 | if (rc < 0) |
| 565 | pr_err("Failed to write PFM_CTL rc=%d\n", rc); |
| 566 | } else { |
| 567 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 568 | OLEDB_PFM_CTL, OLEDB_PFM_ENABLE_BIT, 0); |
| 569 | if (rc < 0) |
| 570 | pr_err("Failed to write PFM_CTL rc=%d\n", rc); |
| 571 | } |
| 572 | |
| 573 | return rc; |
| 574 | } |
| 575 | |
| 576 | static int qpnp_oledb_init_fast_precharge(struct qpnp_oledb *oledb) |
| 577 | { |
| 578 | int rc = 0; |
| 579 | u32 val = 0, temp = 0, mask = 0; |
| 580 | struct qpnp_oledb_fast_precharge_ctl *prechg_ctl = |
| 581 | &oledb->fast_prechg_ctl; |
| 582 | |
| 583 | if (prechg_ctl->fast_prechg_ppulse_en == -EINVAL) |
| 584 | return rc; |
| 585 | |
| 586 | if (prechg_ctl->fast_prechg_ppulse_en) { |
| 587 | mask = val = OLEDB_FAST_PRECHG_PPULSE_EN_BIT; |
| 588 | if (prechg_ctl->prechg_debounce_time != -EINVAL) { |
| 589 | temp = PRECHG_DEBOUNCE_TIME_MS_TO_VAL( |
| 590 | prechg_ctl->prechg_debounce_time); |
| 591 | val |= temp << OLEDB_DBNC_PRECHARGE_SHIFT; |
| 592 | mask |= OLEDB_DBNC_PRECHARGE_MASK; |
| 593 | } |
| 594 | |
| 595 | if (prechg_ctl->prechg_pulse_period != -EINVAL) { |
| 596 | temp = PRECHG_PULSE_PERIOD_US_TO_VAL( |
| 597 | prechg_ctl->prechg_pulse_period); |
| 598 | val |= temp << OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT; |
| 599 | mask |= OLEDB_PRECHARGE_PULSE_PERIOD_MASK; |
| 600 | } |
| 601 | |
| 602 | if (prechg_ctl->prechg_pulse_on_time != -EINVAL) { |
| 603 | val |= PRECHG_PULSE_ON_TIME_NS_TO_VAL( |
| 604 | prechg_ctl->prechg_pulse_on_time); |
| 605 | mask |= OLEDB_PRECHARGE_PULSE_TON_MASK; |
| 606 | } |
| 607 | |
| 608 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 609 | OLEDB_FAST_PRECHARGE, mask, val); |
| 610 | if (rc < 0) |
| 611 | pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc); |
| 612 | } else { |
| 613 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 614 | OLEDB_FAST_PRECHARGE, |
| 615 | OLEDB_FAST_PRECHG_PPULSE_EN_BIT, 0); |
| 616 | if (rc < 0) |
| 617 | pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc); |
| 618 | } |
| 619 | |
| 620 | return rc; |
| 621 | } |
| 622 | |
| 623 | static int qpnp_oledb_hw_init(struct qpnp_oledb *oledb) |
| 624 | { |
| 625 | int rc, i = 0; |
| 626 | u8 val = 0, mask = 0; |
| 627 | u16 current_voltage; |
| 628 | |
| 629 | if (oledb->default_voltage != -EINVAL) { |
| 630 | val = (oledb->default_voltage - OLEDB_VOUT_MIN_MV) / |
| 631 | OLEDB_VOUT_STEP_MV; |
| 632 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 633 | OLEDB_VOUT_DEFAULT, &val, 1); |
| 634 | if (rc < 0) { |
| 635 | pr_err("Failed to write VOUT_DEFAULT rc=%d\n", rc); |
| 636 | return rc; |
| 637 | } |
| 638 | } |
| 639 | |
| 640 | rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_ENABLE, |
| 641 | &oledb->mod_enable, 1); |
| 642 | if (rc < 0) { |
| 643 | pr_err("Failed to read MODULE_ENABLE rc=%d\n", rc); |
| 644 | return rc; |
| 645 | } |
| 646 | |
| 647 | rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL, |
| 648 | &oledb->ext_pinctl_state, 1); |
| 649 | if (rc < 0) { |
| 650 | pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc); |
| 651 | return rc; |
| 652 | } |
| 653 | |
| 654 | rc = qpnp_oledb_get_curr_voltage(oledb, ¤t_voltage); |
| 655 | if (rc < 0) |
| 656 | return rc; |
| 657 | |
| 658 | /* |
| 659 | * Go through if the module is not enabled either through |
| 660 | * external pin control or SPMI interface. |
| 661 | */ |
| 662 | if (!((oledb->ext_pinctl_state & OLEDB_EXT_PIN_CTL_BIT) |
| 663 | || oledb->mod_enable)) { |
| 664 | if (oledb->warmup_delay != -EINVAL) { |
| 665 | for (i = 0; i < ARRAY_SIZE(oledb_warmup_dly_ns); i++) { |
| 666 | if (oledb->warmup_delay == |
| 667 | oledb_warmup_dly_ns[i]) |
| 668 | break; |
| 669 | } |
| 670 | val = i; |
| 671 | rc = qpnp_oledb_masked_write(oledb, |
| 672 | oledb->base + OLEDB_BIAS_GEN_WARMUP_DELAY, |
| 673 | OLEDB_BIAS_GEN_WARMUP_DELAY_MASK, val); |
| 674 | if (rc < 0) { |
| 675 | pr_err("Failed to write WARMUP_DELAY rc=%d\n", |
| 676 | rc); |
| 677 | return rc; |
| 678 | } |
| 679 | } else { |
| 680 | rc = qpnp_oledb_read(oledb, oledb->base + |
| 681 | OLEDB_BIAS_GEN_WARMUP_DELAY, |
| 682 | &val, 1); |
| 683 | if (rc < 0) { |
| 684 | pr_err("Failed to read WARMUP_DELAY rc=%d\n", |
| 685 | rc); |
| 686 | return rc; |
| 687 | } |
| 688 | oledb->warmup_delay = oledb_warmup_dly_ns[val]; |
| 689 | } |
| 690 | |
| 691 | if (oledb->peak_curr_limit != -EINVAL) { |
| 692 | for (i = 0; i < ARRAY_SIZE(oledb_peak_curr_limit_ma); |
| 693 | i++) { |
| 694 | if (oledb->peak_curr_limit == |
| 695 | oledb_peak_curr_limit_ma[i]) |
| 696 | break; |
| 697 | } |
| 698 | val = i; |
| 699 | rc = qpnp_oledb_write(oledb, |
| 700 | oledb->base + OLEDB_ILIM_NFET, |
| 701 | &val, 1); |
| 702 | if (rc < 0) { |
| 703 | pr_err("Failed to write ILIM_NEFT rc=%d\n", rc); |
| 704 | return rc; |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | if (oledb->pd_ctl != -EINVAL) { |
| 709 | val = oledb->pd_ctl; |
| 710 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 711 | OLEDB_PD_CTL, &val, 1); |
| 712 | if (rc < 0) { |
| 713 | pr_err("Failed to write PD_CTL rc=%d\n", rc); |
| 714 | return rc; |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | if (oledb->sc_en != -EINVAL) { |
| 719 | val = oledb->sc_en ? OLEDB_ENABLE_SC_DETECTION_BIT : 0; |
| 720 | mask = OLEDB_ENABLE_SC_DETECTION_BIT; |
| 721 | if (oledb->sc_dbnc_time != -EINVAL) { |
| 722 | val |= SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL( |
| 723 | oledb->sc_dbnc_time); |
| 724 | mask |= OLEDB_DBNC_PRECHARGE_MASK; |
| 725 | } |
| 726 | |
| 727 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 728 | OLEDB_SHORT_PROTECT, &val, 1); |
| 729 | if (rc < 0) { |
| 730 | pr_err("Failed to write SHORT_PROTECT rc=%d\n", |
| 731 | rc); |
| 732 | return rc; |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | rc = qpnp_oledb_init_nlimit(oledb); |
| 737 | if (rc < 0) |
| 738 | return rc; |
| 739 | |
| 740 | rc = qpnp_oledb_init_psm(oledb); |
| 741 | if (rc < 0) |
| 742 | return rc; |
| 743 | |
| 744 | rc = qpnp_oledb_init_pfm(oledb); |
| 745 | if (rc < 0) |
| 746 | return rc; |
| 747 | |
| 748 | rc = qpnp_oledb_init_fast_precharge(oledb); |
| 749 | if (rc < 0) |
| 750 | return rc; |
| 751 | |
| 752 | if (oledb->swire_control) { |
| 753 | val = OLEDB_EN_SWIRE_PD_UPD_BIT | |
| 754 | OLEDB_EN_SWIRE_VOUT_UPD_BIT; |
| 755 | rc = qpnp_oledb_masked_write(oledb, oledb->base + |
| 756 | OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT | |
| 757 | OLEDB_EN_SWIRE_VOUT_UPD_BIT, val); |
| 758 | if (rc < 0) |
| 759 | return rc; |
| 760 | } |
| 761 | |
| 762 | rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_RDY, |
| 763 | &val, 1); |
| 764 | if (rc < 0) { |
| 765 | pr_err("Failed to read MODULE_RDY rc=%d\n", rc); |
| 766 | return rc; |
| 767 | } |
| 768 | |
| 769 | if (!(val & OLEDB_MODULE_RDY_BIT)) { |
| 770 | val = OLEDB_MODULE_RDY_BIT; |
| 771 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 772 | OLEDB_MODULE_RDY, &val, 1); |
| 773 | if (rc < 0) { |
| 774 | pr_err("Failed to write MODULE_RDY rc=%d\n", |
| 775 | rc); |
| 776 | return rc; |
| 777 | } |
| 778 | } |
| 779 | |
| 780 | if (!oledb->dynamic_ext_pinctl_config) { |
| 781 | if (oledb->ext_pin_control) { |
| 782 | val = OLEDB_EXT_PIN_CTL_BIT; |
| 783 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 784 | OLEDB_EXT_PIN_CTL, &val, 1); |
| 785 | if (rc < 0) { |
| 786 | pr_err("Failed to write EXT_PIN_CTL rc=%d\n", |
| 787 | rc); |
| 788 | return rc; |
| 789 | } |
| 790 | } else { |
| 791 | val = OLEDB_MODULE_ENABLE_BIT; |
| 792 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 793 | OLEDB_MODULE_ENABLE, &val, 1); |
| 794 | if (rc < 0) { |
| 795 | pr_err("Failed to write MODULE_ENABLE rc=%d\n", |
| 796 | rc); |
| 797 | return rc; |
| 798 | } |
| 799 | |
| 800 | ndelay(oledb->warmup_delay); |
| 801 | } |
| 802 | |
| 803 | oledb->mod_enable = true; |
| 804 | if (oledb->pbs_control) { |
| 805 | rc = qpnp_oledb_masked_write(oledb, |
| 806 | oledb->base + OLEDB_SWIRE_CONTROL, |
| 807 | OLEDB_EN_SWIRE_PD_UPD_BIT | |
| 808 | OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0); |
| 809 | if (rc < 0) { |
| 810 | pr_err("Failed to write SWIRE_CTL rc=%d\n", |
| 811 | rc); |
| 812 | return rc; |
| 813 | } |
| 814 | } |
| 815 | } |
| 816 | |
| 817 | oledb->current_voltage = current_voltage; |
| 818 | } else { |
| 819 | /* module is enabled */ |
| 820 | if (oledb->current_voltage == -EINVAL) { |
| 821 | oledb->current_voltage = current_voltage; |
| 822 | } else if (!oledb->swire_control) { |
| 823 | if (oledb->current_voltage < OLEDB_VOUT_MIN_MV) { |
| 824 | pr_err("current_voltage %d is less than min_volt %d\n", |
| 825 | oledb->current_voltage, OLEDB_VOUT_MIN_MV); |
| 826 | return -EINVAL; |
| 827 | } |
| 828 | val = DIV_ROUND_UP(oledb->current_voltage - |
| 829 | OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV); |
| 830 | rc = qpnp_oledb_write(oledb, oledb->base + |
| 831 | OLEDB_VOUT_PGM, &val, 1); |
| 832 | if (rc < 0) { |
| 833 | pr_err("Failed to write VOUT_PGM rc=%d\n", |
| 834 | rc); |
| 835 | return rc; |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | oledb->mod_enable = true; |
| 840 | } |
| 841 | |
| 842 | return rc; |
| 843 | } |
| 844 | |
| 845 | static int qpnp_oledb_parse_nlimit(struct qpnp_oledb *oledb) |
| 846 | { |
| 847 | int rc = 0; |
| 848 | struct device_node *of_node = oledb->dev->of_node; |
| 849 | |
| 850 | oledb->nlimit_enable = -EINVAL; |
| 851 | rc = of_property_read_u32(of_node, "qcom,negative-curr-limit-enable", |
| 852 | &oledb->nlimit_enable); |
| 853 | if (!rc) { |
| 854 | oledb->negative_curr_limit = -EINVAL; |
| 855 | rc = of_property_read_u32(of_node, |
| 856 | "qcom,negative-curr-limit-ma", |
| 857 | &oledb->negative_curr_limit); |
| 858 | if (!rc) { |
| 859 | u16 min_curr_limit = oledb_nlimit_ma[0]; |
| 860 | u16 max_curr_limit = oledb_nlimit_ma[ARRAY_SIZE( |
| 861 | oledb_nlimit_ma) - 1]; |
| 862 | if (oledb->negative_curr_limit < min_curr_limit || |
| 863 | oledb->negative_curr_limit > max_curr_limit) { |
| 864 | pr_err("Invalid value in qcom,negative-curr-limit-ma\n"); |
| 865 | return -EINVAL; |
| 866 | } |
| 867 | } |
| 868 | } |
| 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | static int qpnp_oledb_parse_psm(struct qpnp_oledb *oledb) |
| 874 | { |
| 875 | int rc = 0; |
| 876 | struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl; |
| 877 | struct device_node *of_node = oledb->dev->of_node; |
| 878 | |
| 879 | psm_ctl->psm_enable = -EINVAL; |
| 880 | rc = of_property_read_u32(of_node, "qcom,psm-enable", |
| 881 | &psm_ctl->psm_enable); |
| 882 | if (!rc) { |
| 883 | psm_ctl->psm_hys_ctl = -EINVAL; |
| 884 | rc = of_property_read_u32(of_node, "qcom,psm-hys-mv", |
| 885 | &psm_ctl->psm_hys_ctl); |
| 886 | if (!rc) { |
| 887 | if (psm_ctl->psm_hys_ctl < OLEDB_PSM_HYS_CTRL_MIN || |
| 888 | psm_ctl->psm_hys_ctl > OLEDB_PSM_HYS_CTRL_MAX) { |
| 889 | pr_err("Invalid value in qcom,psm-hys-mv\n"); |
| 890 | return -EINVAL; |
| 891 | } |
| 892 | } |
| 893 | |
| 894 | psm_ctl->psm_vref = -EINVAL; |
| 895 | rc = of_property_read_u32(of_node, "qcom,psm-vref-mv", |
| 896 | &psm_ctl->psm_vref); |
| 897 | if (!rc) { |
| 898 | u16 min_vref = oledb_psm_vref_mv[0]; |
| 899 | u16 max_vref = oledb_psm_vref_mv[ARRAY_SIZE( |
| 900 | oledb_psm_vref_mv) - 1]; |
| 901 | if (psm_ctl->psm_vref < min_vref || |
| 902 | psm_ctl->psm_vref > max_vref) { |
| 903 | pr_err("Invalid value in qcom,psm-vref-mv\n"); |
| 904 | return -EINVAL; |
| 905 | } |
| 906 | } |
| 907 | } |
| 908 | |
| 909 | return 0; |
| 910 | } |
| 911 | |
| 912 | static int qpnp_oledb_parse_pfm(struct qpnp_oledb *oledb) |
| 913 | { |
| 914 | int rc = 0; |
| 915 | struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl; |
| 916 | struct device_node *of_node = oledb->dev->of_node; |
| 917 | |
| 918 | pfm_ctl->pfm_enable = -EINVAL; |
| 919 | rc = of_property_read_u32(of_node, "qcom,pfm-enable", |
| 920 | &pfm_ctl->pfm_enable); |
| 921 | if (!rc) { |
| 922 | pfm_ctl->pfm_hys_ctl = -EINVAL; |
| 923 | rc = of_property_read_u32(of_node, "qcom,pfm-hys-mv", |
| 924 | &pfm_ctl->pfm_hys_ctl); |
| 925 | if (!rc) { |
| 926 | if (pfm_ctl->pfm_hys_ctl < OLEDB_PFM_HYS_CTRL_MIN || |
| 927 | pfm_ctl->pfm_hys_ctl > OLEDB_PFM_HYS_CTRL_MAX) { |
| 928 | pr_err("Invalid value in qcom,pfm-hys-mv\n"); |
| 929 | return -EINVAL; |
| 930 | } |
| 931 | } |
| 932 | |
| 933 | pfm_ctl->pfm_curr_limit = -EINVAL; |
| 934 | rc = of_property_read_u32(of_node, |
| 935 | "qcom,pfm-curr-limit-ma", &pfm_ctl->pfm_curr_limit); |
| 936 | if (!rc) { |
| 937 | u16 min_limit = oledb_pfm_curr_limit_ma[0]; |
| 938 | u16 max_limit = oledb_pfm_curr_limit_ma[ARRAY_SIZE( |
| 939 | oledb_pfm_curr_limit_ma) - 1]; |
| 940 | if (pfm_ctl->pfm_curr_limit < min_limit || |
| 941 | pfm_ctl->pfm_curr_limit > max_limit) { |
| 942 | pr_err("Invalid value in qcom,pfm-curr-limit-ma\n"); |
| 943 | return -EINVAL; |
| 944 | } |
| 945 | } |
| 946 | |
| 947 | pfm_ctl->pfm_off_time = -EINVAL; |
| 948 | rc = of_property_read_u32(of_node, "qcom,pfm-off-time-ns", |
| 949 | &pfm_ctl->pfm_off_time); |
| 950 | if (!rc) { |
| 951 | if (pfm_ctl->pfm_off_time < OLEDB_PFM_OFF_TIME_MIN || |
| 952 | pfm_ctl->pfm_off_time > OLEDB_PFM_OFF_TIME_MAX) { |
| 953 | pr_err("Invalid value in qcom,pfm-off-time-ns\n"); |
| 954 | return -EINVAL; |
| 955 | } |
| 956 | } |
| 957 | } |
| 958 | |
| 959 | return 0; |
| 960 | } |
| 961 | |
| 962 | static int qpnp_oledb_parse_fast_precharge(struct qpnp_oledb *oledb) |
| 963 | { |
| 964 | int rc = 0; |
| 965 | struct device_node *of_node = oledb->dev->of_node; |
| 966 | struct qpnp_oledb_fast_precharge_ctl *fast_prechg = |
| 967 | &oledb->fast_prechg_ctl; |
| 968 | |
| 969 | fast_prechg->fast_prechg_ppulse_en = -EINVAL; |
| 970 | rc = of_property_read_u32(of_node, "qcom,fast-precharge-ppulse-enable", |
| 971 | &fast_prechg->fast_prechg_ppulse_en); |
| 972 | if (!rc) { |
| 973 | fast_prechg->prechg_debounce_time = -EINVAL; |
| 974 | rc = of_property_read_u32(of_node, |
| 975 | "qcom,precharge-debounce-time-ms", |
| 976 | &fast_prechg->prechg_debounce_time); |
| 977 | if (!rc) { |
| 978 | int dbnc_time = fast_prechg->prechg_debounce_time; |
| 979 | |
| 980 | if (dbnc_time < OLEDB_PRECHG_TIME_MIN || dbnc_time > |
| 981 | OLEDB_PRECHG_TIME_MAX) { |
| 982 | pr_err("Invalid value in qcom,precharge-debounce-time-ms\n"); |
| 983 | return -EINVAL; |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | fast_prechg->prechg_pulse_period = -EINVAL; |
| 988 | rc = of_property_read_u32(of_node, |
| 989 | "qcom,precharge-pulse-period-us", |
| 990 | &fast_prechg->prechg_pulse_period); |
| 991 | if (!rc) { |
| 992 | int pulse_period = fast_prechg->prechg_pulse_period; |
| 993 | |
| 994 | if (pulse_period < OLEDB_PRECHG_PULSE_PERIOD_MIN || |
| 995 | pulse_period > OLEDB_PRECHG_PULSE_PERIOD_MAX) { |
| 996 | pr_err("Invalid value in qcom,precharge-pulse-period-us\n"); |
| 997 | return -EINVAL; |
| 998 | } |
| 999 | } |
| 1000 | |
| 1001 | fast_prechg->prechg_pulse_on_time = -EINVAL; |
| 1002 | rc = of_property_read_u32(of_node, |
| 1003 | "qcom,precharge-pulse-on-time-ns", |
| 1004 | &fast_prechg->prechg_pulse_on_time); |
| 1005 | if (!rc) { |
| 1006 | int pulse_on_time = fast_prechg->prechg_pulse_on_time; |
| 1007 | |
| 1008 | if (pulse_on_time < OLEDB_PRECHG_PULSE_ON_TIME_MIN || |
| 1009 | pulse_on_time > OLEDB_PRECHG_PULSE_ON_TIME_MAX) { |
| 1010 | pr_err("Invalid value in qcom,precharge-pulse-on-time-ns\n"); |
| 1011 | return -EINVAL; |
| 1012 | } |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | static int qpnp_oledb_parse_dt(struct qpnp_oledb *oledb) |
| 1020 | { |
| 1021 | int rc = 0; |
| 1022 | struct device_node *of_node = oledb->dev->of_node; |
| 1023 | |
| 1024 | oledb->swire_control = |
| 1025 | of_property_read_bool(of_node, "qcom,swire-control"); |
| 1026 | |
| 1027 | oledb->ext_pin_control = |
| 1028 | of_property_read_bool(of_node, "qcom,ext-pin-control"); |
| 1029 | |
| 1030 | if (oledb->ext_pin_control) |
| 1031 | oledb->dynamic_ext_pinctl_config = |
| 1032 | of_property_read_bool(of_node, |
| 1033 | "qcom,dynamic-ext-pinctl-config"); |
| 1034 | oledb->pbs_control = |
| 1035 | of_property_read_bool(of_node, "qcom,pbs-control"); |
| 1036 | |
| 1037 | oledb->current_voltage = -EINVAL; |
| 1038 | rc = of_property_read_u32(of_node, "qcom,oledb-init-voltage-mv", |
| 1039 | &oledb->current_voltage); |
| 1040 | if (!rc && (oledb->current_voltage < OLEDB_VOUT_MIN_MV || |
| 1041 | oledb->current_voltage > OLEDB_VOUT_MAX_MV)) { |
| 1042 | pr_err("Invalid value in qcom,oledb-init-voltage-mv\n"); |
| 1043 | return -EINVAL; |
| 1044 | } |
| 1045 | |
| 1046 | oledb->default_voltage = -EINVAL; |
| 1047 | rc = of_property_read_u32(of_node, "qcom,oledb-default-voltage-mv", |
| 1048 | &oledb->default_voltage); |
| 1049 | if (!rc && (oledb->default_voltage < OLEDB_VOUT_MIN_MV || |
| 1050 | oledb->default_voltage > OLEDB_VOUT_MAX_MV)) { |
| 1051 | pr_err("Invalid value in qcom,oledb-default-voltage-mv\n"); |
| 1052 | return -EINVAL; |
| 1053 | } |
| 1054 | |
| 1055 | oledb->warmup_delay = -EINVAL; |
| 1056 | rc = of_property_read_u32(of_node, "qcom,bias-gen-warmup-delay-ns", |
| 1057 | &oledb->warmup_delay); |
| 1058 | if (!rc) { |
| 1059 | u16 min_delay = oledb_warmup_dly_ns[0]; |
| 1060 | u16 max_delay = oledb_warmup_dly_ns[ARRAY_SIZE( |
| 1061 | oledb_warmup_dly_ns) - 1]; |
| 1062 | if (oledb->warmup_delay < min_delay || |
| 1063 | oledb->warmup_delay > max_delay) { |
| 1064 | pr_err("Invalid value in qcom,bias-gen-warmup-delay-ns\n"); |
| 1065 | return -EINVAL; |
| 1066 | } |
| 1067 | } |
| 1068 | |
| 1069 | oledb->peak_curr_limit = -EINVAL; |
| 1070 | rc = of_property_read_u32(of_node, "qcom,peak-curr-limit-ma", |
| 1071 | &oledb->peak_curr_limit); |
| 1072 | if (!rc) { |
| 1073 | u16 min_limit = oledb_peak_curr_limit_ma[0]; |
| 1074 | u16 max_limit = oledb_peak_curr_limit_ma[ARRAY_SIZE( |
| 1075 | oledb_peak_curr_limit_ma) - 1]; |
| 1076 | if (oledb->peak_curr_limit < min_limit || |
| 1077 | oledb->peak_curr_limit > max_limit) { |
| 1078 | pr_err("Invalid value in qcom,peak-curr-limit-ma\n"); |
| 1079 | return -EINVAL; |
| 1080 | } |
| 1081 | } |
| 1082 | |
| 1083 | oledb->pd_ctl = -EINVAL; |
| 1084 | of_property_read_u32(of_node, "qcom,pull-down-enable", &oledb->pd_ctl); |
| 1085 | |
| 1086 | oledb->sc_en = -EINVAL; |
| 1087 | rc = of_property_read_u32(of_node, "qcom,enable-short-circuit", |
| 1088 | &oledb->sc_en); |
| 1089 | if (!rc) { |
| 1090 | oledb->sc_dbnc_time = -EINVAL; |
| 1091 | rc = of_property_read_u32(of_node, |
| 1092 | "qcom,short-circuit-dbnc-time", &oledb->sc_dbnc_time); |
| 1093 | if (!rc) { |
| 1094 | if (oledb->sc_dbnc_time < OLEDB_MIN_SC_DBNC_TIME_FSW || |
| 1095 | oledb->sc_dbnc_time > OLEDB_MAX_SC_DBNC_TIME_FSW) { |
| 1096 | pr_err("Invalid value in qcom,short-circuit-dbnc-time\n"); |
| 1097 | return -EINVAL; |
| 1098 | } |
| 1099 | } |
| 1100 | } |
| 1101 | |
| 1102 | rc = qpnp_oledb_parse_nlimit(oledb); |
| 1103 | if (rc < 0) |
| 1104 | return rc; |
| 1105 | |
| 1106 | rc = qpnp_oledb_parse_psm(oledb); |
| 1107 | if (rc < 0) |
| 1108 | return rc; |
| 1109 | |
| 1110 | rc = qpnp_oledb_parse_pfm(oledb); |
| 1111 | if (rc < 0) |
| 1112 | return rc; |
| 1113 | |
| 1114 | rc = qpnp_oledb_parse_fast_precharge(oledb); |
| 1115 | |
| 1116 | return rc; |
| 1117 | } |
| 1118 | |
| 1119 | static int qpnp_oledb_regulator_probe(struct platform_device *pdev) |
| 1120 | { |
| 1121 | int rc = 0; |
| 1122 | u32 val; |
| 1123 | struct qpnp_oledb *oledb; |
| 1124 | struct device_node *of_node = pdev->dev.of_node; |
| 1125 | |
| 1126 | oledb = devm_kzalloc(&pdev->dev, |
| 1127 | sizeof(struct qpnp_oledb), GFP_KERNEL); |
| 1128 | if (!oledb) |
| 1129 | return -ENOMEM; |
| 1130 | |
| 1131 | oledb->pdev = pdev; |
| 1132 | oledb->dev = &pdev->dev; |
| 1133 | oledb->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 1134 | dev_set_drvdata(&pdev->dev, oledb); |
| 1135 | if (!oledb->regmap) { |
| 1136 | pr_err("Couldn't get parent's regmap\n"); |
| 1137 | return -EINVAL; |
| 1138 | } |
| 1139 | |
| 1140 | rc = of_property_read_u32(of_node, "reg", &val); |
| 1141 | if (rc < 0) { |
| 1142 | pr_err("Couldn't find reg in node, rc = %d\n", rc); |
| 1143 | return rc; |
| 1144 | } |
| 1145 | |
| 1146 | oledb->base = val; |
| 1147 | rc = qpnp_oledb_parse_dt(oledb); |
| 1148 | if (rc < 0) { |
| 1149 | pr_err("Failed to parse common OLEDB device tree\n"); |
| 1150 | return rc; |
| 1151 | } |
| 1152 | |
| 1153 | rc = qpnp_oledb_hw_init(oledb); |
| 1154 | if (rc < 0) { |
| 1155 | pr_err("Failed to initialize OLEDB, rc=%d\n", rc); |
| 1156 | return rc; |
| 1157 | } |
| 1158 | |
| 1159 | rc = qpnp_oledb_register_regulator(oledb); |
| 1160 | if (!rc) |
| 1161 | pr_info("OLEDB registered successfully, ext_pin_en=%d mod_en=%d cuurent_voltage=%d mV\n", |
| 1162 | oledb->ext_pin_control, oledb->mod_enable, |
| 1163 | oledb->current_voltage); |
| 1164 | |
| 1165 | return rc; |
| 1166 | } |
| 1167 | |
| 1168 | static int qpnp_oledb_regulator_remove(struct platform_device *pdev) |
| 1169 | { |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
| 1173 | const struct of_device_id qpnp_oledb_regulator_match_table[] = { |
| 1174 | { .compatible = QPNP_OLEDB_REGULATOR_DRIVER_NAME,}, |
| 1175 | { }, |
| 1176 | }; |
| 1177 | |
| 1178 | static struct platform_driver qpnp_oledb_regulator_driver = { |
| 1179 | .driver = { |
| 1180 | .name = QPNP_OLEDB_REGULATOR_DRIVER_NAME, |
| 1181 | .of_match_table = qpnp_oledb_regulator_match_table, |
| 1182 | }, |
| 1183 | .probe = qpnp_oledb_regulator_probe, |
| 1184 | .remove = qpnp_oledb_regulator_remove, |
| 1185 | }; |
| 1186 | |
| 1187 | static int __init qpnp_oledb_regulator_init(void) |
| 1188 | { |
| 1189 | return platform_driver_register(&qpnp_oledb_regulator_driver); |
| 1190 | } |
| 1191 | arch_initcall(qpnp_oledb_regulator_init); |
| 1192 | |
| 1193 | static void __exit qpnp_oledb_regulator_exit(void) |
| 1194 | { |
| 1195 | platform_driver_unregister(&qpnp_oledb_regulator_driver); |
| 1196 | } |
| 1197 | module_exit(qpnp_oledb_regulator_exit); |
| 1198 | |
| 1199 | MODULE_DESCRIPTION("QPNP OLEDB driver"); |
| 1200 | MODULE_LICENSE("GPL v2"); |
| 1201 | MODULE_ALIAS("qpnp-oledb-regulator"); |