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Shawn Guo95ceafd2012-09-06 07:09:11 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * The OPP code in function cpu0_set_target() is reused from
5 * drivers/cpufreq/omap-cpufreq.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/clk.h>
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +010015#include <linux/cpu.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040016#include <linux/cpu_cooling.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000017#include <linux/cpufreq.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040018#include <linux/cpumask.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000019#include <linux/err.h>
20#include <linux/module.h>
21#include <linux/of.h>
Nishanth Menone4db1c72013-09-19 16:03:52 -050022#include <linux/pm_opp.h>
Shawn Guo5553f9e2013-01-30 14:27:49 +000023#include <linux/platform_device.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000024#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040026#include <linux/thermal.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000027
28static unsigned int transition_latency;
29static unsigned int voltage_tolerance; /* in percentage */
30
31static struct device *cpu_dev;
32static struct clk *cpu_clk;
33static struct regulator *cpu_reg;
34static struct cpufreq_frequency_table *freq_table;
Eduardo Valentin77cff592013-07-15 09:09:14 -040035static struct thermal_cooling_device *cdev;
Shawn Guo95ceafd2012-09-06 07:09:11 +000036
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053037static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
Shawn Guo95ceafd2012-09-06 07:09:11 +000038{
Nishanth Menon47d43ba2013-09-19 16:03:51 -050039 struct dev_pm_opp *opp;
jhbird.choi@samsung.com5df60552013-03-18 08:09:42 +000040 unsigned long volt = 0, volt_old = 0, tol = 0;
Viresh Kumard4019f02013-08-14 19:38:24 +053041 unsigned int old_freq, new_freq;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010042 long freq_Hz, freq_exact;
Shawn Guo95ceafd2012-09-06 07:09:11 +000043 int ret;
44
Shawn Guo95ceafd2012-09-06 07:09:11 +000045 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
Paul Walmsley2209b0c2013-11-25 18:01:18 -080046 if (freq_Hz <= 0)
Shawn Guo95ceafd2012-09-06 07:09:11 +000047 freq_Hz = freq_table[index].frequency * 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000048
Viresh Kumard4019f02013-08-14 19:38:24 +053049 freq_exact = freq_Hz;
50 new_freq = freq_Hz / 1000;
51 old_freq = clk_get_rate(cpu_clk) / 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000052
Mark Brown4a511de2013-08-13 14:58:24 +020053 if (!IS_ERR(cpu_reg)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000054 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -050055 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
Shawn Guo95ceafd2012-09-06 07:09:11 +000056 if (IS_ERR(opp)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000057 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000058 pr_err("failed to find OPP for %ld\n", freq_Hz);
Viresh Kumard4019f02013-08-14 19:38:24 +053059 return PTR_ERR(opp);
Shawn Guo95ceafd2012-09-06 07:09:11 +000060 }
Nishanth Menon5d4879c2013-09-19 16:03:50 -050061 volt = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +000062 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000063 tol = volt * voltage_tolerance / 100;
64 volt_old = regulator_get_voltage(cpu_reg);
65 }
66
67 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
Viresh Kumard4019f02013-08-14 19:38:24 +053068 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
69 new_freq / 1000, volt ? volt / 1000 : -1);
Shawn Guo95ceafd2012-09-06 07:09:11 +000070
71 /* scaling up? scale voltage before frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053072 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000073 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
74 if (ret) {
75 pr_err("failed to scale voltage up: %d\n", ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053076 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000077 }
78 }
79
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010080 ret = clk_set_rate(cpu_clk, freq_exact);
Shawn Guo95ceafd2012-09-06 07:09:11 +000081 if (ret) {
82 pr_err("failed to set clock rate: %d\n", ret);
Mark Brown4a511de2013-08-13 14:58:24 +020083 if (!IS_ERR(cpu_reg))
Shawn Guo95ceafd2012-09-06 07:09:11 +000084 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
Viresh Kumard4019f02013-08-14 19:38:24 +053085 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000086 }
87
88 /* scaling down? scale voltage after frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053089 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000090 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
91 if (ret) {
92 pr_err("failed to scale voltage down: %d\n", ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053093 clk_set_rate(cpu_clk, old_freq * 1000);
Shawn Guo95ceafd2012-09-06 07:09:11 +000094 }
95 }
96
Viresh Kumarfd143b42013-04-01 12:57:44 +000097 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000098}
99
100static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
101{
Viresh Kumar652ed952014-01-09 20:38:43 +0530102 policy->clk = cpu_clk;
Viresh Kumar78b3d102013-10-03 20:29:09 +0530103 return cpufreq_generic_init(policy, freq_table, transition_latency);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000104}
105
Shawn Guo95ceafd2012-09-06 07:09:11 +0000106static struct cpufreq_driver cpu0_cpufreq_driver = {
Viresh Kumar93575b72014-06-09 19:06:17 +0530107 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
Viresh Kumarf793d792013-10-03 20:28:00 +0530108 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +0530109 .target_index = cpu0_set_target,
Viresh Kumar652ed952014-01-09 20:38:43 +0530110 .get = cpufreq_generic_get,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000111 .init = cpu0_cpufreq_init,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000112 .name = "generic_cpu0",
Viresh Kumarf793d792013-10-03 20:28:00 +0530113 .attr = cpufreq_generic_attr,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000114};
115
Shawn Guo5553f9e2013-01-30 14:27:49 +0000116static int cpu0_cpufreq_probe(struct platform_device *pdev)
Shawn Guo95ceafd2012-09-06 07:09:11 +0000117{
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100118 struct device_node *np;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000119 int ret;
120
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100121 cpu_dev = get_cpu_device(0);
122 if (!cpu_dev) {
123 pr_err("failed to get cpu0 device\n");
124 return -ENODEV;
125 }
Paolo Pisatif5c3ef22013-03-28 09:24:29 +0000126
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100127 np = of_node_get(cpu_dev->of_node);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000128 if (!np) {
129 pr_err("failed to find cpu0 node\n");
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100130 return -ENOENT;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000131 }
132
Lucas Stache3beb0a2014-05-16 12:20:42 +0200133 cpu_reg = regulator_get_optional(cpu_dev, "cpu0");
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000134 if (IS_ERR(cpu_reg)) {
135 /*
136 * If cpu0 regulator supply node is present, but regulator is
137 * not yet registered, we should try defering probe.
138 */
139 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
Markus Pargmann713a3fa2014-08-04 14:48:03 +0200140 dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000141 ret = -EPROBE_DEFER;
142 goto out_put_node;
143 }
144 pr_warn("failed to get cpu0 regulator: %ld\n",
145 PTR_ERR(cpu_reg));
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000146 }
147
Lucas Stache3beb0a2014-05-16 12:20:42 +0200148 cpu_clk = clk_get(cpu_dev, NULL);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000149 if (IS_ERR(cpu_clk)) {
150 ret = PTR_ERR(cpu_clk);
151 pr_err("failed to get cpu0 clock: %d\n", ret);
Lucas Stache3beb0a2014-05-16 12:20:42 +0200152 goto out_put_reg;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000153 }
154
Viresh Kumar1bf8cc32014-07-11 20:24:19 +0530155 /* OPPs might be populated at runtime, don't check for error here */
156 of_init_opp_table(cpu_dev);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000157
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500158 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000159 if (ret) {
160 pr_err("failed to init cpufreq table: %d\n", ret);
Lucas Stache3beb0a2014-05-16 12:20:42 +0200161 goto out_put_clk;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000162 }
163
164 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
165
166 if (of_property_read_u32(np, "clock-latency", &transition_latency))
167 transition_latency = CPUFREQ_ETERNAL;
168
Philipp Zabel43c638e2013-09-26 11:19:37 +0200169 if (!IS_ERR(cpu_reg)) {
Nishanth Menon47d43ba2013-09-19 16:03:51 -0500170 struct dev_pm_opp *opp;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000171 unsigned long min_uV, max_uV;
172 int i;
173
174 /*
175 * OPP is maintained in order of increasing frequency, and
176 * freq_table initialised from OPP is therefore sorted in the
177 * same order.
178 */
179 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
180 ;
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000181 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500182 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000183 freq_table[0].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500184 min_uV = dev_pm_opp_get_voltage(opp);
185 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000186 freq_table[i-1].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500187 max_uV = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000188 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +0000189 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
190 if (ret > 0)
191 transition_latency += ret * 1000;
192 }
193
194 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
195 if (ret) {
196 pr_err("failed register driver: %d\n", ret);
197 goto out_free_table;
198 }
199
Eduardo Valentin77cff592013-07-15 09:09:14 -0400200 /*
201 * For now, just loading the cooling device;
202 * thermal DT code takes care of matching them.
203 */
204 if (of_find_property(np, "#cooling-cells", NULL)) {
205 cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
206 if (IS_ERR(cdev))
207 pr_err("running cpufreq without cooling device: %ld\n",
208 PTR_ERR(cdev));
209 }
210
Shawn Guo95ceafd2012-09-06 07:09:11 +0000211 of_node_put(np);
212 return 0;
213
214out_free_table:
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500215 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Lucas Stache3beb0a2014-05-16 12:20:42 +0200216out_put_clk:
217 if (!IS_ERR(cpu_clk))
218 clk_put(cpu_clk);
219out_put_reg:
220 if (!IS_ERR(cpu_reg))
221 regulator_put(cpu_reg);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000222out_put_node:
223 of_node_put(np);
224 return ret;
225}
Shawn Guo5553f9e2013-01-30 14:27:49 +0000226
227static int cpu0_cpufreq_remove(struct platform_device *pdev)
228{
Eduardo Valentin77cff592013-07-15 09:09:14 -0400229 cpufreq_cooling_unregister(cdev);
Shawn Guo5553f9e2013-01-30 14:27:49 +0000230 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500231 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo5553f9e2013-01-30 14:27:49 +0000232
233 return 0;
234}
235
236static struct platform_driver cpu0_cpufreq_platdrv = {
237 .driver = {
238 .name = "cpufreq-cpu0",
239 .owner = THIS_MODULE,
240 },
241 .probe = cpu0_cpufreq_probe,
242 .remove = cpu0_cpufreq_remove,
243};
244module_platform_driver(cpu0_cpufreq_platdrv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000245
246MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
247MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
248MODULE_LICENSE("GPL");