Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/asm-arm/arch-pxa/pxa-regs.h |
| 3 | * |
| 4 | * Author: Nicolas Pitre |
| 5 | * Created: Jun 15, 2001 |
| 6 | * Copyright: MontaVista Software Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __PXA_REGS_H |
| 14 | #define __PXA_REGS_H |
| 15 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * PXA Chip selects |
| 19 | */ |
| 20 | |
| 21 | #define PXA_CS0_PHYS 0x00000000 |
| 22 | #define PXA_CS1_PHYS 0x04000000 |
| 23 | #define PXA_CS2_PHYS 0x08000000 |
| 24 | #define PXA_CS3_PHYS 0x0C000000 |
| 25 | #define PXA_CS4_PHYS 0x10000000 |
| 26 | #define PXA_CS5_PHYS 0x14000000 |
| 27 | |
| 28 | |
| 29 | /* |
| 30 | * Personal Computer Memory Card International Association (PCMCIA) sockets |
| 31 | */ |
| 32 | |
| 33 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ |
| 34 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ |
| 35 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ |
| 36 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ |
| 37 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ |
| 38 | |
| 39 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ |
| 40 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ |
| 41 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ |
| 42 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ |
| 43 | |
| 44 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ |
| 45 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ |
| 46 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ |
| 47 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ |
| 48 | |
| 49 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ |
| 50 | (0x20000000 + (Nb)*PCMCIASp) |
| 51 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ |
| 52 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ |
| 53 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) |
| 54 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ |
| 55 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) |
| 56 | |
| 57 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ |
| 58 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ |
| 59 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ |
| 60 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ |
| 61 | |
| 62 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ |
| 63 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ |
| 64 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ |
| 65 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ |
| 66 | |
| 67 | |
| 68 | |
| 69 | /* |
| 70 | * DMA Controller |
| 71 | */ |
| 72 | |
| 73 | #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ |
| 74 | #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ |
| 75 | #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ |
| 76 | #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ |
| 77 | #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ |
| 78 | #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ |
| 79 | #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ |
| 80 | #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ |
| 81 | #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ |
| 82 | #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ |
| 83 | #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ |
| 84 | #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ |
| 85 | #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ |
| 86 | #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ |
| 87 | #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ |
| 88 | #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ |
| 89 | |
| 90 | #define DCSR(x) __REG2(0x40000000, (x) << 2) |
| 91 | |
| 92 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ |
| 93 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ |
| 94 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ |
| 95 | #ifdef CONFIG_PXA27x |
| 96 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ |
| 97 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ |
| 98 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ |
| 99 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ |
| 100 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ |
| 101 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ |
| 102 | #define DCSR_ENRINTR (1 << 9) /* The end of Receive */ |
| 103 | #endif |
| 104 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ |
| 105 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ |
| 106 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ |
| 107 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ |
| 108 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ |
| 109 | |
David Vrabel | 68477d1 | 2006-01-18 22:38:44 +0000 | [diff] [blame] | 110 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ |
| 112 | |
| 113 | #define DRCMR(n) __REG2(0x40000100, (n)<<2) |
| 114 | #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ |
| 115 | #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ |
| 116 | #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ |
| 117 | #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ |
| 118 | #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ |
| 119 | #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ |
| 120 | #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ |
| 121 | #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ |
| 122 | #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ |
| 123 | #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ |
| 124 | #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ |
| 125 | #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ |
| 126 | #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ |
| 127 | #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ |
| 128 | #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ |
Liam Girdwood | a451e28 | 2005-10-12 19:58:12 +0100 | [diff] [blame] | 129 | #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */ |
| 130 | #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ |
| 132 | #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ |
| 133 | #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ |
| 134 | #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ |
| 135 | #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ |
| 136 | #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ |
| 137 | #define DRCMR23 __REG(0x4000015c) /* Reserved */ |
| 138 | #define DRCMR24 __REG(0x40000160) /* Reserved */ |
| 139 | #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ |
| 140 | #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ |
| 141 | #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ |
| 142 | #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ |
| 143 | #define DRCMR29 __REG(0x40000174) /* Reserved */ |
| 144 | #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ |
| 145 | #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ |
| 146 | #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ |
| 147 | #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ |
| 148 | #define DRCMR34 __REG(0x40000188) /* Reserved */ |
| 149 | #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ |
| 150 | #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ |
| 151 | #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ |
| 152 | #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ |
| 153 | #define DRCMR39 __REG(0x4000019C) /* Reserved */ |
Liam Girdwood | a451e28 | 2005-10-12 19:58:12 +0100 | [diff] [blame] | 154 | #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */ |
| 155 | #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ |
| 157 | #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ |
| 158 | #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ |
| 159 | |
| 160 | #define DRCMRRXSADR DRCMR2 |
| 161 | #define DRCMRTXSADR DRCMR3 |
| 162 | #define DRCMRRXBTRBR DRCMR4 |
| 163 | #define DRCMRTXBTTHR DRCMR5 |
| 164 | #define DRCMRRXFFRBR DRCMR6 |
| 165 | #define DRCMRTXFFTHR DRCMR7 |
| 166 | #define DRCMRRXMCDR DRCMR8 |
| 167 | #define DRCMRRXMODR DRCMR9 |
| 168 | #define DRCMRTXMODR DRCMR10 |
| 169 | #define DRCMRRXPCDR DRCMR11 |
| 170 | #define DRCMRTXPCDR DRCMR12 |
| 171 | #define DRCMRRXSSDR DRCMR13 |
| 172 | #define DRCMRTXSSDR DRCMR14 |
| 173 | #define DRCMRRXSS2DR DRCMR15 |
| 174 | #define DRCMRTXSS2DR DRCMR16 |
| 175 | #define DRCMRRXICDR DRCMR17 |
| 176 | #define DRCMRTXICDR DRCMR18 |
| 177 | #define DRCMRRXSTRBR DRCMR19 |
| 178 | #define DRCMRTXSTTHR DRCMR20 |
| 179 | #define DRCMRRXMMC DRCMR21 |
| 180 | #define DRCMRTXMMC DRCMR22 |
| 181 | #define DRCMRRXSS3DR DRCMR66 |
| 182 | #define DRCMRTXSS3DR DRCMR67 |
| 183 | #define DRCMRUDC(x) DRCMR((x) + 24) |
| 184 | |
| 185 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ |
| 186 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ |
| 187 | |
| 188 | #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ |
| 189 | #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ |
| 190 | #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ |
| 191 | #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ |
| 192 | #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ |
| 193 | #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ |
| 194 | #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ |
| 195 | #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ |
| 196 | #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ |
| 197 | #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ |
| 198 | #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ |
| 199 | #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ |
| 200 | #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ |
| 201 | #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ |
| 202 | #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ |
| 203 | #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ |
| 204 | #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ |
| 205 | #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ |
| 206 | #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ |
| 207 | #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ |
| 208 | #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ |
| 209 | #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ |
| 210 | #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ |
| 211 | #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ |
| 212 | #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ |
| 213 | #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ |
| 214 | #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ |
| 215 | #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ |
| 216 | #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ |
| 217 | #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ |
| 218 | #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ |
| 219 | #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ |
| 220 | #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ |
| 221 | #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ |
| 222 | #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ |
| 223 | #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ |
| 224 | #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ |
| 225 | #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ |
| 226 | #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ |
| 227 | #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ |
| 228 | #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ |
| 229 | #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ |
| 230 | #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ |
| 231 | #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ |
| 232 | #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ |
| 233 | #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ |
| 234 | #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ |
| 235 | #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ |
| 236 | #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ |
| 237 | #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ |
| 238 | #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ |
| 239 | #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ |
| 240 | #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ |
| 241 | #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ |
| 242 | #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ |
| 243 | #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ |
| 244 | #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ |
| 245 | #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ |
| 246 | #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ |
| 247 | #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ |
| 248 | #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ |
| 249 | #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ |
| 250 | #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ |
| 251 | #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ |
| 252 | |
| 253 | #define DDADR(x) __REG2(0x40000200, (x) << 4) |
| 254 | #define DSADR(x) __REG2(0x40000204, (x) << 4) |
| 255 | #define DTADR(x) __REG2(0x40000208, (x) << 4) |
| 256 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) |
| 257 | |
| 258 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ |
| 259 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ |
| 260 | |
| 261 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ |
| 262 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ |
| 263 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ |
| 264 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ |
| 265 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ |
| 266 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ |
| 267 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ |
| 268 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ |
| 269 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ |
| 270 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ |
| 271 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ |
| 272 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ |
| 273 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ |
| 274 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
| 275 | |
| 276 | |
| 277 | /* |
| 278 | * UARTs |
| 279 | */ |
| 280 | |
| 281 | /* Full Function UART (FFUART) */ |
| 282 | #define FFUART FFRBR |
| 283 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ |
| 284 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ |
| 285 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ |
| 286 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ |
| 287 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ |
| 288 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ |
| 289 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ |
| 290 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ |
| 291 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ |
| 292 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ |
| 293 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ |
| 294 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ |
| 295 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ |
| 296 | |
| 297 | /* Bluetooth UART (BTUART) */ |
| 298 | #define BTUART BTRBR |
| 299 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ |
| 300 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ |
| 301 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ |
| 302 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ |
| 303 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ |
| 304 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ |
| 305 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ |
| 306 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ |
| 307 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ |
| 308 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ |
| 309 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ |
| 310 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ |
| 311 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ |
| 312 | |
| 313 | /* Standard UART (STUART) */ |
| 314 | #define STUART STRBR |
| 315 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ |
| 316 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ |
| 317 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ |
| 318 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ |
| 319 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ |
| 320 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ |
| 321 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ |
| 322 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ |
| 323 | #define STMSR __REG(0x40700018) /* Reserved */ |
| 324 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ |
| 325 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ |
| 326 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ |
| 327 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ |
| 328 | |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 329 | /* Hardware UART (HWUART) */ |
| 330 | #define HWUART HWRBR |
| 331 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ |
| 332 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ |
| 333 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ |
| 334 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ |
| 335 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ |
| 336 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ |
| 337 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ |
| 338 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ |
| 339 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ |
| 340 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ |
| 341 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ |
| 342 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ |
| 343 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ |
| 344 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ |
| 345 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ |
| 346 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ |
| 347 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ |
| 349 | #define IER_UUE (1 << 6) /* UART Unit Enable */ |
| 350 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ |
| 351 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ |
| 352 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ |
| 353 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ |
| 354 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ |
| 355 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ |
| 356 | |
| 357 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ |
| 358 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ |
| 359 | #define IIR_TOD (1 << 3) /* Time Out Detected */ |
| 360 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ |
| 361 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ |
| 362 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ |
| 363 | |
| 364 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ |
| 365 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ |
| 366 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ |
| 367 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ |
| 368 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ |
| 369 | #define FCR_ITL_1 (0) |
| 370 | #define FCR_ITL_8 (FCR_ITL1) |
| 371 | #define FCR_ITL_16 (FCR_ITL2) |
| 372 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) |
| 373 | |
| 374 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ |
| 375 | #define LCR_SB (1 << 6) /* Set Break */ |
| 376 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ |
| 377 | #define LCR_EPS (1 << 4) /* Even Parity Select */ |
| 378 | #define LCR_PEN (1 << 3) /* Parity Enable */ |
| 379 | #define LCR_STB (1 << 2) /* Stop Bit */ |
| 380 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ |
| 381 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ |
| 382 | |
| 383 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ |
| 384 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ |
| 385 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ |
| 386 | #define LSR_BI (1 << 4) /* Break Interrupt */ |
| 387 | #define LSR_FE (1 << 3) /* Framing Error */ |
| 388 | #define LSR_PE (1 << 2) /* Parity Error */ |
| 389 | #define LSR_OE (1 << 1) /* Overrun Error */ |
| 390 | #define LSR_DR (1 << 0) /* Data Ready */ |
| 391 | |
| 392 | #define MCR_LOOP (1 << 4) |
| 393 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ |
| 394 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ |
| 395 | #define MCR_RTS (1 << 1) /* Request to Send */ |
| 396 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ |
| 397 | |
| 398 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ |
| 399 | #define MSR_RI (1 << 6) /* Ring Indicator */ |
| 400 | #define MSR_DSR (1 << 5) /* Data Set Ready */ |
| 401 | #define MSR_CTS (1 << 4) /* Clear To Send */ |
| 402 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ |
| 403 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ |
| 404 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ |
| 405 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ |
| 406 | |
| 407 | /* |
| 408 | * IrSR (Infrared Selection Register) |
| 409 | */ |
| 410 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ |
| 411 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ |
| 412 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ |
| 413 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ |
| 414 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ |
| 415 | |
| 416 | |
| 417 | /* |
| 418 | * I2C registers |
| 419 | */ |
| 420 | |
| 421 | #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ |
| 422 | #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ |
| 423 | #define ICR __REG(0x40301690) /* I2C Control Register - ICR */ |
| 424 | #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ |
| 425 | #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ |
| 426 | |
| 427 | #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ |
| 428 | #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ |
| 429 | #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ |
| 430 | #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ |
| 431 | #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */ |
| 432 | |
| 433 | #define ICR_START (1 << 0) /* start bit */ |
| 434 | #define ICR_STOP (1 << 1) /* stop bit */ |
| 435 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ |
| 436 | #define ICR_TB (1 << 3) /* transfer byte bit */ |
| 437 | #define ICR_MA (1 << 4) /* master abort */ |
| 438 | #define ICR_SCLE (1 << 5) /* master clock enable */ |
| 439 | #define ICR_IUE (1 << 6) /* unit enable */ |
| 440 | #define ICR_GCD (1 << 7) /* general call disable */ |
| 441 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ |
| 442 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ |
| 443 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ |
| 444 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ |
| 445 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ |
| 446 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ |
| 447 | #define ICR_UR (1 << 14) /* unit reset */ |
| 448 | |
| 449 | #define ISR_RWM (1 << 0) /* read/write mode */ |
| 450 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ |
| 451 | #define ISR_UB (1 << 2) /* unit busy */ |
| 452 | #define ISR_IBB (1 << 3) /* bus busy */ |
| 453 | #define ISR_SSD (1 << 4) /* slave stop detected */ |
| 454 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ |
| 455 | #define ISR_ITE (1 << 6) /* tx buffer empty */ |
| 456 | #define ISR_IRF (1 << 7) /* rx buffer full */ |
| 457 | #define ISR_GCAD (1 << 8) /* general call address detected */ |
| 458 | #define ISR_SAD (1 << 9) /* slave address detected */ |
| 459 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ |
| 460 | |
| 461 | |
| 462 | /* |
| 463 | * Serial Audio Controller |
| 464 | */ |
| 465 | |
| 466 | /* FIXME: This clash with SA1111 defines */ |
| 467 | #ifndef _ASM_ARCH_SA1111 |
| 468 | |
| 469 | #define SACR0 __REG(0x40400000) /* Global Control Register */ |
| 470 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ |
| 471 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ |
| 472 | #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ |
| 473 | #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ |
| 474 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ |
| 475 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ |
| 476 | |
| 477 | #define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ |
| 478 | #define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ |
| 479 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ |
| 480 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ |
| 481 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ |
| 482 | #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ |
| 483 | #define SACR0_ENB (1 << 0) /* Enable I2S Link */ |
| 484 | #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ |
| 485 | #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ |
| 486 | #define SACR1_DREC (1 << 3) /* Disable Recording Function */ |
Marc-Andre Hebert | fd88dd7 | 2006-03-30 10:24:08 +0100 | [diff] [blame] | 487 | #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | |
| 489 | #define SASR0_I2SOFF (1 << 7) /* Controller Status */ |
| 490 | #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ |
| 491 | #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ |
| 492 | #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ |
| 493 | #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ |
| 494 | #define SASR0_BSY (1 << 2) /* I2S Busy */ |
| 495 | #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ |
| 496 | #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ |
| 497 | |
| 498 | #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ |
| 499 | #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ |
| 500 | |
| 501 | #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ |
| 502 | #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ |
| 503 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ |
| 504 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ |
| 505 | |
| 506 | #endif |
| 507 | |
| 508 | /* |
| 509 | * AC97 Controller registers |
| 510 | */ |
| 511 | |
| 512 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ |
| 513 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 514 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 515 | |
| 516 | #define PICR __REG(0x40500004) /* PCM In Control Register */ |
| 517 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 518 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 519 | |
| 520 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ |
| 521 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
| 522 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 523 | |
| 524 | #define GCR __REG(0x4050000C) /* Global Control Register */ |
| 525 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ |
| 526 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ |
| 527 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ |
| 528 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ |
| 529 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ |
| 530 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ |
| 531 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ |
| 532 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ |
| 533 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ |
| 534 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ |
| 535 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ |
| 536 | |
| 537 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ |
| 538 | #define POSR_FIFOE (1 << 4) /* FIFO error */ |
| 539 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ |
| 540 | |
| 541 | #define PISR __REG(0x40500014) /* PCM In Status Register */ |
| 542 | #define PISR_FIFOE (1 << 4) /* FIFO error */ |
| 543 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 544 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ |
| 545 | |
| 546 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ |
| 547 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ |
| 548 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 549 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ |
| 550 | |
| 551 | #define GSR __REG(0x4050001C) /* Global Status Register */ |
| 552 | #define GSR_CDONE (1 << 19) /* Command Done */ |
| 553 | #define GSR_SDONE (1 << 18) /* Status Done */ |
| 554 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ |
| 555 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ |
| 556 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ |
| 557 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ |
| 558 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ |
| 559 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ |
| 560 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ |
| 561 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ |
| 562 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ |
| 563 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ |
| 564 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ |
| 565 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ |
| 566 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ |
| 567 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ |
| 568 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ |
| 569 | |
| 570 | #define CAR __REG(0x40500020) /* CODEC Access Register */ |
| 571 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ |
| 572 | |
| 573 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ |
| 574 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ |
| 575 | |
| 576 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ |
| 577 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ |
| 578 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 579 | |
| 580 | #define MICR __REG(0x40500108) /* Modem In Control Register */ |
| 581 | #define MICR_FEIE (1 << 3) /* FIFO Error */ |
| 582 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
| 583 | |
| 584 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ |
| 585 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ |
| 586 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ |
| 587 | |
| 588 | #define MISR __REG(0x40500118) /* Modem In Status Register */ |
| 589 | #define MISR_FIFOE (1 << 4) /* FIFO error */ |
| 590 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
| 591 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ |
| 592 | |
| 593 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ |
| 594 | |
| 595 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ |
| 596 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ |
| 597 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ |
| 598 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ |
| 599 | |
| 600 | |
| 601 | /* |
| 602 | * USB Device Controller |
| 603 | * PXA25x and PXA27x USB device controller registers are different. |
| 604 | */ |
| 605 | #if defined(CONFIG_PXA25x) |
| 606 | |
| 607 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ |
| 608 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ |
| 609 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ |
| 610 | |
| 611 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ |
| 612 | #define UDCCR_UDE (1 << 0) /* UDC enable */ |
| 613 | #define UDCCR_UDA (1 << 1) /* UDC active */ |
| 614 | #define UDCCR_RSM (1 << 2) /* Device resume */ |
| 615 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ |
| 616 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ |
| 617 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ |
| 618 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ |
| 619 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ |
| 620 | |
| 621 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ |
| 622 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ |
| 623 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ |
| 624 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ |
| 625 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ |
| 626 | #define UDCCS0_SST (1 << 4) /* Sent stall */ |
| 627 | #define UDCCS0_FST (1 << 5) /* Force stall */ |
| 628 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ |
| 629 | #define UDCCS0_SA (1 << 7) /* Setup active */ |
| 630 | |
| 631 | /* Bulk IN - Endpoint 1,6,11 */ |
| 632 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ |
| 633 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ |
| 634 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ |
| 635 | |
| 636 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ |
| 637 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ |
| 638 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ |
| 639 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ |
| 640 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ |
| 641 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ |
| 642 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ |
| 643 | |
| 644 | /* Bulk OUT - Endpoint 2,7,12 */ |
| 645 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ |
| 646 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ |
| 647 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ |
| 648 | |
| 649 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ |
| 650 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ |
| 651 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ |
| 652 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ |
| 653 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ |
| 654 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ |
| 655 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ |
| 656 | |
| 657 | /* Isochronous IN - Endpoint 3,8,13 */ |
| 658 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ |
| 659 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ |
| 660 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ |
| 661 | |
| 662 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ |
| 663 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ |
| 664 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ |
| 665 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ |
| 666 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ |
| 667 | |
| 668 | /* Isochronous OUT - Endpoint 4,9,14 */ |
| 669 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ |
| 670 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ |
| 671 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ |
| 672 | |
| 673 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ |
| 674 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ |
Paul Schulz | d1972ef | 2005-10-18 19:40:32 +0100 | [diff] [blame] | 675 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ |
| 677 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ |
| 678 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ |
| 679 | |
| 680 | /* Interrupt IN - Endpoint 5,10,15 */ |
| 681 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ |
| 682 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ |
| 683 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ |
| 684 | |
| 685 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ |
| 686 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ |
| 687 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ |
| 688 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ |
| 689 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ |
| 690 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ |
| 691 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ |
| 692 | |
| 693 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ |
| 694 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ |
| 695 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ |
| 696 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ |
| 697 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ |
| 698 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ |
| 699 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ |
| 700 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ |
| 701 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ |
| 702 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ |
| 703 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ |
| 704 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ |
| 705 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ |
| 706 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ |
| 707 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ |
| 708 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ |
| 709 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ |
| 710 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ |
| 711 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ |
| 712 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ |
| 713 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ |
| 714 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ |
| 715 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ |
| 716 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ |
| 717 | |
| 718 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ |
| 719 | |
| 720 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ |
| 721 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ |
| 722 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ |
| 723 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ |
| 724 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ |
| 725 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ |
| 726 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ |
| 727 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ |
| 728 | |
| 729 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ |
| 730 | |
| 731 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ |
| 732 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ |
| 733 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ |
| 734 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ |
| 735 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ |
| 736 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ |
| 737 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ |
| 738 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ |
| 739 | |
| 740 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ |
| 741 | |
| 742 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ |
| 743 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ |
| 744 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ |
| 745 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ |
| 746 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ |
| 747 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ |
| 748 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ |
| 749 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ |
| 750 | |
| 751 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ |
| 752 | |
| 753 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ |
| 754 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ |
| 755 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ |
| 756 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ |
| 757 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ |
| 758 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ |
| 759 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ |
| 760 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ |
| 761 | |
| 762 | #elif defined(CONFIG_PXA27x) |
| 763 | |
| 764 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ |
| 765 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ |
| 766 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation |
| 767 | Protocol Port Support */ |
| 768 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol |
| 769 | Support */ |
| 770 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol |
| 771 | Enable */ |
| 772 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ |
| 773 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ |
| 774 | #define UDCCR_ACN_S 11 |
| 775 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ |
| 776 | #define UDCCR_AIN_S 8 |
| 777 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface |
| 778 | Setting Number */ |
| 779 | #define UDCCR_AAISN_S 5 |
| 780 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active |
| 781 | Configuration */ |
| 782 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration |
| 783 | Error */ |
| 784 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ |
| 785 | #define UDCCR_UDA (1 << 1) /* UDC Active */ |
| 786 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ |
| 787 | |
| 788 | #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ |
| 789 | #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ |
| 790 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ |
| 791 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ |
| 792 | |
| 793 | #define UDC_INT_FIFOERROR (0x2) |
| 794 | #define UDC_INT_PACKETCMP (0x1) |
| 795 | |
| 796 | #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) |
| 797 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ |
| 798 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ |
| 799 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ |
| 800 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ |
| 801 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ |
| 802 | |
| 803 | #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ |
| 804 | #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ |
| 805 | #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) |
| 806 | #define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ |
| 807 | #define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ |
| 808 | #define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ |
| 809 | #define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ |
| 810 | #define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ |
| 811 | |
| 812 | |
| 813 | #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ |
| 814 | #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ |
| 815 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ |
| 816 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt |
| 817 | Rising Edge Interrupt Enable */ |
| 818 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt |
| 819 | Falling Edge Interrupt Enable */ |
| 820 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge |
| 821 | Interrupt Enable */ |
| 822 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge |
| 823 | Interrupt Enable */ |
| 824 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge |
| 825 | Interrupt Enable */ |
| 826 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge |
| 827 | Interrupt Enable */ |
| 828 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge |
| 829 | Interrupt Enable */ |
| 830 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge |
| 831 | Interrupt Enable */ |
| 832 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising |
| 833 | Edge Interrupt Enable */ |
| 834 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling |
| 835 | Edge Interrupt Enable */ |
| 836 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge |
| 837 | Interrupt Enable */ |
| 838 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge |
| 839 | Interrupt Enable */ |
| 840 | |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 841 | #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ |
| 842 | |
| 843 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ |
| 844 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ |
| 845 | #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ |
| 846 | #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ |
| 847 | #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ |
| 848 | #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ |
| 849 | #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ |
| 850 | #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ |
| 851 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ |
| 852 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ |
| 853 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ |
| 854 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ |
| 855 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ |
| 856 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ |
| 857 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) |
| 859 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ |
| 860 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ |
| 861 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ |
| 862 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ |
| 863 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ |
| 864 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ |
| 865 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ |
| 866 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ |
| 867 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ |
| 868 | |
| 869 | #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ |
| 870 | #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ |
| 871 | #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ |
| 872 | #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ |
| 873 | #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ |
| 874 | #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ |
| 875 | #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ |
| 876 | #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ |
| 877 | #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ |
| 878 | #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ |
| 879 | #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ |
| 880 | #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ |
| 881 | #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ |
| 882 | #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ |
| 883 | #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ |
| 884 | #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ |
| 885 | #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ |
| 886 | #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ |
| 887 | #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ |
| 888 | #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ |
| 889 | #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ |
| 890 | #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ |
| 891 | #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ |
| 892 | |
| 893 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ |
| 894 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ |
| 895 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ |
| 896 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ |
| 897 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ |
| 898 | #define UDCCSR_FST (1 << 5) /* Force STALL */ |
| 899 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ |
| 900 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ |
| 901 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ |
| 902 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ |
| 903 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ |
| 904 | |
| 905 | #define UDCBCN(x) __REG2(0x40600200, (x)<<2) |
| 906 | #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ |
| 907 | #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ |
| 908 | #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ |
| 909 | #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ |
| 910 | #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ |
| 911 | #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ |
| 912 | #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ |
| 913 | #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ |
| 914 | #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ |
| 915 | #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ |
| 916 | #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ |
| 917 | #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ |
| 918 | #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ |
| 919 | #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ |
| 920 | #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ |
| 921 | #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ |
| 922 | #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ |
| 923 | #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ |
| 924 | #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ |
| 925 | #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ |
| 926 | #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ |
| 927 | #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ |
| 928 | #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ |
| 929 | #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ |
| 930 | |
| 931 | #define UDCDN(x) __REG2(0x40600300, (x)<<2) |
| 932 | #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) |
| 933 | #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) |
| 934 | #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ |
| 935 | #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ |
| 936 | #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ |
| 937 | #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ |
| 938 | #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ |
| 939 | #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ |
| 940 | #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ |
| 941 | #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ |
| 942 | #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ |
| 943 | #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ |
| 944 | #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ |
| 945 | #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ |
| 946 | #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ |
| 947 | #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ |
| 948 | #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ |
| 949 | #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ |
| 950 | #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ |
| 951 | #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ |
| 952 | #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ |
| 953 | #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ |
| 954 | #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ |
| 955 | #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ |
| 956 | #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ |
| 957 | #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ |
| 958 | |
| 959 | #define UDCCN(x) __REG2(0x40600400, (x)<<2) |
| 960 | #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ |
| 961 | #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ |
| 962 | #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ |
| 963 | #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ |
| 964 | #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ |
| 965 | #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ |
| 966 | #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ |
| 967 | #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ |
| 968 | #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ |
| 969 | #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ |
| 970 | #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ |
| 971 | #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ |
| 972 | #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ |
| 973 | #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ |
| 974 | #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ |
| 975 | #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ |
| 976 | #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ |
| 977 | #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ |
| 978 | #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ |
| 979 | #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ |
| 980 | #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ |
| 981 | #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ |
| 982 | #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ |
| 983 | |
| 984 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ |
| 985 | #define UDCCONR_CN_S (25) |
| 986 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ |
| 987 | #define UDCCONR_IN_S (22) |
| 988 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ |
| 989 | #define UDCCONR_AISN_S (19) |
| 990 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ |
| 991 | #define UDCCONR_EN_S (15) |
| 992 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ |
| 993 | #define UDCCONR_ET_S (13) |
| 994 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ |
| 995 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ |
| 996 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ |
| 997 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ |
| 998 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ |
| 999 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ |
| 1000 | #define UDCCONR_MPS_S (2) |
| 1001 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ |
| 1002 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ |
| 1003 | |
| 1004 | |
| 1005 | #define UDC_INT_FIFOERROR (0x2) |
| 1006 | #define UDC_INT_PACKETCMP (0x1) |
| 1007 | |
| 1008 | #define UDC_FNR_MASK (0x7ff) |
| 1009 | |
| 1010 | #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) |
| 1011 | #define UDC_BCR_MASK (0x3ff) |
| 1012 | #endif |
| 1013 | |
| 1014 | /* |
| 1015 | * Fast Infrared Communication Port |
| 1016 | */ |
| 1017 | |
| 1018 | #define FICP __REG(0x40800000) /* Start of FICP area */ |
| 1019 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ |
| 1020 | #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ |
| 1021 | #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ |
| 1022 | #define ICDR __REG(0x4080000c) /* ICP Data Register */ |
| 1023 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ |
| 1024 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ |
| 1025 | |
| 1026 | #define ICCR0_AME (1 << 7) /* Adress match enable */ |
| 1027 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ |
| 1028 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ |
| 1029 | #define ICCR0_RXE (1 << 4) /* Receive enable */ |
| 1030 | #define ICCR0_TXE (1 << 3) /* Transmit enable */ |
| 1031 | #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ |
| 1032 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ |
| 1033 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ |
| 1034 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1035 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ |
| 1036 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ |
| 1037 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ |
| 1038 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ |
| 1039 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ |
| 1040 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1041 | |
| 1042 | #ifdef CONFIG_PXA27x |
| 1043 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ |
| 1044 | #endif |
| 1045 | #define ICSR0_FRE (1 << 5) /* Framing error */ |
| 1046 | #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ |
| 1047 | #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ |
| 1048 | #define ICSR0_RAB (1 << 2) /* Receiver abort */ |
| 1049 | #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ |
| 1050 | #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ |
| 1051 | |
| 1052 | #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ |
| 1053 | #define ICSR1_CRE (1 << 5) /* CRC error */ |
| 1054 | #define ICSR1_EOF (1 << 4) /* End of frame */ |
| 1055 | #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ |
| 1056 | #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ |
| 1057 | #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ |
| 1058 | #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ |
| 1059 | |
| 1060 | |
| 1061 | /* |
| 1062 | * Real Time Clock |
| 1063 | */ |
| 1064 | |
| 1065 | #define RCNR __REG(0x40900000) /* RTC Count Register */ |
| 1066 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ |
| 1067 | #define RTSR __REG(0x40900008) /* RTC Status Register */ |
| 1068 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ |
| 1069 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ |
| 1070 | |
| 1071 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ |
| 1072 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ |
| 1073 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ |
| 1074 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ |
| 1075 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ |
| 1076 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ |
| 1077 | |
| 1078 | |
| 1079 | /* |
| 1080 | * OS Timer & Match Registers |
| 1081 | */ |
| 1082 | |
| 1083 | #define OSMR0 __REG(0x40A00000) /* */ |
| 1084 | #define OSMR1 __REG(0x40A00004) /* */ |
| 1085 | #define OSMR2 __REG(0x40A00008) /* */ |
| 1086 | #define OSMR3 __REG(0x40A0000C) /* */ |
| 1087 | #define OSMR4 __REG(0x40A00080) /* */ |
| 1088 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ |
| 1089 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ |
| 1090 | #define OMCR4 __REG(0x40A000C0) /* */ |
| 1091 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ |
| 1092 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ |
| 1093 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ |
| 1094 | |
| 1095 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ |
| 1096 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ |
| 1097 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ |
| 1098 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ |
| 1099 | |
| 1100 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ |
| 1101 | |
| 1102 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ |
| 1103 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ |
| 1104 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ |
| 1105 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ |
| 1106 | |
| 1107 | |
| 1108 | /* |
| 1109 | * Pulse Width Modulator |
| 1110 | */ |
| 1111 | |
| 1112 | #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ |
| 1113 | #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ |
| 1114 | #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ |
| 1115 | |
| 1116 | #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ |
| 1117 | #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ |
| 1118 | #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ |
| 1119 | |
| 1120 | |
| 1121 | /* |
| 1122 | * Interrupt Controller |
| 1123 | */ |
| 1124 | |
| 1125 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ |
| 1126 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ |
| 1127 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ |
| 1128 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ |
| 1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ |
| 1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ |
| 1131 | |
| 1132 | |
| 1133 | /* |
| 1134 | * General Purpose I/O |
| 1135 | */ |
| 1136 | |
| 1137 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ |
| 1138 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ |
| 1139 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ |
| 1140 | |
| 1141 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ |
| 1142 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ |
| 1143 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ |
| 1144 | |
| 1145 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ |
| 1146 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ |
| 1147 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ |
| 1148 | |
| 1149 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ |
| 1150 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ |
| 1151 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ |
| 1152 | |
| 1153 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ |
| 1154 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ |
| 1155 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ |
| 1156 | |
| 1157 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ |
| 1158 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ |
| 1159 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ |
| 1160 | |
| 1161 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ |
| 1162 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ |
| 1163 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ |
| 1164 | |
| 1165 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ |
| 1166 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ |
| 1167 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ |
| 1168 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ |
| 1169 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ |
| 1170 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ |
| 1171 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ |
| 1172 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ |
| 1173 | |
| 1174 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ |
| 1175 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ |
| 1176 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ |
| 1177 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ |
| 1178 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ |
| 1179 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ |
| 1180 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ |
| 1181 | |
| 1182 | /* More handy macros. The argument is a literal GPIO number. */ |
| 1183 | |
| 1184 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) |
| 1185 | |
| 1186 | #ifdef CONFIG_PXA27x |
| 1187 | |
| 1188 | /* Interrupt Controller */ |
| 1189 | |
| 1190 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
| 1191 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ |
| 1192 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ |
| 1193 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ |
| 1194 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ |
| 1195 | |
| 1196 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
| 1197 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
| 1198 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
| 1199 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) |
| 1200 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) |
| 1201 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) |
| 1202 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) |
| 1203 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) |
| 1204 | |
| 1205 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) |
| 1206 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) |
| 1207 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) |
| 1208 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) |
| 1209 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) |
| 1210 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) |
| 1211 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) |
| 1212 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ |
| 1213 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) |
| 1214 | #else |
| 1215 | |
| 1216 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
| 1217 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
| 1218 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
| 1219 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) |
| 1220 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) |
| 1221 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) |
| 1222 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) |
| 1223 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) |
| 1224 | |
| 1225 | #endif |
| 1226 | |
| 1227 | |
| 1228 | /* GPIO alternate function assignments */ |
| 1229 | |
| 1230 | #define GPIO1_RST 1 /* reset */ |
| 1231 | #define GPIO6_MMCCLK 6 /* MMC Clock */ |
| 1232 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ |
| 1233 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ |
| 1234 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ |
| 1235 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ |
| 1236 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ |
| 1237 | #define GPIO12_32KHz 12 /* 32 kHz out */ |
| 1238 | #define GPIO13_MBGNT 13 /* memory controller grant */ |
| 1239 | #define GPIO14_MBREQ 14 /* alternate bus master request */ |
| 1240 | #define GPIO15_nCS_1 15 /* chip select 1 */ |
| 1241 | #define GPIO16_PWM0 16 /* PWM0 output */ |
| 1242 | #define GPIO17_PWM1 17 /* PWM1 output */ |
| 1243 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ |
| 1244 | #define GPIO19_DREQ1 19 /* External DMA Request */ |
| 1245 | #define GPIO20_DREQ0 20 /* External DMA Request */ |
| 1246 | #define GPIO23_SCLK 23 /* SSP clock */ |
| 1247 | #define GPIO24_SFRM 24 /* SSP Frame */ |
| 1248 | #define GPIO25_STXD 25 /* SSP transmit */ |
| 1249 | #define GPIO26_SRXD 26 /* SSP receive */ |
| 1250 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ |
| 1251 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ |
| 1252 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ |
| 1253 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ |
| 1254 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ |
| 1255 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ |
| 1256 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ |
| 1257 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ |
| 1258 | #define GPIO33_nCS_5 33 /* chip select 5 */ |
| 1259 | #define GPIO34_FFRXD 34 /* FFUART receive */ |
| 1260 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ |
| 1261 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ |
| 1262 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ |
| 1263 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ |
| 1264 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ |
| 1265 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ |
| 1266 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ |
| 1267 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ |
| 1268 | #define GPIO41_FFRTS 41 /* FFUART request to send */ |
| 1269 | #define GPIO42_BTRXD 42 /* BTUART receive data */ |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1270 | #define GPIO42_HWRXD 42 /* HWUART receive data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1272 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1273 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1274 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1275 | #define GPIO45_BTRTS 45 /* BTUART request to send */ |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1276 | #define GPIO45_HWRTS 45 /* HWUART request to send */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1277 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ |
| 1278 | #define GPIO46_ICPRXD 46 /* ICP receive data */ |
| 1279 | #define GPIO46_STRXD 46 /* STD_UART receive data */ |
| 1280 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ |
| 1281 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ |
| 1282 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ |
| 1283 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ |
| 1284 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ |
| 1285 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ |
| 1286 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ |
| 1287 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ |
| 1288 | #define GPIO53_MMCCLK 53 /* MMC Clock */ |
| 1289 | #define GPIO54_MMCCLK 54 /* MMC Clock */ |
| 1290 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ |
| 1291 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ |
| 1292 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ |
| 1293 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ |
| 1294 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ |
| 1295 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ |
| 1296 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ |
| 1297 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ |
| 1298 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ |
| 1299 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ |
| 1300 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ |
| 1301 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ |
| 1302 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ |
| 1303 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ |
| 1304 | #define GPIO66_MBREQ 66 /* alternate bus master req */ |
| 1305 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ |
| 1306 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ |
| 1307 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ |
| 1308 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ |
| 1309 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ |
| 1310 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ |
| 1311 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ |
| 1312 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ |
| 1313 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ |
| 1314 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ |
| 1315 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ |
| 1316 | #define GPIO72_32kHz 72 /* 32 kHz clock */ |
| 1317 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ |
| 1318 | #define GPIO73_MBGNT 73 /* Memory controller grant */ |
| 1319 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ |
| 1320 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ |
| 1321 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ |
| 1322 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ |
| 1323 | #define GPIO78_nCS_2 78 /* chip select 2 */ |
| 1324 | #define GPIO79_nCS_3 79 /* chip select 3 */ |
| 1325 | #define GPIO80_nCS_4 80 /* chip select 4 */ |
| 1326 | #define GPIO81_NSCLK 81 /* NSSP clock */ |
| 1327 | #define GPIO82_NSFRM 82 /* NSSP Frame */ |
| 1328 | #define GPIO83_NSTXD 83 /* NSSP transmit */ |
| 1329 | #define GPIO84_NSRXD 84 /* NSSP receive */ |
| 1330 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ |
| 1331 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ |
Jürgen Schindele | 326764a | 2006-06-29 16:01:43 +0100 | [diff] [blame^] | 1332 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ |
| 1334 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ |
| 1335 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ |
| 1336 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ |
| 1337 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ |
| 1338 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ |
Giorgio Padrin | 57cfa5e | 2005-06-08 19:00:15 +0100 | [diff] [blame] | 1339 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1340 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ |
| 1341 | |
| 1342 | /* GPIO alternate function mode & direction */ |
| 1343 | |
| 1344 | #define GPIO_IN 0x000 |
| 1345 | #define GPIO_OUT 0x080 |
| 1346 | #define GPIO_ALT_FN_1_IN 0x100 |
| 1347 | #define GPIO_ALT_FN_1_OUT 0x180 |
| 1348 | #define GPIO_ALT_FN_2_IN 0x200 |
| 1349 | #define GPIO_ALT_FN_2_OUT 0x280 |
| 1350 | #define GPIO_ALT_FN_3_IN 0x300 |
| 1351 | #define GPIO_ALT_FN_3_OUT 0x380 |
| 1352 | #define GPIO_MD_MASK_NR 0x07f |
| 1353 | #define GPIO_MD_MASK_DIR 0x080 |
| 1354 | #define GPIO_MD_MASK_FN 0x300 |
| 1355 | #define GPIO_DFLT_LOW 0x400 |
| 1356 | #define GPIO_DFLT_HIGH 0x800 |
| 1357 | |
| 1358 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) |
| 1359 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) |
| 1360 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) |
| 1361 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) |
| 1362 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) |
| 1363 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) |
| 1364 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) |
| 1365 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) |
| 1366 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) |
| 1367 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) |
| 1368 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) |
| 1369 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) |
| 1370 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) |
| 1371 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) |
| 1372 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) |
| 1373 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) |
| 1374 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) |
| 1375 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) |
| 1376 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) |
| 1377 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) |
| 1378 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) |
| 1379 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) |
| 1380 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) |
| 1381 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) |
| 1382 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) |
| 1383 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) |
| 1384 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) |
| 1385 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) |
| 1386 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) |
| 1387 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) |
| 1388 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) |
| 1389 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) |
| 1390 | #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT) |
| 1391 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) |
| 1392 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) |
| 1393 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) |
| 1394 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) |
| 1395 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) |
| 1396 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) |
| 1397 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) |
| 1398 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) |
| 1399 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) |
| 1400 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) |
| 1401 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) |
| 1402 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1403 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1404 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1405 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1407 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1409 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) |
| 1411 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) |
| 1412 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) |
| 1413 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) |
| 1414 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) |
| 1415 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1416 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) |
| 1417 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) |
| 1418 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1419 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) |
| 1420 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1421 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) |
| 1422 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1423 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) |
| 1424 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) |
| 1425 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) |
| 1426 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) |
| 1427 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) |
| 1428 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) |
| 1429 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) |
| 1430 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) |
| 1431 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) |
| 1432 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) |
| 1433 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) |
| 1434 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) |
| 1435 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) |
| 1436 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) |
| 1437 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) |
| 1438 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) |
| 1439 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) |
| 1440 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) |
| 1441 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) |
| 1442 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) |
| 1443 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) |
| 1444 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) |
| 1445 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) |
| 1446 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) |
| 1447 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) |
| 1448 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) |
| 1449 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) |
| 1450 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) |
| 1451 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) |
| 1452 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) |
| 1453 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) |
| 1454 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) |
| 1455 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) |
| 1456 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) |
| 1457 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) |
| 1458 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) |
| 1459 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) |
| 1460 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) |
| 1461 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) |
| 1462 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) |
| 1463 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) |
| 1464 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) |
| 1465 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) |
| 1466 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) |
| 1467 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) |
| 1468 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) |
| 1469 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) |
| 1470 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) |
| 1471 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) |
| 1472 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) |
| 1473 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) |
| 1474 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) |
Jürgen Schindele | 326764a | 2006-06-29 16:01:43 +0100 | [diff] [blame^] | 1475 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 1476 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) |
| 1478 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) |
| 1479 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) |
| 1480 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) |
| 1481 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) |
| 1482 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) |
Giorgio Padrin | 57cfa5e | 2005-06-08 19:00:15 +0100 | [diff] [blame] | 1483 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1484 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) |
| 1485 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT) |
| 1486 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) |
| 1487 | |
| 1488 | /* |
| 1489 | * Power Manager |
| 1490 | */ |
| 1491 | |
| 1492 | #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ |
| 1493 | #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ |
| 1494 | #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ |
| 1495 | #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ |
| 1496 | #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ |
| 1497 | #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ |
| 1498 | #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ |
| 1499 | #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ |
| 1500 | #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ |
| 1501 | #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ |
| 1502 | #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ |
| 1503 | #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ |
| 1504 | #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ |
| 1505 | |
| 1506 | #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ |
| 1507 | #define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */ |
| 1508 | #define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */ |
| 1509 | #define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */ |
| 1510 | #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ |
| 1511 | #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ |
| 1512 | #define PCMD(x) __REG2(0x40F00080, (x)<<2) |
| 1513 | #define PCMD0 __REG(0x40F00080 + 0 * 4) |
| 1514 | #define PCMD1 __REG(0x40F00080 + 1 * 4) |
| 1515 | #define PCMD2 __REG(0x40F00080 + 2 * 4) |
| 1516 | #define PCMD3 __REG(0x40F00080 + 3 * 4) |
| 1517 | #define PCMD4 __REG(0x40F00080 + 4 * 4) |
| 1518 | #define PCMD5 __REG(0x40F00080 + 5 * 4) |
| 1519 | #define PCMD6 __REG(0x40F00080 + 6 * 4) |
| 1520 | #define PCMD7 __REG(0x40F00080 + 7 * 4) |
| 1521 | #define PCMD8 __REG(0x40F00080 + 8 * 4) |
| 1522 | #define PCMD9 __REG(0x40F00080 + 9 * 4) |
| 1523 | #define PCMD10 __REG(0x40F00080 + 10 * 4) |
| 1524 | #define PCMD11 __REG(0x40F00080 + 11 * 4) |
| 1525 | #define PCMD12 __REG(0x40F00080 + 12 * 4) |
| 1526 | #define PCMD13 __REG(0x40F00080 + 13 * 4) |
| 1527 | #define PCMD14 __REG(0x40F00080 + 14 * 4) |
| 1528 | #define PCMD15 __REG(0x40F00080 + 15 * 4) |
| 1529 | #define PCMD16 __REG(0x40F00080 + 16 * 4) |
| 1530 | #define PCMD17 __REG(0x40F00080 + 17 * 4) |
| 1531 | #define PCMD18 __REG(0x40F00080 + 18 * 4) |
| 1532 | #define PCMD19 __REG(0x40F00080 + 19 * 4) |
| 1533 | #define PCMD20 __REG(0x40F00080 + 20 * 4) |
| 1534 | #define PCMD21 __REG(0x40F00080 + 21 * 4) |
| 1535 | #define PCMD22 __REG(0x40F00080 + 22 * 4) |
| 1536 | #define PCMD23 __REG(0x40F00080 + 23 * 4) |
| 1537 | #define PCMD24 __REG(0x40F00080 + 24 * 4) |
| 1538 | #define PCMD25 __REG(0x40F00080 + 25 * 4) |
| 1539 | #define PCMD26 __REG(0x40F00080 + 26 * 4) |
| 1540 | #define PCMD27 __REG(0x40F00080 + 27 * 4) |
| 1541 | #define PCMD28 __REG(0x40F00080 + 28 * 4) |
| 1542 | #define PCMD29 __REG(0x40F00080 + 29 * 4) |
| 1543 | #define PCMD30 __REG(0x40F00080 + 30 * 4) |
| 1544 | #define PCMD31 __REG(0x40F00080 + 31 * 4) |
| 1545 | |
| 1546 | #define PCMD_MBC (1<<12) |
| 1547 | #define PCMD_DCE (1<<11) |
| 1548 | #define PCMD_LC (1<<10) |
| 1549 | /* FIXME: PCMD_SQC need be checked. */ |
| 1550 | #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, |
| 1551 | bit 9 should be 0 all day. */ |
| 1552 | #define PVCR_VCSA (0x1<<14) |
| 1553 | #define PVCR_CommandDelay (0xf80) |
| 1554 | #define PCFR_PI2C_EN (0x1 << 6) |
| 1555 | |
| 1556 | #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ |
| 1557 | #define PSSR_RDH (1 << 5) /* Read Disable Hold */ |
| 1558 | #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ |
Todd Poynor | 26705ca | 2005-07-01 11:27:05 +0100 | [diff] [blame] | 1559 | #define PSSR_STS (1 << 3) /* Standby Mode Status */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1560 | #define PSSR_VFS (1 << 2) /* VDD Fault Status */ |
| 1561 | #define PSSR_BFS (1 << 1) /* Battery Fault Status */ |
| 1562 | #define PSSR_SSS (1 << 0) /* Software Sleep Status */ |
| 1563 | |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 1564 | #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ |
| 1565 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1566 | #define PCFR_RO (1 << 15) /* RDH Override */ |
| 1567 | #define PCFR_PO (1 << 14) /* PH Override */ |
| 1568 | #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ |
| 1569 | #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ |
| 1570 | #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ |
| 1571 | #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ |
| 1572 | #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 1573 | #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1574 | #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ |
| 1575 | #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ |
| 1576 | #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ |
| 1577 | #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ |
| 1578 | |
| 1579 | #define RCSR_GPR (1 << 3) /* GPIO Reset */ |
| 1580 | #define RCSR_SMR (1 << 2) /* Sleep Mode */ |
| 1581 | #define RCSR_WDR (1 << 1) /* Watchdog Reset */ |
| 1582 | #define RCSR_HWR (1 << 0) /* Hardware Reset */ |
| 1583 | |
| 1584 | #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ |
| 1585 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ |
| 1586 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ |
| 1587 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ |
| 1588 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ |
| 1589 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ |
| 1590 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ |
| 1591 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ |
| 1592 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ |
| 1593 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ |
| 1594 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ |
| 1595 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ |
| 1596 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ |
| 1597 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ |
| 1598 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ |
| 1599 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ |
| 1600 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ |
| 1601 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ |
| 1602 | |
| 1603 | |
| 1604 | /* |
| 1605 | * SSP Serial Port Registers |
| 1606 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. |
| 1607 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. |
| 1608 | */ |
| 1609 | |
| 1610 | /* Common PXA2xx bits first */ |
| 1611 | #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ |
| 1612 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ |
| 1613 | #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ |
| 1614 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ |
| 1615 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ |
| 1616 | #define SSCR0_National (0x2 << 4) /* National Microwire */ |
| 1617 | #define SSCR0_ECS (1 << 6) /* External clock select */ |
| 1618 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ |
David Vrabel | 68477d1 | 2006-01-18 22:38:44 +0000 | [diff] [blame] | 1619 | #if defined(CONFIG_PXA25x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1620 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ |
| 1621 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ |
David Vrabel | 68477d1 | 2006-01-18 22:38:44 +0000 | [diff] [blame] | 1622 | #elif defined(CONFIG_PXA27x) |
| 1623 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ |
| 1624 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ |
| 1625 | #define SSCR0_EDSS (1 << 20) /* Extended data size select */ |
| 1626 | #define SSCR0_NCS (1 << 21) /* Network clock select */ |
| 1627 | #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ |
| 1628 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ |
| 1629 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ |
Liam Girdwood | c322e24 | 2006-06-20 19:26:42 +0100 | [diff] [blame] | 1630 | #define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */ |
David Vrabel | 68477d1 | 2006-01-18 22:38:44 +0000 | [diff] [blame] | 1631 | #define SSCR0_ADC (1 << 30) /* Audio clock select */ |
| 1632 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ |
| 1633 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1634 | |
| 1635 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ |
| 1636 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ |
| 1637 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ |
| 1638 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ |
| 1639 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ |
| 1640 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ |
| 1641 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ |
| 1642 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ |
| 1643 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ |
| 1644 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ |
| 1645 | |
| 1646 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ |
| 1647 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ |
| 1648 | #define SSSR_BSY (1 << 4) /* SSP Busy */ |
| 1649 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ |
| 1650 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ |
| 1651 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ |
| 1652 | |
| 1653 | #define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ |
| 1654 | #define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ |
| 1655 | #define SSCR0_NCS (1 << 21) /* Network Clock Select */ |
| 1656 | #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ |
| 1657 | |
| 1658 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ |
| 1659 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ |
| 1660 | #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ |
| 1661 | #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ |
| 1662 | #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ |
| 1663 | #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ |
| 1664 | #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ |
| 1665 | #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ |
| 1666 | #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ |
| 1667 | #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ |
| 1668 | #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ |
| 1669 | #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ |
| 1670 | #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ |
| 1671 | #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ |
| 1672 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ |
| 1673 | #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ |
| 1674 | #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ |
| 1675 | #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ |
| 1676 | |
| 1677 | #define SSSR_BCE (1 << 23) /* Bit Count Error */ |
| 1678 | #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ |
| 1679 | #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ |
| 1680 | #define SSSR_EOC (1 << 20) /* End Of Chain */ |
| 1681 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ |
| 1682 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ |
| 1683 | |
| 1684 | #define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */ |
| 1685 | #define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */ |
| 1686 | #define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */ |
| 1687 | #define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */ |
| 1688 | #define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */ |
| 1689 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ |
| 1690 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ |
| 1691 | #define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */ |
| 1692 | |
| 1693 | |
| 1694 | #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ |
| 1695 | #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ |
| 1696 | #define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */ |
| 1697 | #define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */ |
| 1698 | #define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */ |
| 1699 | |
| 1700 | /* Support existing PXA25x drivers */ |
| 1701 | #define SSCR0 SSCR0_P1 /* SSP Control Register 0 */ |
| 1702 | #define SSCR1 SSCR1_P1 /* SSP Control Register 1 */ |
| 1703 | #define SSSR SSSR_P1 /* SSP Status Register */ |
| 1704 | #define SSITR SSITR_P1 /* SSP Interrupt Test Register */ |
| 1705 | #define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ |
| 1706 | |
| 1707 | /* PXA27x ports */ |
| 1708 | #if defined (CONFIG_PXA27x) |
| 1709 | #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */ |
| 1710 | #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */ |
Liam Girdwood | c322e24 | 2006-06-20 19:26:42 +0100 | [diff] [blame] | 1711 | #define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */ |
| 1712 | #define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */ |
| 1713 | #define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */ |
| 1714 | #define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1715 | #define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */ |
| 1716 | #define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */ |
| 1717 | #define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */ |
| 1718 | #define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */ |
| 1719 | #define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */ |
| 1720 | #define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */ |
| 1721 | #define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */ |
Liam Girdwood | c322e24 | 2006-06-20 19:26:42 +0100 | [diff] [blame] | 1722 | #define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */ |
| 1723 | #define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */ |
| 1724 | #define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */ |
| 1725 | #define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1726 | #define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */ |
| 1727 | #define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */ |
| 1728 | #define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */ |
| 1729 | #define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */ |
| 1730 | #define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */ |
| 1731 | #define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */ |
| 1732 | #define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */ |
Liam Girdwood | c322e24 | 2006-06-20 19:26:42 +0100 | [diff] [blame] | 1733 | #define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */ |
| 1734 | #define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */ |
| 1735 | #define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */ |
| 1736 | #define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1737 | #else /* PXA255 (only port 2) and PXA26x ports*/ |
| 1738 | #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */ |
| 1739 | #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */ |
| 1740 | #define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */ |
| 1741 | #define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */ |
| 1742 | #define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */ |
| 1743 | #define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */ |
| 1744 | #define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */ |
| 1745 | #define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */ |
| 1746 | #define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */ |
| 1747 | #define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */ |
| 1748 | #define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */ |
| 1749 | #define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */ |
| 1750 | #define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */ |
| 1751 | #define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */ |
| 1752 | #define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */ |
| 1753 | #define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */ |
| 1754 | #endif |
| 1755 | |
| 1756 | #define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL)) |
| 1757 | #define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL)) |
| 1758 | #define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL)) |
| 1759 | #define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL)) |
| 1760 | #define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL)) |
| 1761 | #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL)) |
| 1762 | #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL)) |
Liam Girdwood | c322e24 | 2006-06-20 19:26:42 +0100 | [diff] [blame] | 1763 | #define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL)) |
| 1764 | #define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL)) |
| 1765 | #define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL)) |
| 1766 | #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1767 | |
| 1768 | /* |
| 1769 | * MultiMediaCard (MMC) controller |
| 1770 | */ |
| 1771 | |
| 1772 | #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ |
| 1773 | #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ |
| 1774 | #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ |
| 1775 | #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ |
| 1776 | #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ |
| 1777 | #define MMC_RESTO __REG(0x41100014) /* Expected response time out */ |
| 1778 | #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ |
| 1779 | #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ |
| 1780 | #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ |
| 1781 | #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ |
| 1782 | #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ |
| 1783 | #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ |
| 1784 | #define MMC_CMD __REG(0x41100030) /* Index of current command */ |
| 1785 | #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ |
| 1786 | #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ |
| 1787 | #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ |
| 1788 | #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ |
| 1789 | #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ |
| 1790 | |
| 1791 | |
| 1792 | /* |
| 1793 | * Core Clock |
| 1794 | */ |
| 1795 | |
| 1796 | #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ |
| 1797 | #define CKEN __REG(0x41300004) /* Clock Enable Register */ |
| 1798 | #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ |
| 1799 | #define CCSR __REG(0x4130000C) /* Core Clock Status Register */ |
| 1800 | |
| 1801 | #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ |
| 1802 | #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ |
| 1803 | #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ |
| 1804 | |
| 1805 | #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ |
| 1806 | #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ |
| 1807 | #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ |
| 1808 | #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ |
| 1809 | #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ |
| 1810 | #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ |
| 1811 | #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ |
| 1812 | #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ |
| 1813 | #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ |
| 1814 | #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ |
| 1815 | #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ |
| 1816 | #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ |
| 1817 | #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ |
| 1818 | #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ |
| 1819 | #define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */ |
| 1820 | #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ |
| 1821 | #define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */ |
| 1822 | #define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */ |
| 1823 | #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ |
| 1824 | #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ |
| 1825 | #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ |
| 1826 | #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ |
Matt Reimer | d9e2964 | 2005-10-28 16:25:02 +0100 | [diff] [blame] | 1827 | #define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1828 | #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ |
| 1829 | #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ |
| 1830 | #define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ |
| 1831 | #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ |
| 1832 | #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ |
| 1833 | #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ |
| 1834 | |
| 1835 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ |
| 1836 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ |
| 1837 | |
| 1838 | |
| 1839 | /* |
| 1840 | * LCD |
| 1841 | */ |
| 1842 | |
| 1843 | #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ |
| 1844 | #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ |
| 1845 | #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ |
| 1846 | #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ |
| 1847 | #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ |
| 1848 | #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ |
| 1849 | #define LCSR __REG(0x44000038) /* LCD Controller Status Register */ |
| 1850 | #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ |
| 1851 | #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ |
| 1852 | #define TMEDCR __REG(0x44000044) /* TMED Control Register */ |
| 1853 | |
| 1854 | #define LCCR3_1BPP (0 << 24) |
| 1855 | #define LCCR3_2BPP (1 << 24) |
| 1856 | #define LCCR3_4BPP (2 << 24) |
| 1857 | #define LCCR3_8BPP (3 << 24) |
| 1858 | #define LCCR3_16BPP (4 << 24) |
| 1859 | |
| 1860 | #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ |
| 1861 | #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ |
| 1862 | #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ |
| 1863 | #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ |
| 1864 | #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ |
| 1865 | #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ |
| 1866 | #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ |
| 1867 | #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ |
| 1868 | |
| 1869 | #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ |
| 1870 | #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ |
| 1871 | #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ |
| 1872 | #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ |
| 1873 | #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */ |
| 1874 | /* Select */ |
| 1875 | #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ |
| 1876 | #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ |
| 1877 | |
| 1878 | #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ |
| 1879 | #define LCCR0_SFM (1 << 4) /* Start of frame mask */ |
| 1880 | #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ |
| 1881 | #define LCCR0_EFM (1 << 6) /* End of Frame mask */ |
| 1882 | #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ |
| 1883 | #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ |
| 1884 | #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ |
| 1885 | #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */ |
| 1886 | /* display mode) */ |
| 1887 | #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ |
| 1888 | /* display */ |
| 1889 | #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ |
| 1890 | /* display */ |
| 1891 | #define LCCR0_DIS (1 << 10) /* LCD Disable */ |
| 1892 | #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ |
| 1893 | #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ |
| 1894 | #define LCCR0_PDD_S 12 |
| 1895 | #define LCCR0_BM (1 << 20) /* Branch mask */ |
| 1896 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 1897 | #define LCCR0_LCDT (1 << 22) /* LCD panel type */ |
| 1898 | #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ |
| 1899 | #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ |
| 1900 | #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ |
| 1901 | #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | |
| 1903 | #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ |
| 1904 | #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ |
| 1905 | (((Pixel) - 1) << FShft (LCCR1_PPL)) |
| 1906 | |
| 1907 | #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ |
| 1908 | #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ |
| 1909 | /* pulse Width [1..64 Tpix] */ \ |
| 1910 | (((Tpix) - 1) << FShft (LCCR1_HSW)) |
| 1911 | |
| 1912 | #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ |
| 1913 | /* count - 1 [Tpix] */ |
| 1914 | #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ |
| 1915 | /* [1..256 Tpix] */ \ |
| 1916 | (((Tpix) - 1) << FShft (LCCR1_ELW)) |
| 1917 | |
| 1918 | #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ |
| 1919 | /* Wait count - 1 [Tpix] */ |
| 1920 | #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ |
| 1921 | /* [1..256 Tpix] */ \ |
| 1922 | (((Tpix) - 1) << FShft (LCCR1_BLW)) |
| 1923 | |
| 1924 | |
| 1925 | #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ |
| 1926 | #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ |
| 1927 | (((Line) - 1) << FShft (LCCR2_LPP)) |
| 1928 | |
| 1929 | #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ |
| 1930 | /* Width - 1 [Tln] (L_FCLK) */ |
| 1931 | #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ |
| 1932 | /* Width [1..64 Tln] */ \ |
| 1933 | (((Tln) - 1) << FShft (LCCR2_VSW)) |
| 1934 | |
| 1935 | #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ |
| 1936 | /* count [Tln] */ |
| 1937 | #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ |
| 1938 | /* [0..255 Tln] */ \ |
| 1939 | ((Tln) << FShft (LCCR2_EFW)) |
| 1940 | |
| 1941 | #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ |
| 1942 | /* Wait count [Tln] */ |
| 1943 | #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ |
| 1944 | /* [0..255 Tln] */ \ |
| 1945 | ((Tln) << FShft (LCCR2_BFW)) |
| 1946 | |
| 1947 | #if 0 |
| 1948 | #define LCCR3_PCD (0xff) /* Pixel clock divisor */ |
| 1949 | #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ |
| 1950 | #define LCCR3_ACB_S 8 |
| 1951 | #endif |
| 1952 | |
| 1953 | #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ |
| 1954 | #define LCCR3_API_S 16 |
| 1955 | #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ |
| 1956 | #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ |
| 1957 | #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ |
| 1958 | #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ |
| 1959 | #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ |
| 1960 | |
| 1961 | #define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */ |
| 1962 | /* active display mode) */ |
| 1963 | #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ |
| 1964 | #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ |
| 1965 | |
| 1966 | #if 0 |
| 1967 | #define LCCR3_BPP (7 << 24) /* bits per pixel */ |
| 1968 | #define LCCR3_BPP_S 24 |
| 1969 | #endif |
| 1970 | #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ |
| 1971 | |
| 1972 | |
| 1973 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ |
| 1974 | #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ |
| 1975 | (((Div) << FShft (LCCR3_PCD))) |
| 1976 | |
| 1977 | |
| 1978 | #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ |
| 1979 | #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ |
| 1980 | (((Bpp) << FShft (LCCR3_BPP))) |
| 1981 | |
| 1982 | #define LCCR3_ACB Fld (8, 8) /* AC Bias */ |
| 1983 | #define LCCR3_Acb(Acb) /* BAC Bias */ \ |
| 1984 | (((Acb) << FShft (LCCR3_ACB))) |
| 1985 | |
| 1986 | #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ |
| 1987 | /* pulse active High */ |
| 1988 | #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ |
| 1989 | |
| 1990 | #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ |
| 1991 | /* active High */ |
| 1992 | #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ |
| 1993 | /* active Low */ |
| 1994 | |
| 1995 | #define LCSR_LDD (1 << 0) /* LCD Disable Done */ |
| 1996 | #define LCSR_SOF (1 << 1) /* Start of frame */ |
| 1997 | #define LCSR_BER (1 << 2) /* Bus error */ |
| 1998 | #define LCSR_ABC (1 << 3) /* AC Bias count */ |
| 1999 | #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ |
| 2000 | #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ |
| 2001 | #define LCSR_OU (1 << 6) /* output FIFO underrun */ |
| 2002 | #define LCSR_QD (1 << 7) /* quick disable */ |
| 2003 | #define LCSR_EOF (1 << 8) /* end of frame */ |
| 2004 | #define LCSR_BS (1 << 9) /* branch status */ |
| 2005 | #define LCSR_SINT (1 << 10) /* subsequent interrupt */ |
| 2006 | |
| 2007 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ |
| 2008 | |
| 2009 | #define LCSR_LDD (1 << 0) /* LCD Disable Done */ |
| 2010 | #define LCSR_SOF (1 << 1) /* Start of frame */ |
| 2011 | #define LCSR_BER (1 << 2) /* Bus error */ |
| 2012 | #define LCSR_ABC (1 << 3) /* AC Bias count */ |
| 2013 | #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ |
| 2014 | #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ |
| 2015 | #define LCSR_OU (1 << 6) /* output FIFO underrun */ |
| 2016 | #define LCSR_QD (1 << 7) /* quick disable */ |
| 2017 | #define LCSR_EOF (1 << 8) /* end of frame */ |
| 2018 | #define LCSR_BS (1 << 9) /* branch status */ |
| 2019 | #define LCSR_SINT (1 << 10) /* subsequent interrupt */ |
| 2020 | |
| 2021 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ |
| 2022 | |
| 2023 | /* |
| 2024 | * Memory controller |
| 2025 | */ |
| 2026 | |
| 2027 | #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ |
| 2028 | #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ |
| 2029 | #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ |
| 2030 | #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ |
| 2031 | #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ |
| 2032 | #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ |
| 2033 | #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ |
| 2034 | #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ |
| 2035 | #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ |
| 2036 | #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ |
| 2037 | #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ |
| 2038 | #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ |
| 2039 | #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ |
| 2040 | #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ |
| 2041 | #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ |
| 2042 | #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ |
| 2043 | #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ |
| 2044 | |
| 2045 | /* |
| 2046 | * More handy macros for PCMCIA |
| 2047 | * |
| 2048 | * Arg is socket number |
| 2049 | */ |
| 2050 | #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ |
| 2051 | #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ |
| 2052 | #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ |
| 2053 | |
| 2054 | /* MECR register defines */ |
| 2055 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ |
| 2056 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ |
| 2057 | |
Todd Poynor | 3e18a45 | 2005-07-01 11:27:06 +0100 | [diff] [blame] | 2058 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2059 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ |
| 2060 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ |
| 2061 | #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ |
| 2062 | #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ |
| 2063 | #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ |
| 2064 | #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ |
| 2065 | #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ |
| 2066 | #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ |
| 2067 | #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ |
| 2068 | #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ |
| 2069 | #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ |
| 2070 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ |
| 2071 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ |
| 2072 | |
| 2073 | |
| 2074 | #ifdef CONFIG_PXA27x |
| 2075 | |
Jared Hulbert | 5b2e98c | 2006-01-05 21:12:26 +0000 | [diff] [blame] | 2076 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ |
| 2077 | |
| 2078 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ |
| 2079 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ |
| 2080 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ |
| 2081 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ |
| 2082 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ |
| 2083 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ |
| 2084 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ |
| 2085 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ |
| 2086 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ |
| 2087 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2088 | /* |
| 2089 | * Keypad |
| 2090 | */ |
| 2091 | #define KPC __REG(0x41500000) /* Keypad Interface Control register */ |
| 2092 | #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ |
| 2093 | #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */ |
| 2094 | #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */ |
| 2095 | #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ |
| 2096 | #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ |
| 2097 | #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ |
| 2098 | #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ |
| 2099 | #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ |
| 2100 | #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ |
| 2101 | |
| 2102 | #define KPC_AS (0x1 << 30) /* Automatic Scan bit */ |
| 2103 | #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ |
| 2104 | #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ |
| 2105 | #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ |
| 2106 | #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ |
| 2107 | #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ |
| 2108 | #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ |
| 2109 | #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ |
| 2110 | #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ |
| 2111 | #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ |
| 2112 | #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ |
| 2113 | #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ |
| 2114 | #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7) |
| 2115 | #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ |
| 2116 | #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ |
| 2117 | #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */ |
| 2118 | #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ |
| 2119 | #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */ |
| 2120 | #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */ |
| 2121 | #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */ |
| 2122 | #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ |
| 2123 | #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ |
| 2124 | |
| 2125 | #define KPDK_DKP (0x1 << 31) |
| 2126 | #define KPDK_DK7 (0x1 << 7) |
| 2127 | #define KPDK_DK6 (0x1 << 6) |
| 2128 | #define KPDK_DK5 (0x1 << 5) |
| 2129 | #define KPDK_DK4 (0x1 << 4) |
| 2130 | #define KPDK_DK3 (0x1 << 3) |
| 2131 | #define KPDK_DK2 (0x1 << 2) |
| 2132 | #define KPDK_DK1 (0x1 << 1) |
| 2133 | #define KPDK_DK0 (0x1 << 0) |
| 2134 | |
| 2135 | #define KPREC_OF1 (0x1 << 31) |
| 2136 | #define kPREC_UF1 (0x1 << 30) |
| 2137 | #define KPREC_OF0 (0x1 << 15) |
| 2138 | #define KPREC_UF0 (0x1 << 14) |
| 2139 | |
| 2140 | #define KPMK_MKP (0x1 << 31) |
| 2141 | #define KPAS_SO (0x1 << 31) |
| 2142 | #define KPASMKPx_SO (0x1 << 31) |
| 2143 | |
| 2144 | /* |
| 2145 | * UHC: USB Host Controller (OHCI-like) register definitions |
| 2146 | */ |
| 2147 | #define UHC_BASE_PHYS (0x4C000000) |
| 2148 | #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */ |
| 2149 | #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */ |
| 2150 | #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */ |
| 2151 | #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */ |
| 2152 | #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */ |
| 2153 | #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */ |
| 2154 | #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */ |
| 2155 | #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */ |
| 2156 | #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */ |
| 2157 | #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */ |
| 2158 | #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */ |
| 2159 | #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */ |
| 2160 | #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */ |
| 2161 | #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */ |
| 2162 | #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */ |
| 2163 | #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ |
| 2164 | #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ |
| 2165 | #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 2166 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2167 | #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ |
Richard Purdie | 3e88a57 | 2005-08-29 22:46:33 +0100 | [diff] [blame] | 2168 | #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ |
| 2169 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2170 | #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ |
| 2171 | #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ |
| 2172 | #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ |
| 2173 | #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */ |
| 2174 | #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */ |
| 2175 | |
| 2176 | #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */ |
| 2177 | #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ |
| 2178 | #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ |
| 2179 | #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ |
| 2180 | #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ |
| 2181 | #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ |
| 2182 | #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ |
| 2183 | #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ |
| 2184 | #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ |
| 2185 | #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ |
| 2186 | |
| 2187 | #define UHCHR __REG(0x4C000064) /* UHC Reset Register */ |
| 2188 | #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ |
| 2189 | #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ |
| 2190 | #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ |
| 2191 | #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ |
| 2192 | #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ |
| 2193 | #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ |
| 2194 | #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ |
| 2195 | #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ |
| 2196 | #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ |
| 2197 | #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ |
| 2198 | #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ |
| 2199 | |
| 2200 | #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/ |
| 2201 | #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ |
| 2202 | #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ |
| 2203 | #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ |
| 2204 | #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ |
| 2205 | #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort |
| 2206 | Interrupt Enable*/ |
| 2207 | #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ |
| 2208 | #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ |
| 2209 | |
| 2210 | #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */ |
| 2211 | |
| 2212 | /* Camera Interface */ |
| 2213 | #define CICR0 __REG(0x50000000) |
| 2214 | #define CICR1 __REG(0x50000004) |
| 2215 | #define CICR2 __REG(0x50000008) |
| 2216 | #define CICR3 __REG(0x5000000C) |
| 2217 | #define CICR4 __REG(0x50000010) |
| 2218 | #define CISR __REG(0x50000014) |
| 2219 | #define CIFR __REG(0x50000018) |
| 2220 | #define CITOR __REG(0x5000001C) |
| 2221 | #define CIBR0 __REG(0x50000028) |
| 2222 | #define CIBR1 __REG(0x50000030) |
| 2223 | #define CIBR2 __REG(0x50000038) |
| 2224 | |
| 2225 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ |
| 2226 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ |
| 2227 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ |
| 2228 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ |
| 2229 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ |
| 2230 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ |
| 2231 | #define CICR0_TOM (1 << 9) /* Time-out mask */ |
| 2232 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ |
| 2233 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ |
| 2234 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ |
| 2235 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ |
| 2236 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ |
| 2237 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ |
| 2238 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ |
| 2239 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ |
| 2240 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ |
| 2241 | |
| 2242 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ |
| 2243 | #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ |
| 2244 | #define CICR1_PPL (0x3f << 15) /* Pixels per line mask */ |
| 2245 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ |
| 2246 | #define CICR1_RGB_F (1 << 11) /* RGB format */ |
| 2247 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ |
| 2248 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ |
| 2249 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ |
| 2250 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ |
| 2251 | #define CICR1_DW (0x7 << 0) /* Data width mask */ |
| 2252 | |
| 2253 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock |
| 2254 | wait count mask */ |
| 2255 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock |
| 2256 | wait count mask */ |
| 2257 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ |
| 2258 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock |
| 2259 | wait count mask */ |
| 2260 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization |
| 2261 | wait count mask */ |
| 2262 | |
| 2263 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock |
| 2264 | wait count mask */ |
| 2265 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock |
| 2266 | wait count mask */ |
| 2267 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ |
| 2268 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock |
| 2269 | wait count mask */ |
| 2270 | #define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */ |
| 2271 | |
| 2272 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ |
| 2273 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ |
| 2274 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ |
| 2275 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ |
| 2276 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ |
| 2277 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ |
| 2278 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ |
| 2279 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ |
| 2280 | |
| 2281 | #define CISR_FTO (1 << 15) /* FIFO time-out */ |
| 2282 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ |
| 2283 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ |
| 2284 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ |
| 2285 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ |
| 2286 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ |
| 2287 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ |
| 2288 | #define CISR_EOL (1 << 8) /* End of line */ |
| 2289 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ |
| 2290 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ |
| 2291 | #define CISR_SOF (1 << 5) /* Start of frame */ |
| 2292 | #define CISR_CDD (1 << 4) /* Camera interface disable done */ |
| 2293 | #define CISR_EOF (1 << 3) /* End of frame */ |
| 2294 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ |
| 2295 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ |
| 2296 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ |
| 2297 | |
| 2298 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ |
| 2299 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ |
| 2300 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ |
| 2301 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ |
| 2302 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ |
| 2303 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ |
| 2304 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ |
| 2305 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ |
| 2306 | |
| 2307 | #define SRAM_SIZE 0x40000 /* 4x64K */ |
| 2308 | |
| 2309 | #define SRAM_MEM_PHYS 0x5C000000 |
| 2310 | |
| 2311 | #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ |
| 2312 | #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ |
| 2313 | |
| 2314 | #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ |
| 2315 | #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ |
| 2316 | #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ |
| 2317 | #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ |
| 2318 | |
| 2319 | #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ |
| 2320 | #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ |
| 2321 | #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ |
| 2322 | #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ |
| 2323 | |
| 2324 | #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ |
| 2325 | #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ |
| 2326 | #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ |
| 2327 | #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ |
| 2328 | |
| 2329 | #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ |
| 2330 | #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ |
| 2331 | #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ |
| 2332 | #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ |
| 2333 | |
| 2334 | #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ |
| 2335 | #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ |
| 2336 | #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ |
| 2337 | #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ |
| 2338 | |
| 2339 | #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ |
| 2340 | |
| 2341 | #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ |
| 2342 | #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ |
| 2343 | #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ |
| 2344 | |
| 2345 | #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ |
| 2346 | #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ |
| 2347 | #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ |
| 2348 | |
| 2349 | #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ |
| 2350 | #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ |
| 2351 | #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ |
| 2352 | |
| 2353 | #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ |
| 2354 | #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ |
| 2355 | #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ |
| 2356 | |
| 2357 | #endif |
| 2358 | |
Todd Poynor | 80a1857 | 2005-10-28 16:25:01 +0100 | [diff] [blame] | 2359 | /* PWRMODE register M field values */ |
| 2360 | |
| 2361 | #define PWRMODE_IDLE 0x1 |
| 2362 | #define PWRMODE_STANDBY 0x2 |
| 2363 | #define PWRMODE_SLEEP 0x3 |
| 2364 | #define PWRMODE_DEEPSLEEP 0x7 |
| 2365 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2366 | #endif |