abeykun | b85a5e3 | 2016-08-24 13:51:40 -0400 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SDE_HW_CATALOG_H |
| 14 | #define _SDE_HW_CATALOG_H |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bug.h> |
| 18 | #include <linux/bitmap.h> |
| 19 | #include <linux/err.h> |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 20 | #include <linux/msm-bus.h> |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 21 | #include <drm/drmP.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 22 | |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 23 | /** |
| 24 | * Max hardware block count: For ex: max 12 SSPP pipes or |
| 25 | * 5 ctl paths. In all cases, it can have max 12 hardware blocks |
| 26 | * based on current design |
| 27 | */ |
| 28 | #define MAX_BLOCKS 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 29 | |
| 30 | #define SDE_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ |
| 31 | ((MINOR & 0xFFF) << 16) |\ |
| 32 | (STEP & 0xFFFF)) |
| 33 | |
| 34 | #define SDE_HW_MAJOR(rev) ((rev) >> 28) |
abeykun | b85a5e3 | 2016-08-24 13:51:40 -0400 | [diff] [blame] | 35 | #define SDE_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 36 | #define SDE_HW_STEP(rev) ((rev) & 0xFFFF) |
| 37 | #define SDE_HW_MAJOR_MINOR(rev) ((rev) >> 16) |
| 38 | |
| 39 | #define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2) \ |
| 40 | (SDE_HW_MAJOR_MINOR((rev1)) == SDE_HW_MAJOR_MINOR((rev2))) |
| 41 | |
| 42 | #define SDE_HW_VER_170 SDE_HW_VER(1, 7, 0) /* 8996 v1.0 */ |
| 43 | #define SDE_HW_VER_171 SDE_HW_VER(1, 7, 1) /* 8996 v2.0 */ |
| 44 | #define SDE_HW_VER_172 SDE_HW_VER(1, 7, 2) /* 8996 v3.0 */ |
| 45 | #define SDE_HW_VER_300 SDE_HW_VER(3, 0, 0) /* 8998 v1.0 */ |
Lloyd Atkinson | 274cc46 | 2017-02-21 11:52:06 -0500 | [diff] [blame] | 46 | #define SDE_HW_VER_301 SDE_HW_VER(3, 0, 1) /* 8998 v1.1 */ |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 47 | #define SDE_HW_VER_400 SDE_HW_VER(4, 0, 0) /* sdm845 v1.0 */ |
abeykun | b85a5e3 | 2016-08-24 13:51:40 -0400 | [diff] [blame] | 48 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 49 | #define IS_SDM845_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_400) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 50 | |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 51 | #define SDE_HW_BLK_NAME_LEN 16 |
| 52 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 53 | #define MAX_IMG_WIDTH 0x3fff |
| 54 | #define MAX_IMG_HEIGHT 0x3fff |
| 55 | |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 56 | #define CRTC_DUAL_MIXERS 2 |
| 57 | |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 58 | #define SDE_COLOR_PROCESS_VER(MAJOR, MINOR) \ |
| 59 | ((((MAJOR) & 0xFFFF) << 16) | (((MINOR) & 0xFFFF))) |
| 60 | #define SDE_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16) |
| 61 | #define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF) |
| 62 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 63 | /** |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 64 | * Supported UBWC feature versions |
| 65 | */ |
| 66 | enum { |
| 67 | SDE_HW_UBWC_VER_10 = 0x100, |
| 68 | SDE_HW_UBWC_VER_20 = 0x200, |
| 69 | SDE_HW_UBWC_VER_30 = 0x300, |
| 70 | }; |
| 71 | |
| 72 | #define IS_UBWC_20_SUPPORTED(rev) ((rev) >= SDE_HW_UBWC_VER_20) |
| 73 | |
| 74 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 75 | * MDP TOP BLOCK features |
| 76 | * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe |
| 77 | * @SDE_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats |
| 78 | * @SDE_MDP_BWC, MDSS HW supports Bandwidth compression. |
| 79 | * @SDE_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth |
| 80 | * compression initial revision |
| 81 | * @SDE_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 |
| 82 | * @SDE_MDP_CDP, Client driven prefetch |
| 83 | * @SDE_MDP_MAX Maximum value |
| 84 | |
| 85 | */ |
| 86 | enum { |
| 87 | SDE_MDP_PANIC_PER_PIPE = 0x1, |
| 88 | SDE_MDP_10BIT_SUPPORT, |
| 89 | SDE_MDP_BWC, |
| 90 | SDE_MDP_UBWC_1_0, |
| 91 | SDE_MDP_UBWC_1_5, |
| 92 | SDE_MDP_CDP, |
| 93 | SDE_MDP_MAX |
| 94 | }; |
| 95 | |
| 96 | /** |
| 97 | * SSPP sub-blocks/features |
| 98 | * @SDE_SSPP_SRC Src and fetch part of the pipes, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 99 | * @SDE_SSPP_SCALER_QSEED2, QSEED2 algorithm support |
| 100 | * @SDE_SSPP_SCALER_QSEED3, QSEED3 alogorithm support |
| 101 | * @SDE_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes |
| 102 | * @SDE_SSPP_CSC, Support of Color space converion |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 103 | * @SDE_SSPP_CSC_10BIT, Support of 10-bit Color space conversion |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 104 | * @SDE_SSPP_HSIC, Global HSIC control |
| 105 | * @SDE_SSPP_MEMCOLOR Memory Color Support |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 106 | * @SDE_SSPP_IGC, Inverse gamma correction |
| 107 | * @SDE_SSPP_PCC, Color correction support |
| 108 | * @SDE_SSPP_CURSOR, SSPP can be used as a cursor layer |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 109 | * @SDE_SSPP_QOS, SSPP support QoS control, danger/safe/creq |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 110 | * @SDE_SSPP_EXCL_RECT, SSPP supports exclusion rect |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 111 | * @SDE_SSPP_SMART_DMA_V1, SmartDMA 1.0 support |
| 112 | * @SDE_SSPP_SMART_DMA_V2, SmartDMA 2.0 support |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 113 | * @SDE_SSPP_MAX maximum value |
| 114 | */ |
| 115 | enum { |
| 116 | SDE_SSPP_SRC = 0x1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 117 | SDE_SSPP_SCALER_QSEED2, |
| 118 | SDE_SSPP_SCALER_QSEED3, |
| 119 | SDE_SSPP_SCALER_RGB, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 120 | SDE_SSPP_CSC, |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 121 | SDE_SSPP_CSC_10BIT, |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 122 | SDE_SSPP_HSIC, |
| 123 | SDE_SSPP_MEMCOLOR, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 124 | SDE_SSPP_IGC, |
| 125 | SDE_SSPP_PCC, |
| 126 | SDE_SSPP_CURSOR, |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 127 | SDE_SSPP_QOS, |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 128 | SDE_SSPP_EXCL_RECT, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 129 | SDE_SSPP_SMART_DMA_V1, |
| 130 | SDE_SSPP_SMART_DMA_V2, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 131 | SDE_SSPP_MAX |
| 132 | }; |
| 133 | |
| 134 | /* |
| 135 | * MIXER sub-blocks/features |
| 136 | * @SDE_MIXER_LAYER Layer mixer layer blend configuration, |
| 137 | * @SDE_MIXER_SOURCESPLIT Layer mixer supports source-split configuration |
| 138 | * @SDE_MIXER_GC Gamma correction block |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 139 | * @SDE_DIM_LAYER Layer mixer supports dim layer |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 140 | * @SDE_MIXER_MAX maximum value |
| 141 | */ |
| 142 | enum { |
| 143 | SDE_MIXER_LAYER = 0x1, |
| 144 | SDE_MIXER_SOURCESPLIT, |
| 145 | SDE_MIXER_GC, |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 146 | SDE_DIM_LAYER, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 147 | SDE_MIXER_MAX |
| 148 | }; |
| 149 | |
| 150 | /** |
| 151 | * DSPP sub-blocks |
| 152 | * @SDE_DSPP_IGC DSPP Inverse gamma correction block |
| 153 | * @SDE_DSPP_PCC Panel color correction block |
| 154 | * @SDE_DSPP_GC Gamma correction block |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 155 | * @SDE_DSPP_HSIC Global HSIC block |
| 156 | * @SDE_DSPP_MEMCOLOR Memory Color block |
| 157 | * @SDE_DSPP_SIXZONE Six zone block |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 158 | * @SDE_DSPP_GAMUT Gamut bloc |
| 159 | * @SDE_DSPP_DITHER Dither block |
Gopikrishnaiah Anandan | b67b0d1 | 2016-06-23 11:43:08 -0700 | [diff] [blame] | 160 | * @SDE_DSPP_HIST Histogram block |
| 161 | * @SDE_DSPP_VLUT PA VLUT block |
| 162 | * @SDE_DSPP_AD AD block |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 163 | * @SDE_DSPP_MAX maximum value |
| 164 | */ |
| 165 | enum { |
| 166 | SDE_DSPP_IGC = 0x1, |
| 167 | SDE_DSPP_PCC, |
| 168 | SDE_DSPP_GC, |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 169 | SDE_DSPP_HSIC, |
| 170 | SDE_DSPP_MEMCOLOR, |
| 171 | SDE_DSPP_SIXZONE, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 172 | SDE_DSPP_GAMUT, |
| 173 | SDE_DSPP_DITHER, |
| 174 | SDE_DSPP_HIST, |
Gopikrishnaiah Anandan | b67b0d1 | 2016-06-23 11:43:08 -0700 | [diff] [blame] | 175 | SDE_DSPP_VLUT, |
Gopikrishnaiah Anandan | 41980b4 | 2016-06-21 16:01:33 -0700 | [diff] [blame] | 176 | SDE_DSPP_AD, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 177 | SDE_DSPP_MAX |
| 178 | }; |
| 179 | |
| 180 | /** |
| 181 | * PINGPONG sub-blocks |
| 182 | * @SDE_PINGPONG_TE Tear check block |
| 183 | * @SDE_PINGPONG_TE2 Additional tear check block for split pipes |
| 184 | * @SDE_PINGPONG_SPLIT PP block supports split fifo |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 185 | * @SDE_PINGPONG_SLAVE PP block is a suitable slave for split fifo |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 186 | * @SDE_PINGPONG_DSC, Display stream compression blocks |
| 187 | * @SDE_PINGPONG_MAX |
| 188 | */ |
| 189 | enum { |
| 190 | SDE_PINGPONG_TE = 0x1, |
| 191 | SDE_PINGPONG_TE2, |
| 192 | SDE_PINGPONG_SPLIT, |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 193 | SDE_PINGPONG_SLAVE, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 194 | SDE_PINGPONG_DSC, |
| 195 | SDE_PINGPONG_MAX |
| 196 | }; |
| 197 | |
| 198 | /** |
Lloyd Atkinson | cf8996b | 2016-08-23 09:34:13 -0400 | [diff] [blame] | 199 | * CTL sub-blocks |
| 200 | * @SDE_CTL_SPLIT_DISPLAY CTL supports video mode split display |
| 201 | * @SDE_CTL_PINGPONG_SPLIT CTL supports pingpong split |
| 202 | * @SDE_CTL_MAX |
| 203 | */ |
| 204 | enum { |
| 205 | SDE_CTL_SPLIT_DISPLAY = 0x1, |
| 206 | SDE_CTL_PINGPONG_SPLIT, |
| 207 | SDE_CTL_MAX |
| 208 | }; |
| 209 | |
| 210 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 211 | * WB sub-blocks and features |
| 212 | * @SDE_WB_LINE_MODE Writeback module supports line/linear mode |
| 213 | * @SDE_WB_BLOCK_MODE Writeback module supports block mode read |
| 214 | * @SDE_WB_ROTATE rotation support,this is available if writeback |
| 215 | * supports block mode read |
| 216 | * @SDE_WB_CSC Writeback color conversion block support |
| 217 | * @SDE_WB_CHROMA_DOWN, Writeback chroma down block, |
| 218 | * @SDE_WB_DOWNSCALE, Writeback integer downscaler, |
| 219 | * @SDE_WB_DITHER, Dither block |
| 220 | * @SDE_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 221 | * @SDE_WB_UBWC, Writeback Universal bandwidth compression |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 222 | * @SDE_WB_YUV_CONFIG Writeback supports output of YUV colorspace |
Alan Kwong | 9ffcd59 | 2016-09-27 07:41:56 -0400 | [diff] [blame] | 223 | * @SDE_WB_PIPE_ALPHA Writeback supports pipe alpha |
abeykun | f1539f7 | 2016-08-24 16:08:03 -0400 | [diff] [blame] | 224 | * @SDE_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in |
| 225 | * the destination image |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 226 | * @SDE_WB_MAX maximum value |
| 227 | */ |
| 228 | enum { |
| 229 | SDE_WB_LINE_MODE = 0x1, |
| 230 | SDE_WB_BLOCK_MODE, |
| 231 | SDE_WB_ROTATE = SDE_WB_BLOCK_MODE, |
| 232 | SDE_WB_CSC, |
| 233 | SDE_WB_CHROMA_DOWN, |
| 234 | SDE_WB_DOWNSCALE, |
| 235 | SDE_WB_DITHER, |
| 236 | SDE_WB_TRAFFIC_SHAPER, |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 237 | SDE_WB_UBWC, |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 238 | SDE_WB_YUV_CONFIG, |
Alan Kwong | 9ffcd59 | 2016-09-27 07:41:56 -0400 | [diff] [blame] | 239 | SDE_WB_PIPE_ALPHA, |
abeykun | f1539f7 | 2016-08-24 16:08:03 -0400 | [diff] [blame] | 240 | SDE_WB_XY_ROI_OFFSET, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 241 | SDE_WB_MAX |
| 242 | }; |
| 243 | |
| 244 | /** |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 245 | * VBIF sub-blocks and features |
| 246 | * @SDE_VBIF_QOS_OTLIM VBIF supports OT Limit |
| 247 | * @SDE_VBIF_MAX maximum value |
| 248 | */ |
| 249 | enum { |
| 250 | SDE_VBIF_QOS_OTLIM = 0x1, |
| 251 | SDE_VBIF_MAX |
| 252 | }; |
| 253 | |
| 254 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 255 | * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 256 | * @name: string name for debug purposes |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 257 | * @id: enum identifying this block |
| 258 | * @base: register base offset to mdss |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 259 | * @len: length of hardware block |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 260 | * @features bit mask identifying sub-blocks/features |
| 261 | */ |
| 262 | #define SDE_HW_BLK_INFO \ |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 263 | char name[SDE_HW_BLK_NAME_LEN]; \ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 264 | u32 id; \ |
| 265 | u32 base; \ |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 266 | u32 len; \ |
| 267 | unsigned long features; \ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 268 | |
| 269 | /** |
| 270 | * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 271 | * @name: string name for debug purposes |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 272 | * @id: enum identifying this sub-block |
| 273 | * @base: offset of this sub-block relative to the block |
| 274 | * offset |
| 275 | * @len register block length of this sub-block |
| 276 | */ |
| 277 | #define SDE_HW_SUBBLK_INFO \ |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 278 | char name[SDE_HW_BLK_NAME_LEN]; \ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 279 | u32 id; \ |
| 280 | u32 base; \ |
| 281 | u32 len |
| 282 | |
| 283 | /** |
| 284 | * struct sde_src_blk: SSPP part of the source pipes |
| 285 | * @info: HW register and features supported by this sub-blk |
| 286 | */ |
| 287 | struct sde_src_blk { |
| 288 | SDE_HW_SUBBLK_INFO; |
| 289 | }; |
| 290 | |
| 291 | /** |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 292 | * struct sde_scaler_blk: Scaler information |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 293 | * @info: HW register and features supported by this sub-blk |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 294 | * @version: qseed block revision |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 295 | */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 296 | struct sde_scaler_blk { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 297 | SDE_HW_SUBBLK_INFO; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 298 | u32 version; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | struct sde_csc_blk { |
| 302 | SDE_HW_SUBBLK_INFO; |
| 303 | }; |
| 304 | |
| 305 | /** |
| 306 | * struct sde_pp_blk : Pixel processing sub-blk information |
| 307 | * @info: HW register and features supported by this sub-blk |
| 308 | * @version: HW Algorithm version |
| 309 | */ |
| 310 | struct sde_pp_blk { |
| 311 | SDE_HW_SUBBLK_INFO; |
| 312 | u32 version; |
| 313 | }; |
| 314 | |
| 315 | /** |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 316 | * struct sde_format_extended - define sde specific pixel format+modifier |
| 317 | * @fourcc_format: Base FOURCC pixel format code |
| 318 | * @modifier: 64-bit drm format modifier, same modifier must be applied to all |
| 319 | * framebuffer planes |
| 320 | */ |
| 321 | struct sde_format_extended { |
| 322 | uint32_t fourcc_format; |
| 323 | uint64_t modifier; |
| 324 | }; |
| 325 | |
| 326 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 327 | * struct sde_sspp_sub_blks : SSPP sub-blocks |
| 328 | * @maxdwnscale: max downscale ratio supported(without DECIMATION) |
| 329 | * @maxupscale: maxupscale ratio supported |
| 330 | * @maxwidth: max pixelwidth supported by this pipe |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 331 | * @danger_lut_linear: LUT to generate danger signals for linear format |
| 332 | * @safe_lut_linear: LUT to generate safe signals for linear format |
| 333 | * @danger_lut_tile: LUT to generate danger signals for tile format |
| 334 | * @safe_lut_tile: LUT to generate safe signals for tile format |
| 335 | * @danger_lut_nrt: LUT to generate danger signals for non-realtime use case |
| 336 | * @safe_lut_nrt: LUT to generate safe signals for non-realtime use case |
| 337 | * @creq_lut_nrt: LUT to generate creq signals for non-realtime use case |
| 338 | * @creq_vblank: creq priority during vertical blanking |
| 339 | * @danger_vblank: danger priority during vertical blanking |
| 340 | * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 341 | * @smart_dma_priority: hw priority of rect1 of multirect pipe |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 342 | * @src_blk: |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 343 | * @scaler_blk: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 344 | * @csc_blk: |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 345 | * @hsic: |
| 346 | * @memcolor: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 347 | * @pcc_blk: |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 348 | * @igc_blk: |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 349 | * @format_list: Pointer to list of supported formats |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 350 | */ |
| 351 | struct sde_sspp_sub_blks { |
| 352 | u32 maxlinewidth; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 353 | u32 danger_lut_linear; |
| 354 | u32 safe_lut_linear; |
| 355 | u32 danger_lut_tile; |
| 356 | u32 safe_lut_tile; |
| 357 | u32 danger_lut_nrt; |
| 358 | u32 safe_lut_nrt; |
| 359 | u32 creq_lut_nrt; |
| 360 | u32 creq_vblank; |
| 361 | u32 danger_vblank; |
| 362 | u32 pixel_ram_size; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 363 | u32 maxdwnscale; |
| 364 | u32 maxupscale; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 365 | u32 maxhdeciexp; /* max decimation is 2^value */ |
| 366 | u32 maxvdeciexp; /* max decimation is 2^value */ |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 367 | u32 smart_dma_priority; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 368 | struct sde_src_blk src_blk; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 369 | struct sde_scaler_blk scaler_blk; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 370 | struct sde_pp_blk csc_blk; |
Benet Clark | 37809e6 | 2016-10-24 10:14:00 -0700 | [diff] [blame] | 371 | struct sde_pp_blk hsic_blk; |
| 372 | struct sde_pp_blk memcolor_blk; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 373 | struct sde_pp_blk pcc_blk; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 374 | struct sde_pp_blk igc_blk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 375 | |
| 376 | const struct sde_format_extended *format_list; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 377 | }; |
| 378 | |
| 379 | /** |
| 380 | * struct sde_lm_sub_blks: information of mixer block |
| 381 | * @maxwidth: Max pixel width supported by this mixer |
| 382 | * @maxblendstages: Max number of blend-stages supported |
| 383 | * @blendstage_base: Blend-stage register base offset |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 384 | * @gc: gamma correction block |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 385 | */ |
| 386 | struct sde_lm_sub_blks { |
| 387 | u32 maxwidth; |
| 388 | u32 maxblendstages; |
| 389 | u32 blendstage_base[MAX_BLOCKS]; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 390 | struct sde_pp_blk gc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | struct sde_dspp_sub_blks { |
| 394 | struct sde_pp_blk igc; |
| 395 | struct sde_pp_blk pcc; |
| 396 | struct sde_pp_blk gc; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 397 | struct sde_pp_blk hsic; |
| 398 | struct sde_pp_blk memcolor; |
| 399 | struct sde_pp_blk sixzone; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 400 | struct sde_pp_blk gamut; |
| 401 | struct sde_pp_blk dither; |
| 402 | struct sde_pp_blk hist; |
Gopikrishnaiah Anandan | 41980b4 | 2016-06-21 16:01:33 -0700 | [diff] [blame] | 403 | struct sde_pp_blk ad; |
Gopikrishnaiah Anandan | b67b0d1 | 2016-06-23 11:43:08 -0700 | [diff] [blame] | 404 | struct sde_pp_blk vlut; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 405 | }; |
| 406 | |
| 407 | struct sde_pingpong_sub_blks { |
| 408 | struct sde_pp_blk te; |
| 409 | struct sde_pp_blk te2; |
| 410 | struct sde_pp_blk dsc; |
| 411 | }; |
| 412 | |
| 413 | struct sde_wb_sub_blocks { |
| 414 | u32 maxlinewidth; |
| 415 | }; |
| 416 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 417 | struct sde_mdss_base_cfg { |
| 418 | SDE_HW_BLK_INFO; |
| 419 | }; |
| 420 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 421 | /** |
| 422 | * sde_clk_ctrl_type - Defines top level clock control signals |
| 423 | */ |
| 424 | enum sde_clk_ctrl_type { |
| 425 | SDE_CLK_CTRL_NONE, |
| 426 | SDE_CLK_CTRL_VIG0, |
| 427 | SDE_CLK_CTRL_VIG1, |
| 428 | SDE_CLK_CTRL_VIG2, |
| 429 | SDE_CLK_CTRL_VIG3, |
| 430 | SDE_CLK_CTRL_VIG4, |
| 431 | SDE_CLK_CTRL_RGB0, |
| 432 | SDE_CLK_CTRL_RGB1, |
| 433 | SDE_CLK_CTRL_RGB2, |
| 434 | SDE_CLK_CTRL_RGB3, |
| 435 | SDE_CLK_CTRL_DMA0, |
| 436 | SDE_CLK_CTRL_DMA1, |
| 437 | SDE_CLK_CTRL_CURSOR0, |
| 438 | SDE_CLK_CTRL_CURSOR1, |
| 439 | SDE_CLK_CTRL_WB0, |
| 440 | SDE_CLK_CTRL_WB1, |
| 441 | SDE_CLK_CTRL_WB2, |
| 442 | SDE_CLK_CTRL_MAX, |
| 443 | }; |
| 444 | |
| 445 | /* struct sde_clk_ctrl_reg : Clock control register |
| 446 | * @reg_off: register offset |
| 447 | * @bit_off: bit offset |
| 448 | */ |
| 449 | struct sde_clk_ctrl_reg { |
| 450 | u32 reg_off; |
| 451 | u32 bit_off; |
| 452 | }; |
| 453 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 454 | /* struct sde_mdp_cfg : MDP TOP-BLK instance info |
| 455 | * @id: index identifying this block |
| 456 | * @base: register base offset to mdss |
| 457 | * @features bit mask identifying sub-blocks/features |
| 458 | * @highest_bank_bit: UBWC parameter |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 459 | * @ubwc_static: ubwc static configuration |
| 460 | * @ubwc_swizzle: ubwc default swizzle setting |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 461 | * @clk_ctrls clock control register definition |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 462 | */ |
| 463 | struct sde_mdp_cfg { |
| 464 | SDE_HW_BLK_INFO; |
| 465 | u32 highest_bank_bit; |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 466 | u32 ubwc_static; |
| 467 | u32 ubwc_swizzle; |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 468 | struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 469 | }; |
| 470 | |
| 471 | /* struct sde_mdp_cfg : MDP TOP-BLK instance info |
| 472 | * @id: index identifying this block |
| 473 | * @base: register base offset to mdss |
| 474 | * @features bit mask identifying sub-blocks/features |
| 475 | */ |
| 476 | struct sde_ctl_cfg { |
| 477 | SDE_HW_BLK_INFO; |
| 478 | }; |
| 479 | |
| 480 | /** |
| 481 | * struct sde_sspp_cfg - information of source pipes |
| 482 | * @id: index identifying this block |
| 483 | * @base register offset of this block |
| 484 | * @features bit mask identifying sub-blocks/features |
Lloyd Atkinson | 350bb41 | 2016-07-06 10:47:29 -0400 | [diff] [blame] | 485 | * @sblk: SSPP sub-blocks information |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 486 | * @xin_id: bus client identifier |
| 487 | * @clk_ctrl clock control identifier |
abeykun | f35ff33 | 2016-12-20 13:06:09 -0500 | [diff] [blame] | 488 | * @type sspp type identifier |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 489 | */ |
| 490 | struct sde_sspp_cfg { |
| 491 | SDE_HW_BLK_INFO; |
| 492 | const struct sde_sspp_sub_blks *sblk; |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 493 | u32 xin_id; |
| 494 | enum sde_clk_ctrl_type clk_ctrl; |
abeykun | f35ff33 | 2016-12-20 13:06:09 -0500 | [diff] [blame] | 495 | u32 type; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | /** |
| 499 | * struct sde_lm_cfg - information of layer mixer blocks |
| 500 | * @id: index identifying this block |
| 501 | * @base register offset of this block |
| 502 | * @features bit mask identifying sub-blocks/features |
Lloyd Atkinson | 350bb41 | 2016-07-06 10:47:29 -0400 | [diff] [blame] | 503 | * @sblk: LM Sub-blocks information |
| 504 | * @dspp: ID of connected DSPP, DSPP_MAX if unsupported |
| 505 | * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported |
| 506 | * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 507 | */ |
| 508 | struct sde_lm_cfg { |
| 509 | SDE_HW_BLK_INFO; |
| 510 | const struct sde_lm_sub_blks *sblk; |
Lloyd Atkinson | 350bb41 | 2016-07-06 10:47:29 -0400 | [diff] [blame] | 511 | u32 dspp; |
| 512 | u32 pingpong; |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 513 | unsigned long lm_pair_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 514 | }; |
| 515 | |
| 516 | /** |
| 517 | * struct sde_dspp_cfg - information of DSPP blocks |
| 518 | * @id enum identifying this block |
| 519 | * @base register offset of this block |
| 520 | * @features bit mask identifying sub-blocks/features |
| 521 | * supported by this block |
| 522 | * @sblk sub-blocks information |
| 523 | */ |
| 524 | struct sde_dspp_cfg { |
| 525 | SDE_HW_BLK_INFO; |
| 526 | const struct sde_dspp_sub_blks *sblk; |
| 527 | }; |
| 528 | |
| 529 | /** |
| 530 | * struct sde_pingpong_cfg - information of PING-PONG blocks |
| 531 | * @id enum identifying this block |
| 532 | * @base register offset of this block |
| 533 | * @features bit mask identifying sub-blocks/features |
| 534 | * @sblk sub-blocks information |
| 535 | */ |
| 536 | struct sde_pingpong_cfg { |
| 537 | SDE_HW_BLK_INFO; |
| 538 | const struct sde_pingpong_sub_blks *sblk; |
| 539 | }; |
| 540 | |
| 541 | /** |
Jeykumar Sankaran | 5c2f070 | 2017-03-09 18:03:15 -0800 | [diff] [blame] | 542 | * struct sde_dsc_cfg - information of DSC blocks |
| 543 | * @id enum identifying this block |
| 544 | * @base register offset of this block |
| 545 | * @features bit mask identifying sub-blocks/features |
| 546 | */ |
| 547 | struct sde_dsc_cfg { |
| 548 | SDE_HW_BLK_INFO; |
| 549 | }; |
| 550 | |
| 551 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 552 | * struct sde_cdm_cfg - information of chroma down blocks |
| 553 | * @id enum identifying this block |
| 554 | * @base register offset of this block |
| 555 | * @features bit mask identifying sub-blocks/features |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 556 | * @intf_connect Bitmask of INTF IDs this CDM can connect to |
| 557 | * @wb_connect: Bitmask of Writeback IDs this CDM can connect to |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 558 | */ |
| 559 | struct sde_cdm_cfg { |
| 560 | SDE_HW_BLK_INFO; |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 561 | unsigned long intf_connect; |
| 562 | unsigned long wb_connect; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 563 | }; |
| 564 | |
| 565 | /** |
| 566 | * struct sde_intf_cfg - information of timing engine blocks |
| 567 | * @id enum identifying this block |
| 568 | * @base register offset of this block |
| 569 | * @features bit mask identifying sub-blocks/features |
| 570 | * @type: Interface type(DSI, DP, HDMI) |
Lloyd Atkinson | 2d4e766 | 2015-11-05 15:52:07 -0500 | [diff] [blame] | 571 | * @controller_id: Controller Instance ID in case of multiple of intf type |
Lloyd Atkinson | f30546e | 2016-06-26 10:08:25 -0400 | [diff] [blame] | 572 | * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 573 | */ |
| 574 | struct sde_intf_cfg { |
| 575 | SDE_HW_BLK_INFO; |
| 576 | u32 type; /* interface type*/ |
Lloyd Atkinson | 2d4e766 | 2015-11-05 15:52:07 -0500 | [diff] [blame] | 577 | u32 controller_id; |
Lloyd Atkinson | f30546e | 2016-06-26 10:08:25 -0400 | [diff] [blame] | 578 | u32 prog_fetch_lines_worst_case; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 579 | }; |
| 580 | |
| 581 | /** |
| 582 | * struct sde_wb_cfg - information of writeback blocks |
| 583 | * @id enum identifying this block |
| 584 | * @base register offset of this block |
| 585 | * @features bit mask identifying sub-blocks/features |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 586 | * @sblk sub-block information |
| 587 | * @format_list: Pointer to list of supported formats |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 588 | * @vbif_idx vbif identifier |
| 589 | * @xin_id client interface identifier |
| 590 | * @clk_ctrl clock control identifier |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 591 | */ |
| 592 | struct sde_wb_cfg { |
| 593 | SDE_HW_BLK_INFO; |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 594 | const struct sde_wb_sub_blocks *sblk; |
| 595 | const struct sde_format_extended *format_list; |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 596 | u32 vbif_idx; |
| 597 | u32 xin_id; |
| 598 | enum sde_clk_ctrl_type clk_ctrl; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 599 | }; |
| 600 | |
| 601 | /** |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 602 | * struct sde_vbif_dynamic_ot_cfg - dynamic OT setting |
| 603 | * @pps pixel per seconds |
| 604 | * @ot_limit OT limit to use up to specified pixel per second |
| 605 | */ |
| 606 | struct sde_vbif_dynamic_ot_cfg { |
| 607 | u64 pps; |
| 608 | u32 ot_limit; |
| 609 | }; |
| 610 | |
| 611 | /** |
| 612 | * struct sde_vbif_dynamic_ot_tbl - dynamic OT setting table |
| 613 | * @count length of cfg |
| 614 | * @cfg pointer to array of configuration settings with |
| 615 | * ascending requirements |
| 616 | */ |
| 617 | struct sde_vbif_dynamic_ot_tbl { |
| 618 | u32 count; |
Alan Kwong | b9d2f6f | 2016-10-12 00:27:07 -0400 | [diff] [blame] | 619 | struct sde_vbif_dynamic_ot_cfg *cfg; |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 620 | }; |
| 621 | |
| 622 | /** |
| 623 | * struct sde_vbif_cfg - information of VBIF blocks |
| 624 | * @id enum identifying this block |
| 625 | * @base register offset of this block |
| 626 | * @features bit mask identifying sub-blocks/features |
| 627 | * @ot_rd_limit default OT read limit |
| 628 | * @ot_wr_limit default OT write limit |
| 629 | * @xin_halt_timeout maximum time (in usec) for xin to halt |
| 630 | * @dynamic_ot_rd_tbl dynamic OT read configuration table |
| 631 | * @dynamic_ot_wr_tbl dynamic OT write configuration table |
| 632 | */ |
| 633 | struct sde_vbif_cfg { |
| 634 | SDE_HW_BLK_INFO; |
| 635 | u32 default_ot_rd_limit; |
| 636 | u32 default_ot_wr_limit; |
| 637 | u32 xin_halt_timeout; |
| 638 | struct sde_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; |
| 639 | struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; |
| 640 | }; |
Gopikrishnaiah Anandan | 031d8ff | 2016-12-15 16:58:45 -0800 | [diff] [blame] | 641 | /** |
| 642 | * struct sde_reg_dma_cfg - information of lut dma blocks |
| 643 | * @id enum identifying this block |
| 644 | * @base register offset of this block |
| 645 | * @features bit mask identifying sub-blocks/features |
| 646 | * @version version of lutdma hw block |
| 647 | * @trigger_sel_off offset to trigger select registers of lutdma |
| 648 | */ |
| 649 | struct sde_reg_dma_cfg { |
| 650 | SDE_HW_BLK_INFO; |
| 651 | u32 version; |
| 652 | u32 trigger_sel_off; |
| 653 | }; |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 654 | |
| 655 | /** |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 656 | * struct sde_perf_cfg - performance control settings |
| 657 | * @max_bw_low low threshold of maximum bandwidth (kbps) |
| 658 | * @max_bw_high high threshold of maximum bandwidth (kbps) |
| 659 | */ |
| 660 | struct sde_perf_cfg { |
| 661 | u32 max_bw_low; |
| 662 | u32 max_bw_high; |
| 663 | }; |
| 664 | |
| 665 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 666 | * struct sde_mdss_cfg - information of MDSS HW |
| 667 | * This is the main catalog data structure representing |
| 668 | * this HW version. Contains number of instances, |
| 669 | * register offsets, capabilities of the all MDSS HW sub-blocks. |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 670 | * |
| 671 | * @max_sspp_linewidth max source pipe line width support. |
| 672 | * @max_mixer_width max layer mixer line width support. |
| 673 | * @max_mixer_blendstages max layer mixer blend stages or |
| 674 | * supported z order |
| 675 | * @max_wb_linewidth max writeback line width support. |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 676 | * @qseed_type qseed2 or qseed3 support. |
Dhaval Patel | 5aad745 | 2017-01-12 09:59:31 -0800 | [diff] [blame] | 677 | * @csc_type csc or csc_10bit support. |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 678 | * @smart_dma_rev Supported version of SmartDMA feature. |
Dhaval Patel | 1964fb9 | 2016-10-13 19:28:08 -0700 | [diff] [blame] | 679 | * @has_src_split source split feature status |
| 680 | * @has_cdp Client driver prefetch feature status |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 681 | * @has_wb_ubwc UBWC feature supported on WB |
| 682 | * @ubwc_version UBWC feature version (0x0 for not supported) |
abeykun | f35ff33 | 2016-12-20 13:06:09 -0500 | [diff] [blame] | 683 | * @dma_formats Supported formats for dma pipe |
| 684 | * @cursor_formats Supported formats for cursor pipe |
| 685 | * @vig_formats Supported formats for vig pipe |
| 686 | * @wb_formats Supported formats for wb |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 687 | */ |
| 688 | struct sde_mdss_cfg { |
| 689 | u32 hwversion; |
| 690 | |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 691 | u32 max_sspp_linewidth; |
| 692 | u32 max_mixer_width; |
| 693 | u32 max_mixer_blendstages; |
| 694 | u32 max_wb_linewidth; |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 695 | u32 qseed_type; |
Dhaval Patel | 5aad745 | 2017-01-12 09:59:31 -0800 | [diff] [blame] | 696 | u32 csc_type; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 697 | u32 smart_dma_rev; |
Dhaval Patel | 1964fb9 | 2016-10-13 19:28:08 -0700 | [diff] [blame] | 698 | bool has_src_split; |
| 699 | bool has_cdp; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 700 | bool has_dim_layer; |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame^] | 701 | bool has_wb_ubwc; |
| 702 | u32 ubwc_version; |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 703 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 704 | u32 mdss_count; |
| 705 | struct sde_mdss_base_cfg mdss[MAX_BLOCKS]; |
| 706 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 707 | u32 mdp_count; |
| 708 | struct sde_mdp_cfg mdp[MAX_BLOCKS]; |
| 709 | |
| 710 | u32 ctl_count; |
| 711 | struct sde_ctl_cfg ctl[MAX_BLOCKS]; |
| 712 | |
| 713 | u32 sspp_count; |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 714 | struct sde_sspp_cfg sspp[MAX_BLOCKS]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 715 | |
| 716 | u32 mixer_count; |
| 717 | struct sde_lm_cfg mixer[MAX_BLOCKS]; |
| 718 | |
| 719 | u32 dspp_count; |
| 720 | struct sde_dspp_cfg dspp[MAX_BLOCKS]; |
| 721 | |
| 722 | u32 pingpong_count; |
| 723 | struct sde_pingpong_cfg pingpong[MAX_BLOCKS]; |
| 724 | |
Jeykumar Sankaran | 5c2f070 | 2017-03-09 18:03:15 -0800 | [diff] [blame] | 725 | u32 dsc_count; |
| 726 | struct sde_dsc_cfg dsc[MAX_BLOCKS]; |
| 727 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 728 | u32 cdm_count; |
| 729 | struct sde_cdm_cfg cdm[MAX_BLOCKS]; |
| 730 | |
| 731 | u32 intf_count; |
| 732 | struct sde_intf_cfg intf[MAX_BLOCKS]; |
| 733 | |
| 734 | u32 wb_count; |
| 735 | struct sde_wb_cfg wb[MAX_BLOCKS]; |
| 736 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 737 | u32 vbif_count; |
| 738 | struct sde_vbif_cfg vbif[MAX_BLOCKS]; |
Gopikrishnaiah Anandan | 031d8ff | 2016-12-15 16:58:45 -0800 | [diff] [blame] | 739 | |
| 740 | u32 reg_dma_count; |
| 741 | struct sde_reg_dma_cfg dma_cfg; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 742 | /* Add additional block data structures here */ |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 743 | |
| 744 | struct sde_perf_cfg perf; |
abeykun | f35ff33 | 2016-12-20 13:06:09 -0500 | [diff] [blame] | 745 | struct sde_format_extended *dma_formats; |
| 746 | struct sde_format_extended *cursor_formats; |
| 747 | struct sde_format_extended *vig_formats; |
| 748 | struct sde_format_extended *wb_formats; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 749 | }; |
| 750 | |
| 751 | struct sde_mdss_hw_cfg_handler { |
| 752 | u32 major; |
| 753 | u32 minor; |
| 754 | struct sde_mdss_cfg* (*cfg_init)(u32); |
| 755 | }; |
| 756 | |
| 757 | /* |
| 758 | * Access Macros |
| 759 | */ |
| 760 | #define BLK_MDP(s) ((s)->mdp) |
| 761 | #define BLK_CTL(s) ((s)->ctl) |
| 762 | #define BLK_VIG(s) ((s)->vig) |
| 763 | #define BLK_RGB(s) ((s)->rgb) |
| 764 | #define BLK_DMA(s) ((s)->dma) |
| 765 | #define BLK_CURSOR(s) ((s)->cursor) |
| 766 | #define BLK_MIXER(s) ((s)->mixer) |
| 767 | #define BLK_DSPP(s) ((s)->dspp) |
| 768 | #define BLK_PINGPONG(s) ((s)->pingpong) |
| 769 | #define BLK_CDM(s) ((s)->cdm) |
| 770 | #define BLK_INTF(s) ((s)->intf) |
| 771 | #define BLK_WB(s) ((s)->wb) |
| 772 | #define BLK_AD(s) ((s)->ad) |
| 773 | |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 774 | /** |
Clarence Ip | 17162b5 | 2016-11-24 17:06:29 -0500 | [diff] [blame] | 775 | * sde_hw_catalog_init - sde hardware catalog init API parses dtsi property |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 776 | * and stores all parsed offset, hardware capabilities in config structure. |
| 777 | * @dev: drm device node. |
| 778 | * @hw_rev: caller needs provide the hardware revision before parsing. |
| 779 | * |
| 780 | * Return: parsed sde config structure |
| 781 | */ |
| 782 | struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 783 | |
Clarence Ip | 17162b5 | 2016-11-24 17:06:29 -0500 | [diff] [blame] | 784 | /** |
| 785 | * sde_hw_catalog_deinit - sde hardware catalog cleanup |
| 786 | * @sde_cfg: pointer returned from init function |
| 787 | */ |
| 788 | void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg); |
| 789 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 790 | /** |
| 791 | * sde_hw_sspp_multirect_enabled - check multirect enabled for the sspp |
| 792 | * @cfg: pointer to sspp cfg |
| 793 | */ |
| 794 | static inline bool sde_hw_sspp_multirect_enabled(const struct sde_sspp_cfg *cfg) |
| 795 | { |
| 796 | return test_bit(SDE_SSPP_SMART_DMA_V1, &cfg->features) || |
| 797 | test_bit(SDE_SSPP_SMART_DMA_V2, &cfg->features); |
| 798 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 799 | #endif /* _SDE_HW_CATALOG_H */ |