Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3/4 - specific DPLL control functions |
| 3 | * |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 6 | * |
| 7 | * Written by Paul Walmsley |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 8 | * Testing and integration fixes by Jouni Högander |
| 9 | * |
| 10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth |
| 11 | * Menon |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 12 | * |
| 13 | * Parts of this code are based on code written by |
| 14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/io.h> |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 28 | #include <linux/bitops.h> |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 29 | #include <linux/clkdev.h> |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include "soc.h" |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 32 | #include "clockdomain.h" |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 33 | #include "clock.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 34 | #include "cm2xxx_3xxx.h" |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 35 | #include "cm-regbits-34xx.h" |
| 36 | |
| 37 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
| 38 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
| 39 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 |
| 40 | |
| 41 | #define MAX_DPLL_WAIT_TRIES 1000000 |
| 42 | |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 43 | /* Private functions */ |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 44 | |
| 45 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 46 | #ifdef CONFIG_COMMON_CLK |
| 47 | static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) |
| 48 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 49 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 50 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 51 | { |
| 52 | const struct dpll_data *dd; |
| 53 | u32 v; |
| 54 | |
| 55 | dd = clk->dpll_data; |
| 56 | |
| 57 | v = __raw_readl(dd->control_reg); |
| 58 | v &= ~dd->enable_mask; |
| 59 | v |= clken_bits << __ffs(dd->enable_mask); |
| 60 | __raw_writel(v, dd->control_reg); |
| 61 | } |
| 62 | |
| 63 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 64 | #ifdef CONFIG_COMMON_CLK |
| 65 | static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) |
| 66 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 67 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 68 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 69 | { |
| 70 | const struct dpll_data *dd; |
| 71 | int i = 0; |
| 72 | int ret = -EINVAL; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 73 | const char *clk_name; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 74 | |
| 75 | dd = clk->dpll_data; |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 76 | #ifdef CONFIG_COMMON_CLK |
| 77 | clk_name = __clk_get_name(clk->hw.clk); |
| 78 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 79 | clk_name = __clk_get_name(clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 80 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 81 | |
| 82 | state <<= __ffs(dd->idlest_mask); |
| 83 | |
| 84 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && |
| 85 | i < MAX_DPLL_WAIT_TRIES) { |
| 86 | i++; |
| 87 | udelay(1); |
| 88 | } |
| 89 | |
| 90 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 91 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 92 | clk_name, (state) ? "locked" : "bypassed"); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 93 | } else { |
| 94 | pr_debug("clock: %s transition to '%s' in %d loops\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 95 | clk_name, (state) ? "locked" : "bypassed", i); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 96 | |
| 97 | ret = 0; |
| 98 | } |
| 99 | |
| 100 | return ret; |
| 101 | } |
| 102 | |
| 103 | /* From 3430 TRM ES2 4.7.6.2 */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 104 | #ifdef CONFIG_COMMON_CLK |
| 105 | static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) |
| 106 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 107 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 108 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 109 | { |
| 110 | unsigned long fint; |
| 111 | u16 f = 0; |
| 112 | |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 113 | fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 114 | |
| 115 | pr_debug("clock: fint is %lu\n", fint); |
| 116 | |
| 117 | if (fint >= 750000 && fint <= 1000000) |
| 118 | f = 0x3; |
| 119 | else if (fint > 1000000 && fint <= 1250000) |
| 120 | f = 0x4; |
| 121 | else if (fint > 1250000 && fint <= 1500000) |
| 122 | f = 0x5; |
| 123 | else if (fint > 1500000 && fint <= 1750000) |
| 124 | f = 0x6; |
| 125 | else if (fint > 1750000 && fint <= 2100000) |
| 126 | f = 0x7; |
| 127 | else if (fint > 7500000 && fint <= 10000000) |
| 128 | f = 0xB; |
| 129 | else if (fint > 10000000 && fint <= 12500000) |
| 130 | f = 0xC; |
| 131 | else if (fint > 12500000 && fint <= 15000000) |
| 132 | f = 0xD; |
| 133 | else if (fint > 15000000 && fint <= 17500000) |
| 134 | f = 0xE; |
| 135 | else if (fint > 17500000 && fint <= 21000000) |
| 136 | f = 0xF; |
| 137 | else |
| 138 | pr_debug("clock: unknown freqsel setting for %d\n", n); |
| 139 | |
| 140 | return f; |
| 141 | } |
| 142 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 143 | /* |
| 144 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness |
| 145 | * @clk: pointer to a DPLL struct clk |
| 146 | * |
| 147 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report |
| 148 | * readiness before returning. Will save and restore the DPLL's |
| 149 | * autoidle state across the enable, per the CDP code. If the DPLL |
| 150 | * locked successfully, return 0; if the DPLL did not lock in the time |
| 151 | * allotted, or DPLL3 was passed in, return -EINVAL. |
| 152 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 153 | #ifdef CONFIG_COMMON_CLK |
| 154 | static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) |
| 155 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 156 | static int _omap3_noncore_dpll_lock(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 157 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 158 | { |
Vikram Pandita | 55ffe16 | 2012-07-04 05:00:44 -0600 | [diff] [blame] | 159 | const struct dpll_data *dd; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 160 | u8 ai; |
Vikram Pandita | 55ffe16 | 2012-07-04 05:00:44 -0600 | [diff] [blame] | 161 | u8 state = 1; |
| 162 | int r = 0; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 163 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 164 | #ifdef CONFIG_COMMON_CLK |
| 165 | pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); |
| 166 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 167 | pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 168 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 169 | |
Vikram Pandita | 55ffe16 | 2012-07-04 05:00:44 -0600 | [diff] [blame] | 170 | dd = clk->dpll_data; |
| 171 | state <<= __ffs(dd->idlest_mask); |
| 172 | |
| 173 | /* Check if already locked */ |
| 174 | if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) |
| 175 | goto done; |
| 176 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 177 | ai = omap3_dpll_autoidle_read(clk); |
| 178 | |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 179 | if (ai) |
| 180 | omap3_dpll_deny_idle(clk); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 181 | |
| 182 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); |
| 183 | |
| 184 | r = _omap3_wait_dpll_status(clk, 1); |
| 185 | |
| 186 | if (ai) |
| 187 | omap3_dpll_allow_idle(clk); |
| 188 | |
Vikram Pandita | 55ffe16 | 2012-07-04 05:00:44 -0600 | [diff] [blame] | 189 | done: |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 190 | return r; |
| 191 | } |
| 192 | |
| 193 | /* |
| 194 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness |
| 195 | * @clk: pointer to a DPLL struct clk |
| 196 | * |
| 197 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In |
| 198 | * bypass mode, the DPLL's rate is set equal to its parent clock's |
| 199 | * rate. Waits for the DPLL to report readiness before returning. |
| 200 | * Will save and restore the DPLL's autoidle state across the enable, |
| 201 | * per the CDP code. If the DPLL entered bypass mode successfully, |
| 202 | * return 0; if the DPLL did not enter bypass in the time allotted, or |
| 203 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, |
| 204 | * return -EINVAL. |
| 205 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 206 | #ifdef CONFIG_COMMON_CLK |
| 207 | static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) |
| 208 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 209 | static int _omap3_noncore_dpll_bypass(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 210 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 211 | { |
| 212 | int r; |
| 213 | u8 ai; |
| 214 | |
| 215 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) |
| 216 | return -EINVAL; |
| 217 | |
| 218 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 219 | #ifdef CONFIG_COMMON_CLK |
| 220 | __clk_get_name(clk->hw.clk)); |
| 221 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 222 | __clk_get_name(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 223 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 224 | |
| 225 | ai = omap3_dpll_autoidle_read(clk); |
| 226 | |
| 227 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); |
| 228 | |
| 229 | r = _omap3_wait_dpll_status(clk, 0); |
| 230 | |
| 231 | if (ai) |
| 232 | omap3_dpll_allow_idle(clk); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 233 | |
| 234 | return r; |
| 235 | } |
| 236 | |
| 237 | /* |
| 238 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop |
| 239 | * @clk: pointer to a DPLL struct clk |
| 240 | * |
| 241 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and |
| 242 | * restore the DPLL's autoidle state across the stop, per the CDP |
| 243 | * code. If DPLL3 was passed in, or the DPLL does not support |
| 244 | * low-power stop, return -EINVAL; otherwise, return 0. |
| 245 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 246 | #ifdef CONFIG_COMMON_CLK |
| 247 | static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) |
| 248 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 249 | static int _omap3_noncore_dpll_stop(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 250 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 251 | { |
| 252 | u8 ai; |
| 253 | |
| 254 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) |
| 255 | return -EINVAL; |
| 256 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 257 | #ifdef CONFIG_COMMON_CLK |
| 258 | pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); |
| 259 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 260 | pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 261 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 262 | |
| 263 | ai = omap3_dpll_autoidle_read(clk); |
| 264 | |
| 265 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); |
| 266 | |
| 267 | if (ai) |
| 268 | omap3_dpll_allow_idle(clk); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 273 | /** |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 274 | * _lookup_dco - Lookup DCO used by j-type DPLL |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 275 | * @clk: pointer to a DPLL struct clk |
| 276 | * @dco: digital control oscillator selector |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 277 | * @m: DPLL multiplier to set |
| 278 | * @n: DPLL divider to set |
| 279 | * |
| 280 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" |
| 281 | * |
| 282 | * XXX This code is not needed for 3430/AM35xx; can it be optimized |
| 283 | * out in non-multi-OMAP builds for those chips? |
| 284 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 285 | #ifdef CONFIG_COMMON_CLK |
| 286 | static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) |
| 287 | #else |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 288 | static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 289 | #endif |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 290 | { |
| 291 | unsigned long fint, clkinp; /* watch out for overflow */ |
| 292 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 293 | #ifdef CONFIG_COMMON_CLK |
| 294 | clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); |
| 295 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 296 | clkinp = __clk_get_rate(__clk_get_parent(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 297 | #endif |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 298 | fint = (clkinp / n) * m; |
| 299 | |
| 300 | if (fint < 1000000000) |
| 301 | *dco = 2; |
| 302 | else |
| 303 | *dco = 4; |
| 304 | } |
| 305 | |
| 306 | /** |
| 307 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL |
| 308 | * @clk: pointer to a DPLL struct clk |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 309 | * @sd_div: target sigma-delta divider |
| 310 | * @m: DPLL multiplier to set |
| 311 | * @n: DPLL divider to set |
| 312 | * |
| 313 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" |
| 314 | * |
| 315 | * XXX This code is not needed for 3430/AM35xx; can it be optimized |
| 316 | * out in non-multi-OMAP builds for those chips? |
| 317 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 318 | #ifdef CONFIG_COMMON_CLK |
| 319 | static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) |
| 320 | #else |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 321 | static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 322 | #endif |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 323 | { |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 324 | unsigned long clkinp, sd; /* watch out for overflow */ |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 325 | int mod1, mod2; |
| 326 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 327 | #ifdef CONFIG_COMMON_CLK |
| 328 | clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); |
| 329 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 330 | clkinp = __clk_get_rate(__clk_get_parent(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 331 | #endif |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 332 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 333 | /* |
| 334 | * target sigma-delta to near 250MHz |
| 335 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] |
| 336 | */ |
| 337 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ |
| 338 | mod1 = (clkinp * m) % (250 * n); |
| 339 | sd = (clkinp * m) / (250 * n); |
| 340 | mod2 = sd % 10; |
| 341 | sd /= 10; |
| 342 | |
| 343 | if (mod1 || mod2) |
| 344 | sd++; |
| 345 | *sd_div = sd; |
| 346 | } |
| 347 | |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 348 | /* |
| 349 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly |
| 350 | * @clk: struct clk * of DPLL to set |
| 351 | * @m: DPLL multiplier to set |
| 352 | * @n: DPLL divider to set |
| 353 | * @freqsel: FREQSEL value to set |
| 354 | * |
| 355 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to |
| 356 | * lock.. Returns -EINVAL upon error, or 0 upon success. |
| 357 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 358 | #ifdef CONFIG_COMMON_CLK |
| 359 | static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, |
| 360 | u16 freqsel) |
| 361 | #else |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 362 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 363 | #endif |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 364 | { |
| 365 | struct dpll_data *dd = clk->dpll_data; |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 366 | u8 dco, sd_div; |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 367 | u32 v; |
| 368 | |
| 369 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ |
| 370 | _omap3_noncore_dpll_bypass(clk); |
| 371 | |
Vishwanath BS | 5eb75f5 | 2010-02-24 12:05:57 -0700 | [diff] [blame] | 372 | /* |
| 373 | * Set jitter correction. No jitter correction for OMAP4 and 3630 |
| 374 | * since freqsel field is no longer present |
| 375 | */ |
Vaibhav Hiremath | 78da264 | 2012-08-24 20:24:24 +0530 | [diff] [blame] | 376 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 377 | v = __raw_readl(dd->control_reg); |
| 378 | v &= ~dd->freqsel_mask; |
| 379 | v |= freqsel << __ffs(dd->freqsel_mask); |
| 380 | __raw_writel(v, dd->control_reg); |
| 381 | } |
| 382 | |
| 383 | /* Set DPLL multiplier, divider */ |
| 384 | v = __raw_readl(dd->mult_div1_reg); |
| 385 | v &= ~(dd->mult_mask | dd->div1_mask); |
| 386 | v |= m << __ffs(dd->mult_mask); |
| 387 | v |= (n - 1) << __ffs(dd->div1_mask); |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 388 | |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 389 | /* Configure dco and sd_div for dplls that have these fields */ |
| 390 | if (dd->dco_mask) { |
| 391 | _lookup_dco(clk, &dco, m, n); |
| 392 | v &= ~(dd->dco_mask); |
| 393 | v |= dco << __ffs(dd->dco_mask); |
| 394 | } |
| 395 | if (dd->sddiv_mask) { |
| 396 | _lookup_sddiv(clk, &sd_div, m, n); |
| 397 | v &= ~(dd->sddiv_mask); |
| 398 | v |= sd_div << __ffs(dd->sddiv_mask); |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 399 | } |
| 400 | |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 401 | __raw_writel(v, dd->mult_div1_reg); |
| 402 | |
| 403 | /* We let the clock framework set the other output dividers later */ |
| 404 | |
| 405 | /* REVISIT: Set ramp-up delay? */ |
| 406 | |
| 407 | _omap3_noncore_dpll_lock(clk); |
| 408 | |
| 409 | return 0; |
| 410 | } |
| 411 | |
| 412 | /* Public functions */ |
| 413 | |
| 414 | /** |
| 415 | * omap3_dpll_recalc - recalculate DPLL rate |
| 416 | * @clk: DPLL struct clk |
| 417 | * |
| 418 | * Recalculate and propagate the DPLL rate. |
| 419 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 420 | #ifdef CONFIG_COMMON_CLK |
| 421 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) |
| 422 | { |
| 423 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
| 424 | #else |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 425 | unsigned long omap3_dpll_recalc(struct clk *clk) |
| 426 | { |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 427 | #endif |
Paul Walmsley | 60c3f65 | 2010-01-26 20:13:11 -0700 | [diff] [blame] | 428 | return omap2_get_dpll_rate(clk); |
| 429 | } |
| 430 | |
| 431 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ |
| 432 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 433 | /** |
| 434 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode |
| 435 | * @clk: pointer to a DPLL struct clk |
| 436 | * |
| 437 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. |
| 438 | * The choice of modes depends on the DPLL's programmed rate: if it is |
| 439 | * the same as the DPLL's parent clock, it will enter bypass; |
| 440 | * otherwise, it will enter lock. This code will wait for the DPLL to |
| 441 | * indicate readiness before returning, unless the DPLL takes too long |
| 442 | * to enter the target state. Intended to be used as the struct clk's |
| 443 | * enable function. If DPLL3 was passed in, or the DPLL does not |
| 444 | * support low-power stop, or if the DPLL took too long to enter |
| 445 | * bypass or lock, return -EINVAL; otherwise, return 0. |
| 446 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 447 | #ifdef CONFIG_COMMON_CLK |
| 448 | int omap3_noncore_dpll_enable(struct clk_hw *hw) |
| 449 | { |
| 450 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
| 451 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 452 | int omap3_noncore_dpll_enable(struct clk *clk) |
| 453 | { |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 454 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 455 | int r; |
| 456 | struct dpll_data *dd; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 457 | struct clk *parent; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 458 | |
| 459 | dd = clk->dpll_data; |
| 460 | if (!dd) |
| 461 | return -EINVAL; |
| 462 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 463 | #ifdef CONFIG_COMMON_CLK |
| 464 | if (clk->clkdm) { |
| 465 | r = clkdm_clk_enable(clk->clkdm, hw->clk); |
| 466 | if (r) { |
| 467 | WARN(1, |
| 468 | "%s: could not enable %s's clockdomain %s: %d\n", |
| 469 | __func__, __clk_get_name(hw->clk), |
| 470 | clk->clkdm->name, r); |
| 471 | return r; |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | parent = __clk_get_parent(hw->clk); |
| 476 | |
| 477 | if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { |
| 478 | #else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 479 | parent = __clk_get_parent(clk); |
| 480 | |
| 481 | if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 482 | #endif |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 483 | WARN_ON(parent != dd->clk_bypass); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 484 | r = _omap3_noncore_dpll_bypass(clk); |
| 485 | } else { |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 486 | WARN_ON(parent != dd->clk_ref); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 487 | r = _omap3_noncore_dpll_lock(clk); |
| 488 | } |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 489 | |
| 490 | #ifndef CONFIG_COMMON_CLK |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 491 | /* |
| 492 | *FIXME: this is dubious - if clk->rate has changed, what about |
| 493 | * propagating? |
| 494 | */ |
| 495 | if (!r) |
Jon Hunter | 49642ac | 2011-10-07 00:53:01 -0600 | [diff] [blame] | 496 | clk->rate = (clk->recalc) ? clk->recalc(clk) : |
| 497 | omap2_get_dpll_rate(clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 498 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 499 | |
| 500 | return r; |
| 501 | } |
| 502 | |
| 503 | /** |
| 504 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop |
| 505 | * @clk: pointer to a DPLL struct clk |
| 506 | * |
| 507 | * Instructs a non-CORE DPLL to enter low-power stop. This function is |
| 508 | * intended for use in struct clkops. No return value. |
| 509 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 510 | #ifdef CONFIG_COMMON_CLK |
| 511 | void omap3_noncore_dpll_disable(struct clk_hw *hw) |
| 512 | { |
| 513 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
| 514 | |
| 515 | _omap3_noncore_dpll_stop(clk); |
| 516 | if (clk->clkdm) |
| 517 | clkdm_clk_disable(clk->clkdm, hw->clk); |
| 518 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 519 | void omap3_noncore_dpll_disable(struct clk *clk) |
| 520 | { |
| 521 | _omap3_noncore_dpll_stop(clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 522 | if (clk->clkdm) |
| 523 | clkdm_clk_disable(clk->clkdm, clk); |
| 524 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 525 | } |
| 526 | |
| 527 | |
| 528 | /* Non-CORE DPLL rate set code */ |
| 529 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 530 | /** |
| 531 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate |
| 532 | * @clk: struct clk * of DPLL to set |
| 533 | * @rate: rounded target rate |
| 534 | * |
| 535 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter |
| 536 | * low-power bypass, and the target rate is the bypass source clock |
| 537 | * rate, then configure the DPLL for bypass. Otherwise, round the |
| 538 | * target rate if it hasn't been done already, then program and lock |
| 539 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. |
| 540 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 541 | #ifdef CONFIG_COMMON_CLK |
| 542 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, |
| 543 | unsigned long parent_rate) |
| 544 | { |
| 545 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
| 546 | struct clk *new_parent = NULL; |
| 547 | u16 freqsel = 0; |
| 548 | struct dpll_data *dd; |
| 549 | int ret; |
| 550 | |
| 551 | if (!hw || !rate) |
| 552 | return -EINVAL; |
| 553 | |
| 554 | dd = clk->dpll_data; |
| 555 | if (!dd) |
| 556 | return -EINVAL; |
| 557 | |
| 558 | __clk_prepare(dd->clk_bypass); |
| 559 | clk_enable(dd->clk_bypass); |
| 560 | __clk_prepare(dd->clk_ref); |
| 561 | clk_enable(dd->clk_ref); |
| 562 | |
| 563 | if (__clk_get_rate(dd->clk_bypass) == rate && |
| 564 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
| 565 | pr_debug("%s: %s: set rate: entering bypass.\n", |
| 566 | __func__, __clk_get_name(hw->clk)); |
| 567 | |
| 568 | ret = _omap3_noncore_dpll_bypass(clk); |
| 569 | if (!ret) |
| 570 | new_parent = dd->clk_bypass; |
| 571 | } else { |
| 572 | if (dd->last_rounded_rate != rate) |
| 573 | rate = __clk_round_rate(hw->clk, rate); |
| 574 | |
| 575 | if (dd->last_rounded_rate == 0) |
| 576 | return -EINVAL; |
| 577 | |
| 578 | /* No freqsel on OMAP4 and OMAP3630 */ |
| 579 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { |
| 580 | freqsel = _omap3_dpll_compute_freqsel(clk, |
| 581 | dd->last_rounded_n); |
| 582 | if (!freqsel) |
| 583 | WARN_ON(1); |
| 584 | } |
| 585 | |
| 586 | pr_debug("%s: %s: set rate: locking rate to %lu.\n", |
| 587 | __func__, __clk_get_name(hw->clk), rate); |
| 588 | |
| 589 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, |
| 590 | dd->last_rounded_n, freqsel); |
| 591 | if (!ret) |
| 592 | new_parent = dd->clk_ref; |
| 593 | } |
| 594 | /* |
| 595 | * FIXME - this is all wrong. common code handles reparenting and |
| 596 | * migrating prepare/enable counts. dplls should be a multiplexer |
| 597 | * clock and this should be a set_parent operation so that all of that |
| 598 | * stuff is inherited for free |
| 599 | */ |
| 600 | |
| 601 | if (!ret) |
| 602 | __clk_reparent(hw->clk, new_parent); |
| 603 | |
| 604 | clk_disable(dd->clk_ref); |
| 605 | __clk_unprepare(dd->clk_ref); |
| 606 | clk_disable(dd->clk_bypass); |
| 607 | __clk_unprepare(dd->clk_bypass); |
| 608 | |
| 609 | return 0; |
| 610 | } |
| 611 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 612 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) |
| 613 | { |
| 614 | struct clk *new_parent = NULL; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 615 | unsigned long hw_rate, bypass_rate; |
Rajendra Nayak | 16975a7 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 616 | u16 freqsel = 0; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 617 | struct dpll_data *dd; |
| 618 | int ret; |
| 619 | |
| 620 | if (!clk || !rate) |
| 621 | return -EINVAL; |
| 622 | |
| 623 | dd = clk->dpll_data; |
| 624 | if (!dd) |
| 625 | return -EINVAL; |
| 626 | |
Jon Hunter | 49642ac | 2011-10-07 00:53:01 -0600 | [diff] [blame] | 627 | hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); |
| 628 | if (rate == hw_rate) |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 629 | return 0; |
| 630 | |
| 631 | /* |
| 632 | * Ensure both the bypass and ref clocks are enabled prior to |
| 633 | * doing anything; we need the bypass clock running to reprogram |
| 634 | * the DPLL. |
| 635 | */ |
| 636 | omap2_clk_enable(dd->clk_bypass); |
| 637 | omap2_clk_enable(dd->clk_ref); |
| 638 | |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 639 | bypass_rate = __clk_get_rate(dd->clk_bypass); |
| 640 | if (bypass_rate == rate && |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 641 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
| 642 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); |
| 643 | |
| 644 | ret = _omap3_noncore_dpll_bypass(clk); |
| 645 | if (!ret) |
| 646 | new_parent = dd->clk_bypass; |
| 647 | } else { |
| 648 | if (dd->last_rounded_rate != rate) |
Mike Turquette | 273a1ce | 2011-10-07 00:53:00 -0600 | [diff] [blame] | 649 | rate = clk->round_rate(clk, rate); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 650 | |
| 651 | if (dd->last_rounded_rate == 0) |
| 652 | return -EINVAL; |
| 653 | |
Vishwanath BS | 5eb75f5 | 2010-02-24 12:05:57 -0700 | [diff] [blame] | 654 | /* No freqsel on OMAP4 and OMAP3630 */ |
Vaibhav Hiremath | 78da264 | 2012-08-24 20:24:24 +0530 | [diff] [blame] | 655 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { |
Rajendra Nayak | 16975a7 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 656 | freqsel = _omap3_dpll_compute_freqsel(clk, |
| 657 | dd->last_rounded_n); |
| 658 | if (!freqsel) |
| 659 | WARN_ON(1); |
| 660 | } |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 661 | |
| 662 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 663 | __clk_get_name(clk), rate); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 664 | |
| 665 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, |
| 666 | dd->last_rounded_n, freqsel); |
| 667 | if (!ret) |
| 668 | new_parent = dd->clk_ref; |
| 669 | } |
| 670 | if (!ret) { |
| 671 | /* |
Uwe Kleine-König | 732bee7 | 2010-06-11 12:16:59 +0200 | [diff] [blame] | 672 | * Switch the parent clock in the hierarchy, and make sure |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 673 | * that the new parent's usecount is correct. Note: we |
| 674 | * enable the new parent before disabling the old to avoid |
| 675 | * any unnecessary hardware disable->enable transitions. |
| 676 | */ |
| 677 | if (clk->usecount) { |
| 678 | omap2_clk_enable(new_parent); |
| 679 | omap2_clk_disable(clk->parent); |
| 680 | } |
| 681 | clk_reparent(clk, new_parent); |
| 682 | clk->rate = rate; |
| 683 | } |
| 684 | omap2_clk_disable(dd->clk_ref); |
| 685 | omap2_clk_disable(dd->clk_bypass); |
| 686 | |
| 687 | return 0; |
| 688 | } |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 689 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 690 | |
| 691 | /* DPLL autoidle read/set code */ |
| 692 | |
| 693 | /** |
| 694 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits |
| 695 | * @clk: struct clk * of the DPLL to read |
| 696 | * |
| 697 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns |
| 698 | * -EINVAL if passed a null pointer or if the struct clk does not |
| 699 | * appear to refer to a DPLL. |
| 700 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 701 | #ifdef CONFIG_COMMON_CLK |
| 702 | u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) |
| 703 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 704 | u32 omap3_dpll_autoidle_read(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 705 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 706 | { |
| 707 | const struct dpll_data *dd; |
| 708 | u32 v; |
| 709 | |
| 710 | if (!clk || !clk->dpll_data) |
| 711 | return -EINVAL; |
| 712 | |
| 713 | dd = clk->dpll_data; |
| 714 | |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 715 | if (!dd->autoidle_reg) |
| 716 | return -EINVAL; |
| 717 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 718 | v = __raw_readl(dd->autoidle_reg); |
| 719 | v &= dd->autoidle_mask; |
| 720 | v >>= __ffs(dd->autoidle_mask); |
| 721 | |
| 722 | return v; |
| 723 | } |
| 724 | |
| 725 | /** |
| 726 | * omap3_dpll_allow_idle - enable DPLL autoidle bits |
| 727 | * @clk: struct clk * of the DPLL to operate on |
| 728 | * |
| 729 | * Enable DPLL automatic idle control. This automatic idle mode |
| 730 | * switching takes effect only when the DPLL is locked, at least on |
| 731 | * OMAP3430. The DPLL will enter low-power stop when its downstream |
| 732 | * clocks are gated. No return value. |
| 733 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 734 | #ifdef CONFIG_COMMON_CLK |
| 735 | void omap3_dpll_allow_idle(struct clk_hw_omap *clk) |
| 736 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 737 | void omap3_dpll_allow_idle(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 738 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 739 | { |
| 740 | const struct dpll_data *dd; |
| 741 | u32 v; |
| 742 | |
| 743 | if (!clk || !clk->dpll_data) |
| 744 | return; |
| 745 | |
| 746 | dd = clk->dpll_data; |
| 747 | |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 748 | if (!dd->autoidle_reg) { |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 749 | #ifndef CONFIG_COMMON_CLK |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 750 | pr_debug("clock: DPLL %s: autoidle not supported\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 751 | __clk_get_name(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 752 | #endif |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 753 | return; |
| 754 | } |
| 755 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 756 | /* |
| 757 | * REVISIT: CORE DPLL can optionally enter low-power bypass |
| 758 | * by writing 0x5 instead of 0x1. Add some mechanism to |
| 759 | * optionally enter this mode. |
| 760 | */ |
| 761 | v = __raw_readl(dd->autoidle_reg); |
| 762 | v &= ~dd->autoidle_mask; |
| 763 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); |
| 764 | __raw_writel(v, dd->autoidle_reg); |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 765 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | /** |
| 769 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling |
| 770 | * @clk: struct clk * of the DPLL to operate on |
| 771 | * |
| 772 | * Disable DPLL automatic idle control. No return value. |
| 773 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 774 | #ifdef CONFIG_COMMON_CLK |
| 775 | void omap3_dpll_deny_idle(struct clk_hw_omap *clk) |
| 776 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 777 | void omap3_dpll_deny_idle(struct clk *clk) |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 778 | #endif |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 779 | { |
| 780 | const struct dpll_data *dd; |
| 781 | u32 v; |
| 782 | |
| 783 | if (!clk || !clk->dpll_data) |
| 784 | return; |
| 785 | |
| 786 | dd = clk->dpll_data; |
| 787 | |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 788 | if (!dd->autoidle_reg) { |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 789 | #ifndef CONFIG_COMMON_CLK |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 790 | pr_debug("clock: DPLL %s: autoidle not supported\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 791 | __clk_get_name(clk)); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 792 | #endif |
Vaibhav Bedia | d76316f | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 793 | return; |
| 794 | } |
| 795 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 796 | v = __raw_readl(dd->autoidle_reg); |
| 797 | v &= ~dd->autoidle_mask; |
| 798 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); |
| 799 | __raw_writel(v, dd->autoidle_reg); |
| 800 | |
| 801 | } |
| 802 | |
| 803 | /* Clock control for DPLL outputs */ |
| 804 | |
| 805 | /** |
| 806 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate |
| 807 | * @clk: DPLL output struct clk |
| 808 | * |
| 809 | * Using parent clock DPLL data, look up DPLL state. If locked, set our |
| 810 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. |
| 811 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 812 | #ifdef CONFIG_COMMON_CLK |
| 813 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, |
| 814 | unsigned long parent_rate) |
| 815 | { |
| 816 | const struct dpll_data *dd; |
| 817 | unsigned long rate; |
| 818 | u32 v; |
| 819 | struct clk_hw_omap *pclk = NULL; |
| 820 | struct clk *parent; |
| 821 | |
| 822 | /* Walk up the parents of clk, looking for a DPLL */ |
| 823 | do { |
| 824 | do { |
| 825 | parent = __clk_get_parent(hw->clk); |
| 826 | hw = __clk_get_hw(parent); |
| 827 | } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); |
| 828 | if (!hw) |
| 829 | break; |
| 830 | pclk = to_clk_hw_omap(hw); |
| 831 | } while (pclk && !pclk->dpll_data); |
| 832 | #else |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 833 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) |
| 834 | { |
| 835 | const struct dpll_data *dd; |
| 836 | unsigned long rate; |
| 837 | u32 v; |
| 838 | struct clk *pclk; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 839 | unsigned long parent_rate; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 840 | |
| 841 | /* Walk up the parents of clk, looking for a DPLL */ |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 842 | pclk = __clk_get_parent(clk); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 843 | while (pclk && !pclk->dpll_data) |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 844 | pclk = __clk_get_parent(pclk); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 845 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 846 | parent_rate = __clk_get_rate(__clk_get_parent(clk)); |
| 847 | #endif |
Paul Walmsley | a032d33 | 2012-08-03 09:21:10 -0600 | [diff] [blame] | 848 | /* clk does not have a DPLL as a parent? error in the clock data */ |
| 849 | if (!pclk) { |
| 850 | WARN_ON(1); |
| 851 | return 0; |
| 852 | } |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 853 | |
| 854 | dd = pclk->dpll_data; |
| 855 | |
| 856 | WARN_ON(!dd->enable_mask); |
| 857 | |
| 858 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
| 859 | v >>= __ffs(dd->enable_mask); |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 860 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 861 | rate = parent_rate; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 862 | else |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 863 | rate = parent_rate * 2; |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 864 | return rate; |
| 865 | } |
Vaibhav Hiremath | 353cec4 | 2012-07-05 08:05:15 -0700 | [diff] [blame] | 866 | |
| 867 | /* OMAP3/4 non-CORE DPLL clkops */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 868 | #ifdef CONFIG_COMMON_CLK |
| 869 | const struct clk_hw_omap_ops clkhwops_omap3_dpll = { |
| 870 | .allow_idle = omap3_dpll_allow_idle, |
| 871 | .deny_idle = omap3_dpll_deny_idle, |
| 872 | }; |
| 873 | #else |
Vaibhav Hiremath | 353cec4 | 2012-07-05 08:05:15 -0700 | [diff] [blame] | 874 | const struct clkops clkops_omap3_noncore_dpll_ops = { |
| 875 | .enable = omap3_noncore_dpll_enable, |
| 876 | .disable = omap3_noncore_dpll_disable, |
| 877 | .allow_idle = omap3_dpll_allow_idle, |
| 878 | .deny_idle = omap3_dpll_deny_idle, |
| 879 | }; |
| 880 | |
| 881 | const struct clkops clkops_omap3_core_dpll_ops = { |
| 882 | .allow_idle = omap3_dpll_allow_idle, |
| 883 | .deny_idle = omap3_dpll_deny_idle, |
| 884 | }; |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame^] | 885 | #endif |