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gerrit-public.fairphone.software / kernel / msm-4.9 / 330ee00412bbaefa7d0597a1bed7804e818ba91c / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 5e3a0e5c6be1b9b75caae2f853f15d291db53aac [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
50
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]51/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]52 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]53 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]54struct r100_mc_save {
55 u32 GENMO_WT;
56 u32 CRTC_EXT_CNTL;
57 u32 CRTC_GEN_CNTL;
58 u32 CRTC2_GEN_CNTL;
59 u32 CUR_OFFSET;
60 u32 CUR2_OFFSET;
61};
62int r100_init(struct radeon_device *rdev);
63void r100_fini(struct radeon_device *rdev);
64int r100_suspend(struct radeon_device *rdev);
65int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]66void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]67bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]68int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]69u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]70void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
71int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]72void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]73int r100_irq_set(struct radeon_device *rdev);
74int r100_irq_process(struct radeon_device *rdev);
75void r100_fence_ring_emit(struct radeon_device *rdev,
76 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]77void r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]78 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]79 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]80 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]81int r100_cs_parse(struct radeon_cs_parser *p);
82void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
83uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
84int r100_copy_blit(struct radeon_device *rdev,
85 uint64_t src_offset,
86 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]87 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]88 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]89int r100_set_surface_reg(struct radeon_device *rdev, int reg,
90 uint32_t tiling_flags, uint32_t pitch,
91 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]92void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]93void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]94void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]95int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]96void r100_hpd_init(struct radeon_device *rdev);
97void r100_hpd_fini(struct radeon_device *rdev);
98bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
99void r100_hpd_set_polarity(struct radeon_device *rdev,
100 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]101int r100_debugfs_rbbm_init(struct radeon_device *rdev);
102int r100_debugfs_cp_init(struct radeon_device *rdev);
103void r100_cp_disable(struct radeon_device *rdev);
104int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
105void r100_cp_fini(struct radeon_device *rdev);
106int r100_pci_gart_init(struct radeon_device *rdev);
107void r100_pci_gart_fini(struct radeon_device *rdev);
108int r100_pci_gart_enable(struct radeon_device *rdev);
109void r100_pci_gart_disable(struct radeon_device *rdev);
110int r100_debugfs_mc_info_init(struct radeon_device *rdev);
111int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]112int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]113void r100_irq_disable(struct radeon_device *rdev);
114void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
116void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]117int r100_cp_reset(struct radeon_device *rdev);
118void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]119void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]120int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 struct radeon_bo *robj);
123int r100_cs_parse_packet0(struct radeon_cs_parser *p,
124 struct radeon_cs_packet *pkt,
125 const unsigned *auth, unsigned n,
126 radeon_packet0_check_t check);
127int r100_cs_packet_parse(struct radeon_cs_parser *p,
128 struct radeon_cs_packet *pkt,
129 unsigned idx);
130void r100_enable_bm(struct radeon_device *rdev);
131void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]132void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]133extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]134extern void r100_pm_misc(struct radeon_device *rdev);
135extern void r100_pm_prepare(struct radeon_device *rdev);
136extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]137extern void r100_pm_init_profile(struct radeon_device *rdev);
138extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]139extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
140extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
141extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]142extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]143extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]144
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]145/*
146 * r200,rv250,rs300,rv280
147 */
148extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]149 uint64_t src_offset,
150 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]151 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]152 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]153void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]154
155/*
156 * r300,r350,rv350,rv380
157 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]158extern int r300_init(struct radeon_device *rdev);
159extern void r300_fini(struct radeon_device *rdev);
160extern int r300_suspend(struct radeon_device *rdev);
161extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]162extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]163extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]164extern void r300_fence_ring_emit(struct radeon_device *rdev,
165 struct radeon_fence *fence);
166extern int r300_cs_parse(struct radeon_cs_parser *p);
167extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
168extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]169extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]170extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]171extern void r300_set_reg_safe(struct radeon_device *rdev);
172extern void r300_mc_program(struct radeon_device *rdev);
173extern void r300_mc_init(struct radeon_device *rdev);
174extern void r300_clock_startup(struct radeon_device *rdev);
175extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
176extern int rv370_pcie_gart_init(struct radeon_device *rdev);
177extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
178extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
179extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]180extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]181
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]182/*
183 * r420,r423,rv410
184 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]185extern int r420_init(struct radeon_device *rdev);
186extern void r420_fini(struct radeon_device *rdev);
187extern int r420_suspend(struct radeon_device *rdev);
188extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]189extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]190extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
191extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
192extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
193extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]194
195/*
196 * rs400,rs480
197 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]198extern int rs400_init(struct radeon_device *rdev);
199extern void rs400_fini(struct radeon_device *rdev);
200extern int rs400_suspend(struct radeon_device *rdev);
201extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]202void rs400_gart_tlb_flush(struct radeon_device *rdev);
203int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
204uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
205void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]206int rs400_gart_init(struct radeon_device *rdev);
207int rs400_gart_enable(struct radeon_device *rdev);
208void rs400_gart_adjust_size(struct radeon_device *rdev);
209void rs400_gart_disable(struct radeon_device *rdev);
210void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]211extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]212
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]213/*
214 * rs600.
215 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]216extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]217extern int rs600_init(struct radeon_device *rdev);
218extern void rs600_fini(struct radeon_device *rdev);
219extern int rs600_suspend(struct radeon_device *rdev);
220extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]221int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]222int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]223void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]224u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]225void rs600_gart_tlb_flush(struct radeon_device *rdev);
226int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
227uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
228void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]229void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]230void rs600_hpd_init(struct radeon_device *rdev);
231void rs600_hpd_fini(struct radeon_device *rdev);
232bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
233void rs600_hpd_set_polarity(struct radeon_device *rdev,
234 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]235extern void rs600_pm_misc(struct radeon_device *rdev);
236extern void rs600_pm_prepare(struct radeon_device *rdev);
237extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]238extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
239extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
240extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]241void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]242extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]243extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]244
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]245/*
246 * rs690,rs740
247 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]248int rs690_init(struct radeon_device *rdev);
249void rs690_fini(struct radeon_device *rdev);
250int rs690_resume(struct radeon_device *rdev);
251int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]252uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
253void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]254void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]255void rs690_line_buffer_adjust(struct radeon_device *rdev,
256 struct drm_display_mode *mode1,
257 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]258extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]259
260/*
261 * rv515
262 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]263struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]264 u32 vga_render_control;
265 u32 vga_hdp_control;
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]266};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]267
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]268int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]269void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]270uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
271void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]272void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]273void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]274int rv515_resume(struct radeon_device *rdev);
275int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]276void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
277void rv515_vga_render_disable(struct radeon_device *rdev);
278void rv515_set_safe_registers(struct radeon_device *rdev);
279void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
280void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
281void rv515_clock_startup(struct radeon_device *rdev);
282void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]283int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]284
285/*
286 * r520,rv530,rv560,rv570,r580
287 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]288int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]289int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]290int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]291
292/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]293 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]294 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]295int r600_init(struct radeon_device *rdev);
296void r600_fini(struct radeon_device *rdev);
297int r600_suspend(struct radeon_device *rdev);
298int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]299void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]300int r600_wb_init(struct radeon_device *rdev);
301void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]302void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]303uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
304void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]305int r600_cs_parse(struct radeon_cs_parser *p);
306void r600_fence_ring_emit(struct radeon_device *rdev,
307 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]308void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]309 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]310 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]311 bool emit_wait);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]312bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]313int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]314int r600_set_surface_reg(struct radeon_device *rdev, int reg,
315 uint32_t tiling_flags, uint32_t pitch,
316 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]317void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]318int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]319void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]320int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]321int r600_copy_blit(struct radeon_device *rdev,
322 uint64_t src_offset, uint64_t dst_offset,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]323 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]324void r600_hpd_init(struct radeon_device *rdev);
325void r600_hpd_fini(struct radeon_device *rdev);
326bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
327void r600_hpd_set_polarity(struct radeon_device *rdev,
328 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]329extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]330extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]331extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]332extern void r600_pm_init_profile(struct radeon_device *rdev);
333extern void rs780_pm_init_profile(struct radeon_device *rdev);
334extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]335extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
336extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]337bool r600_card_posted(struct radeon_device *rdev);
338void r600_cp_stop(struct radeon_device *rdev);
339int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]340void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]341int r600_cp_resume(struct radeon_device *rdev);
342void r600_cp_fini(struct radeon_device *rdev);
343int r600_count_pipe_bits(uint32_t val);
344int r600_mc_wait_for_idle(struct radeon_device *rdev);
345int r600_pcie_gart_init(struct radeon_device *rdev);
346void r600_scratch_init(struct radeon_device *rdev);
347int r600_blit_init(struct radeon_device *rdev);
348void r600_blit_fini(struct radeon_device *rdev);
349int r600_init_microcode(struct radeon_device *rdev);
350/* r600 irq */
351int r600_irq_process(struct radeon_device *rdev);
352int r600_irq_init(struct radeon_device *rdev);
353void r600_irq_fini(struct radeon_device *rdev);
354void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
355int r600_irq_set(struct radeon_device *rdev);
356void r600_irq_suspend(struct radeon_device *rdev);
357void r600_disable_interrupts(struct radeon_device *rdev);
358void r600_rlc_stop(struct radeon_device *rdev);
359/* r600 audio */
360int r600_audio_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]361void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
Rafał Miłecki3299de92012-05-14 21:25:57 +0200[diff] [blame]362struct r600_audio r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]363void r600_audio_fini(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]364int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
365void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]366/* r600 blit */
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]367int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]368 struct radeon_fence **fence, struct radeon_sa_bo **vb,
369 struct radeon_semaphore **sem);
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]370void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]371 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]372void r600_kms_blit_copy(struct radeon_device *rdev,
373 u64 src_gpu_addr, u64 dst_gpu_addr,
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]374 unsigned num_gpu_pages,
375 struct radeon_sa_bo *vb);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]376int r600_mc_wait_for_idle(struct radeon_device *rdev);
Marek Olšák6759a0a2012-08-09 16:34:17 +0200[diff] [blame]377uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]378
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]379/*
380 * rv770,rv730,rv710,rv740
381 */
382int rv770_init(struct radeon_device *rdev);
383void rv770_fini(struct radeon_device *rdev);
384int rv770_suspend(struct radeon_device *rdev);
385int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]386void rv770_pm_misc(struct radeon_device *rdev);
387u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
388void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
389void r700_cp_stop(struct radeon_device *rdev);
390void r700_cp_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]391
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]392/*
393 * evergreen
394 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]395struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]396 u32 vga_render_control;
397 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]398 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]399};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]400
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]401void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]402int evergreen_init(struct radeon_device *rdev);
403void evergreen_fini(struct radeon_device *rdev);
404int evergreen_suspend(struct radeon_device *rdev);
405int evergreen_resume(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]406bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]407int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]408void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]409void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]410void evergreen_hpd_init(struct radeon_device *rdev);
411void evergreen_hpd_fini(struct radeon_device *rdev);
412bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
413void evergreen_hpd_set_polarity(struct radeon_device *rdev,
414 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]415u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
416int evergreen_irq_set(struct radeon_device *rdev);
417int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]418extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]419extern void evergreen_pm_misc(struct radeon_device *rdev);
420extern void evergreen_pm_prepare(struct radeon_device *rdev);
421extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]422extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]423extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]424extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
425extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
426extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]427extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]428void evergreen_disable_interrupt_state(struct radeon_device *rdev);
429int evergreen_blit_init(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]430int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]431
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]432/*
433 * cayman
434 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]435void cayman_fence_ring_emit(struct radeon_device *rdev,
436 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]437void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
438int cayman_init(struct radeon_device *rdev);
439void cayman_fini(struct radeon_device *rdev);
440int cayman_suspend(struct radeon_device *rdev);
441int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]442int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]443void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
444int cayman_vm_init(struct radeon_device *rdev);
445void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]446void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]447uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Christian Königdce34bf2012-09-17 19:36:18 +0200[diff] [blame]448void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
449 uint64_t addr, unsigned count,
450 uint32_t incr, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]451int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]452
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]453/* DCE6 - SI */
454void dce6_bandwidth_update(struct radeon_device *rdev);
455
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]456/*
457 * si
458 */
459void si_fence_ring_emit(struct radeon_device *rdev,
460 struct radeon_fence *fence);
461void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
462int si_init(struct radeon_device *rdev);
463void si_fini(struct radeon_device *rdev);
464int si_suspend(struct radeon_device *rdev);
465int si_resume(struct radeon_device *rdev);
466bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
467int si_asic_reset(struct radeon_device *rdev);
468void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
469int si_irq_set(struct radeon_device *rdev);
470int si_irq_process(struct radeon_device *rdev);
471int si_vm_init(struct radeon_device *rdev);
472void si_vm_fini(struct radeon_device *rdev);
Alex Deucher82ffd922012-10-02 14:47:46 -0400[diff] [blame]473void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
474 uint64_t addr, unsigned count,
475 uint32_t incr, uint32_t flags);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]476void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]477int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Marek Olšák6759a0a2012-08-09 16:34:17 +0200[diff] [blame]478uint64_t si_get_gpu_clock(struct radeon_device *rdev);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]479
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]480#endif