Dave Airlie | 94bb598 | 2006-12-19 17:49:08 +1100 | [diff] [blame] | 1 | /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */ |
| 2 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * The Weather Channel (TM) funded Tungsten Graphics to develop the |
| 6 | * initial release of the Radeon 8500 driver under the XFree86 license. |
| 7 | * This notice must be preserved. |
| 8 | * |
| 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 10 | * copy of this software and associated documentation files (the "Software"), |
| 11 | * to deal in the Software without restriction, including without limitation |
| 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 13 | * and/or sell copies of the Software, and to permit persons to whom the |
| 14 | * Software is furnished to do so, subject to the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the next |
| 17 | * paragraph) shall be included in all copies or substantial portions of the |
| 18 | * Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 23 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 26 | * DEALINGS IN THE SOFTWARE. |
| 27 | * |
| 28 | * Authors: |
| 29 | * Keith Whitwell <keith@tungstengraphics.com> |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 30 | * Michel D�zer <michel@daenzer.net> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | */ |
| 32 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
| 34 | #include <drm/radeon_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include "radeon_drv.h" |
| 36 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 37 | void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state) |
Dave Airlie | 6921e33 | 2005-06-26 21:05:59 +1000 | [diff] [blame] | 38 | { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 39 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 40 | |
| 41 | if (state) |
| 42 | dev_priv->irq_enable_reg |= mask; |
| 43 | else |
| 44 | dev_priv->irq_enable_reg &= ~mask; |
| 45 | |
Dave Airlie | 077ebed | 2008-12-22 17:11:02 +1000 | [diff] [blame] | 46 | if (dev->irq_enabled) |
Dave Airlie | fae7043 | 2008-12-09 15:30:50 +1000 | [diff] [blame] | 47 | RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) |
| 51 | { |
| 52 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 53 | |
| 54 | if (state) |
| 55 | dev_priv->r500_disp_irq_reg |= mask; |
| 56 | else |
| 57 | dev_priv->r500_disp_irq_reg &= ~mask; |
| 58 | |
Dave Airlie | 077ebed | 2008-12-22 17:11:02 +1000 | [diff] [blame] | 59 | if (dev->irq_enabled) |
Dave Airlie | fae7043 | 2008-12-09 15:30:50 +1000 | [diff] [blame] | 60 | RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | int radeon_enable_vblank(struct drm_device *dev, int crtc) |
| 64 | { |
| 65 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 66 | |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 67 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 68 | switch (crtc) { |
| 69 | case 0: |
| 70 | r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1); |
| 71 | break; |
| 72 | case 1: |
| 73 | r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1); |
| 74 | break; |
| 75 | default: |
| 76 | DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", |
| 77 | crtc); |
Vasiliy Kulikov | 21e2eae | 2010-11-14 23:08:27 +0300 | [diff] [blame] | 78 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 79 | } |
| 80 | } else { |
| 81 | switch (crtc) { |
| 82 | case 0: |
| 83 | radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1); |
| 84 | break; |
| 85 | case 1: |
| 86 | radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1); |
| 87 | break; |
| 88 | default: |
| 89 | DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", |
| 90 | crtc); |
Vasiliy Kulikov | 21e2eae | 2010-11-14 23:08:27 +0300 | [diff] [blame] | 91 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 92 | } |
| 93 | } |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | void radeon_disable_vblank(struct drm_device *dev, int crtc) |
| 99 | { |
| 100 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 101 | |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 102 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 103 | switch (crtc) { |
| 104 | case 0: |
| 105 | r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0); |
| 106 | break; |
| 107 | case 1: |
| 108 | r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0); |
| 109 | break; |
| 110 | default: |
| 111 | DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", |
| 112 | crtc); |
| 113 | break; |
| 114 | } |
| 115 | } else { |
| 116 | switch (crtc) { |
| 117 | case 0: |
| 118 | radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0); |
| 119 | break; |
| 120 | case 1: |
| 121 | radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0); |
| 122 | break; |
| 123 | default: |
| 124 | DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", |
| 125 | crtc); |
| 126 | break; |
| 127 | } |
| 128 | } |
| 129 | } |
| 130 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 131 | static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 132 | { |
| 133 | u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS); |
| 134 | u32 irq_mask = RADEON_SW_INT_TEST; |
| 135 | |
| 136 | *r500_disp_int = 0; |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 137 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 138 | /* vbl interrupts in a different place */ |
| 139 | |
| 140 | if (irqs & R500_DISPLAY_INT_STATUS) { |
| 141 | /* if a display interrupt */ |
| 142 | u32 disp_irq; |
| 143 | |
| 144 | disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS); |
| 145 | |
| 146 | *r500_disp_int = disp_irq; |
| 147 | if (disp_irq & R500_D1_VBLANK_INTERRUPT) |
| 148 | RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK); |
| 149 | if (disp_irq & R500_D2_VBLANK_INTERRUPT) |
| 150 | RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK); |
| 151 | } |
| 152 | irq_mask |= R500_DISPLAY_INT_STATUS; |
| 153 | } else |
| 154 | irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT; |
| 155 | |
| 156 | irqs &= irq_mask; |
| 157 | |
Dave Airlie | 6921e33 | 2005-06-26 21:05:59 +1000 | [diff] [blame] | 158 | if (irqs) |
| 159 | RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 160 | |
Dave Airlie | 6921e33 | 2005-06-26 21:05:59 +1000 | [diff] [blame] | 161 | return irqs; |
| 162 | } |
| 163 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | /* Interrupts - Used for device synchronization and flushing in the |
| 165 | * following circumstances: |
| 166 | * |
| 167 | * - Exclusive FB access with hw idle: |
| 168 | * - Wait for GUI Idle (?) interrupt, then do normal flush. |
| 169 | * |
| 170 | * - Frame throttling, NV_fence: |
| 171 | * - Drop marker irq's into command stream ahead of time. |
| 172 | * - Wait on irq's with lock *not held* |
| 173 | * - Check each for termination condition |
| 174 | * |
| 175 | * - Internally in cp_getbuffer, etc: |
| 176 | * - as above, but wait with lock held??? |
| 177 | * |
| 178 | * NOTE: These functions are misleadingly named -- the irq's aren't |
| 179 | * tied to dma at all, this is just a hangover from dri prehistory. |
| 180 | */ |
| 181 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 182 | irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 184 | struct drm_device *dev = (struct drm_device *) arg; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 185 | drm_radeon_private_t *dev_priv = |
| 186 | (drm_radeon_private_t *) dev->dev_private; |
| 187 | u32 stat; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 188 | u32 r500_disp_int; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | |
Alex Deucher | b15591f | 2009-09-17 14:25:12 -0400 | [diff] [blame] | 190 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 191 | return IRQ_NONE; |
| 192 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | /* Only consider the bits we're interested in - others could be used |
| 194 | * outside the DRM |
| 195 | */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 196 | stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | if (!stat) |
| 198 | return IRQ_NONE; |
| 199 | |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 200 | stat &= dev_priv->irq_enable_reg; |
| 201 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | /* SW interrupt */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 203 | if (stat & RADEON_SW_INT_TEST) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 204 | DRM_WAKEUP(&dev_priv->swi_queue); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | |
| 206 | /* VBLANK interrupt */ |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 207 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 208 | if (r500_disp_int & R500_D1_VBLANK_INTERRUPT) |
| 209 | drm_handle_vblank(dev, 0); |
| 210 | if (r500_disp_int & R500_D2_VBLANK_INTERRUPT) |
| 211 | drm_handle_vblank(dev, 1); |
| 212 | } else { |
| 213 | if (stat & RADEON_CRTC_VBLANK_STAT) |
| 214 | drm_handle_vblank(dev, 0); |
| 215 | if (stat & RADEON_CRTC2_VBLANK_STAT) |
| 216 | drm_handle_vblank(dev, 1); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 217 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | return IRQ_HANDLED; |
| 219 | } |
| 220 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 221 | static int radeon_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | { |
| 223 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 224 | unsigned int ret; |
| 225 | RING_LOCALS; |
| 226 | |
| 227 | atomic_inc(&dev_priv->swi_emitted); |
| 228 | ret = atomic_read(&dev_priv->swi_emitted); |
| 229 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 230 | BEGIN_RING(4); |
| 231 | OUT_RING_REG(RADEON_LAST_SWI_REG, ret); |
| 232 | OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); |
| 233 | ADVANCE_RING(); |
| 234 | COMMIT_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
| 236 | return ret; |
| 237 | } |
| 238 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 239 | static int radeon_wait_irq(struct drm_device * dev, int swi_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 241 | drm_radeon_private_t *dev_priv = |
| 242 | (drm_radeon_private_t *) dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | int ret = 0; |
| 244 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 245 | if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) |
| 246 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | |
| 248 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 249 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 250 | DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, |
| 251 | RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | |
| 253 | return ret; |
| 254 | } |
| 255 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 256 | u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 258 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 259 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 260 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 261 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 262 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | } |
| 264 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 265 | if (crtc < 0 || crtc > 1) { |
| 266 | DRM_ERROR("Invalid crtc %d\n", crtc); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 267 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 268 | } |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 269 | |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 270 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 271 | if (crtc == 0) |
| 272 | return RADEON_READ(R500_D1CRTC_FRAME_COUNT); |
| 273 | else |
| 274 | return RADEON_READ(R500_D2CRTC_FRAME_COUNT); |
| 275 | } else { |
| 276 | if (crtc == 0) |
| 277 | return RADEON_READ(RADEON_CRTC_CRNT_FRAME); |
| 278 | else |
| 279 | return RADEON_READ(RADEON_CRTC2_CRNT_FRAME); |
| 280 | } |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 281 | } |
| 282 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | /* Needs the lock as it touches the ring. |
| 284 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 285 | int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 288 | drm_radeon_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | int result; |
| 290 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 291 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 292 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 293 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | } |
| 295 | |
Darren Jenkins | 65aa2f4 | 2009-12-30 12:16:35 +1100 | [diff] [blame] | 296 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 297 | return -EINVAL; |
| 298 | |
| 299 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 300 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 301 | result = radeon_emit_irq(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 303 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 304 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 305 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | /* Doesn't need the hardware lock. |
| 312 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 313 | int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 316 | drm_radeon_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 318 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 319 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 320 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | } |
| 322 | |
Alex Deucher | b15591f | 2009-09-17 14:25:12 -0400 | [diff] [blame] | 323 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 324 | return -EINVAL; |
| 325 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 326 | return radeon_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | /* drm_dma.h hooks |
| 330 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 331 | void radeon_driver_irq_preinstall(struct drm_device * dev) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 332 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | drm_radeon_private_t *dev_priv = |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 334 | (drm_radeon_private_t *) dev->dev_private; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 335 | u32 dummy; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | |
Alex Deucher | b15591f | 2009-09-17 14:25:12 -0400 | [diff] [blame] | 337 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 338 | return; |
| 339 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 340 | /* Disable *all* interrupts */ |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 341 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 342 | RADEON_WRITE(R500_DxMODE_INT_MASK, 0); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 343 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | |
| 345 | /* Clear bits if they're already high */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 346 | radeon_acknowledge_irqs(dev_priv, &dummy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | } |
| 348 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 349 | int radeon_driver_irq_postinstall(struct drm_device *dev) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 350 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | drm_radeon_private_t *dev_priv = |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 352 | (drm_radeon_private_t *) dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 354 | atomic_set(&dev_priv->swi_emitted, 0); |
| 355 | DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 357 | dev->max_vblank_count = 0x001fffff; |
| 358 | |
Alex Deucher | b15591f | 2009-09-17 14:25:12 -0400 | [diff] [blame] | 359 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 360 | return 0; |
| 361 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 362 | radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); |
| 363 | |
| 364 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | } |
| 366 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 367 | void radeon_driver_irq_uninstall(struct drm_device * dev) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 368 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | drm_radeon_private_t *dev_priv = |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 370 | (drm_radeon_private_t *) dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | if (!dev_priv) |
| 372 | return; |
| 373 | |
Alex Deucher | b15591f | 2009-09-17 14:25:12 -0400 | [diff] [blame] | 374 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 375 | return; |
| 376 | |
Alex Deucher | 800b699 | 2009-03-06 11:47:54 -0500 | [diff] [blame] | 377 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 378 | RADEON_WRITE(R500_DxMODE_INT_MASK, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | /* Disable *all* interrupts */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 380 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | } |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 382 | |
| 383 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 384 | int radeon_vblank_crtc_get(struct drm_device *dev) |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 385 | { |
| 386 | drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 387 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 388 | return dev_priv->vblank_crtc; |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 389 | } |
| 390 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 391 | int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value) |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 392 | { |
| 393 | drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; |
| 394 | if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) { |
| 395 | DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 396 | return -EINVAL; |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 397 | } |
| 398 | dev_priv->vblank_crtc = (unsigned int)value; |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 399 | return 0; |
| 400 | } |