Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Agere Systems Inc. |
| 3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 4 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 5 | * Copyright © 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 6 | * All rights reserved. |
| 7 | * http://www.agere.com |
| 8 | * |
| 9 | *------------------------------------------------------------------------------ |
| 10 | * |
| 11 | * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the |
| 12 | * PHY. |
| 13 | * |
| 14 | *------------------------------------------------------------------------------ |
| 15 | * |
| 16 | * SOFTWARE LICENSE |
| 17 | * |
| 18 | * This software is provided subject to the following terms and conditions, |
| 19 | * which you should read carefully before using the software. Using this |
| 20 | * software indicates your acceptance of these terms and conditions. If you do |
| 21 | * not agree with these terms and conditions, do not use the software. |
| 22 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 23 | * Copyright © 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 24 | * All rights reserved. |
| 25 | * |
| 26 | * Redistribution and use in source or binary forms, with or without |
| 27 | * modifications, are permitted provided that the following conditions are met: |
| 28 | * |
| 29 | * . Redistributions of source code must retain the above copyright notice, this |
| 30 | * list of conditions and the following Disclaimer as comments in the code as |
| 31 | * well as in the documentation and/or other materials provided with the |
| 32 | * distribution. |
| 33 | * |
| 34 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 35 | * this list of conditions and the following Disclaimer in the documentation |
| 36 | * and/or other materials provided with the distribution. |
| 37 | * |
| 38 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 39 | * may be used to endorse or promote products derived from this software |
| 40 | * without specific prior written permission. |
| 41 | * |
| 42 | * Disclaimer |
| 43 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 44 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 45 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 46 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 47 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 48 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 49 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 50 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 51 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 52 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 54 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 55 | * DAMAGE. |
| 56 | * |
| 57 | */ |
| 58 | |
| 59 | #ifndef _ET1310_PHY_H_ |
| 60 | #define _ET1310_PHY_H_ |
| 61 | |
| 62 | #include "et1310_address_map.h" |
| 63 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 64 | /* MI Register Addresses */ |
| 65 | #define MI_CONTROL_REG 0 |
| 66 | #define MI_STATUS_REG 1 |
| 67 | #define MI_PHY_IDENTIFIER_1_REG 2 |
| 68 | #define MI_PHY_IDENTIFIER_2_REG 3 |
| 69 | #define MI_AUTONEG_ADVERTISEMENT_REG 4 |
| 70 | #define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5 |
| 71 | #define MI_AUTONEG_EXPANSION_REG 6 |
| 72 | #define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7 |
| 73 | #define MI_LINK_PARTNER_NEXT_PAGE_REG 8 |
| 74 | #define MI_1000BASET_CONTROL_REG 9 |
| 75 | #define MI_1000BASET_STATUS_REG 10 |
| 76 | #define MI_RESERVED11_REG 11 |
| 77 | #define MI_RESERVED12_REG 12 |
| 78 | #define MI_RESERVED13_REG 13 |
| 79 | #define MI_RESERVED14_REG 14 |
| 80 | #define MI_EXTENDED_STATUS_REG 15 |
| 81 | |
| 82 | /* VMI Register Addresses */ |
| 83 | #define VMI_RESERVED16_REG 16 |
| 84 | #define VMI_RESERVED17_REG 17 |
| 85 | #define VMI_RESERVED18_REG 18 |
| 86 | #define VMI_LOOPBACK_CONTROL_REG 19 |
| 87 | #define VMI_RESERVED20_REG 20 |
| 88 | #define VMI_MI_CONTROL_REG 21 |
| 89 | #define VMI_PHY_CONFIGURATION_REG 22 |
| 90 | #define VMI_PHY_CONTROL_REG 23 |
| 91 | #define VMI_INTERRUPT_MASK_REG 24 |
| 92 | #define VMI_INTERRUPT_STATUS_REG 25 |
| 93 | #define VMI_PHY_STATUS_REG 26 |
| 94 | #define VMI_LED_CONTROL_1_REG 27 |
| 95 | #define VMI_LED_CONTROL_2_REG 28 |
| 96 | #define VMI_RESERVED29_REG 29 |
| 97 | #define VMI_RESERVED30_REG 30 |
| 98 | #define VMI_RESERVED31_REG 31 |
| 99 | |
| 100 | /* PHY Register Mapping(MI) Management Interface Regs */ |
| 101 | typedef struct _MI_REGS_t { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 102 | u8 bmcr; /* Basic mode control reg(Reg 0x00) */ |
| 103 | u8 bmsr; /* Basic mode status reg(Reg 0x01) */ |
| 104 | u8 idr1; /* Phy identifier reg 1(Reg 0x02) */ |
| 105 | u8 idr2; /* Phy identifier reg 2(Reg 0x03) */ |
| 106 | u8 anar; /* Auto-Negotiation advertisement(Reg 0x04) */ |
| 107 | u8 anlpar; /* Auto-Negotiation link Partner Ability(Reg 0x05) */ |
| 108 | u8 aner; /* Auto-Negotiation expansion reg(Reg 0x06) */ |
| 109 | u8 annptr; /* Auto-Negotiation next page transmit reg(Reg 0x07) */ |
| 110 | u8 lpnpr; /* link partner next page reg(Reg 0x08) */ |
| 111 | u8 gcr; /* Gigabit basic mode control reg(Reg 0x09) */ |
| 112 | u8 gsr; /* Gigabit basic mode status reg(Reg 0x0A) */ |
| 113 | u8 mi_res1[4]; /* Future use by MI working group(Reg 0x0B - 0x0E) */ |
| 114 | u8 esr; /* Extended status reg(Reg 0x0F) */ |
| 115 | u8 mi_res2[3]; /* Future use by MI working group(Reg 0x10 - 0x12) */ |
| 116 | u8 loop_ctl; /* Loopback Control Reg(Reg 0x13) */ |
| 117 | u8 mi_res3; /* Future use by MI working group(Reg 0x14) */ |
| 118 | u8 mcr; /* MI Control Reg(Reg 0x15) */ |
| 119 | u8 pcr; /* Configuration Reg(Reg 0x16) */ |
| 120 | u8 phy_ctl; /* PHY Control Reg(Reg 0x17) */ |
| 121 | u8 imr; /* Interrupt Mask Reg(Reg 0x18) */ |
| 122 | u8 isr; /* Interrupt Status Reg(Reg 0x19) */ |
| 123 | u8 psr; /* PHY Status Reg(Reg 0x1A) */ |
| 124 | u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */ |
| 125 | u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */ |
| 126 | u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 127 | } MI_REGS_t, *PMI_REGS_t; |
| 128 | |
| 129 | /* MI Register 0: Basic mode control register */ |
| 130 | typedef union _MI_BMCR_t { |
| 131 | u16 value; |
| 132 | struct { |
| 133 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 134 | u16 reset:1; /* bit 15 */ |
| 135 | u16 loopback:1; /* bit 14 */ |
| 136 | u16 speed_sel:1; /* bit 13 */ |
| 137 | u16 enable_autoneg:1; /* bit 12 */ |
| 138 | u16 power_down:1; /* bit 11 */ |
| 139 | u16 isolate:1; /* bit 10 */ |
| 140 | u16 restart_autoneg:1; /* bit 9 */ |
| 141 | u16 duplex_mode:1; /* bit 8 */ |
| 142 | u16 col_test:1; /* bit 7 */ |
| 143 | u16 speed_1000_sel:1; /* bit 6 */ |
| 144 | u16 res1:6; /* bits 0-5 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 145 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 146 | u16 res1:6; /* bits 0-5 */ |
| 147 | u16 speed_1000_sel:1; /* bit 6 */ |
| 148 | u16 col_test:1; /* bit 7 */ |
| 149 | u16 duplex_mode:1; /* bit 8 */ |
| 150 | u16 restart_autoneg:1; /* bit 9 */ |
| 151 | u16 isolate:1; /* bit 10 */ |
| 152 | u16 power_down:1; /* bit 11 */ |
| 153 | u16 enable_autoneg:1; /* bit 12 */ |
| 154 | u16 speed_sel:1; /* bit 13 */ |
| 155 | u16 loopback:1; /* bit 14 */ |
| 156 | u16 reset:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 157 | #endif |
| 158 | } bits; |
| 159 | } MI_BMCR_t, *PMI_BMCR_t; |
| 160 | |
| 161 | /* MI Register 1: Basic mode status register */ |
| 162 | typedef union _MI_BMSR_t { |
| 163 | u16 value; |
| 164 | struct { |
| 165 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 166 | u16 link_100T4:1; /* bit 15 */ |
| 167 | u16 link_100fdx:1; /* bit 14 */ |
| 168 | u16 link_100hdx:1; /* bit 13 */ |
| 169 | u16 link_10fdx:1; /* bit 12 */ |
| 170 | u16 link_10hdx:1; /* bit 11 */ |
| 171 | u16 link_100T2fdx:1; /* bit 10 */ |
| 172 | u16 link_100T2hdx:1; /* bit 9 */ |
| 173 | u16 extend_status:1; /* bit 8 */ |
| 174 | u16 res1:1; /* bit 7 */ |
| 175 | u16 preamble_supress:1; /* bit 6 */ |
| 176 | u16 auto_neg_complete:1; /* bit 5 */ |
| 177 | u16 remote_fault:1; /* bit 4 */ |
| 178 | u16 auto_neg_able:1; /* bit 3 */ |
| 179 | u16 link_status:1; /* bit 2 */ |
| 180 | u16 jabber_detect:1; /* bit 1 */ |
| 181 | u16 ext_cap:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 182 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 183 | u16 ext_cap:1; /* bit 0 */ |
| 184 | u16 jabber_detect:1; /* bit 1 */ |
| 185 | u16 link_status:1; /* bit 2 */ |
| 186 | u16 auto_neg_able:1; /* bit 3 */ |
| 187 | u16 remote_fault:1; /* bit 4 */ |
| 188 | u16 auto_neg_complete:1; /* bit 5 */ |
| 189 | u16 preamble_supress:1; /* bit 6 */ |
| 190 | u16 res1:1; /* bit 7 */ |
| 191 | u16 extend_status:1; /* bit 8 */ |
| 192 | u16 link_100T2hdx:1; /* bit 9 */ |
| 193 | u16 link_100T2fdx:1; /* bit 10 */ |
| 194 | u16 link_10hdx:1; /* bit 11 */ |
| 195 | u16 link_10fdx:1; /* bit 12 */ |
| 196 | u16 link_100hdx:1; /* bit 13 */ |
| 197 | u16 link_100fdx:1; /* bit 14 */ |
| 198 | u16 link_100T4:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 199 | #endif |
| 200 | } bits; |
| 201 | } MI_BMSR_t, *PMI_BMSR_t; |
| 202 | |
| 203 | /* MI Register 2: Physical Identifier 1 */ |
| 204 | typedef union _MI_IDR1_t { |
| 205 | u16 value; |
| 206 | struct { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 207 | u16 ieee_address:16; /* 0x0282 default(bits 0-15) */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 208 | } bits; |
| 209 | } MI_IDR1_t, *PMI_IDR1_t; |
| 210 | |
| 211 | /* MI Register 3: Physical Identifier 2 */ |
| 212 | typedef union _MI_IDR2_t { |
| 213 | u16 value; |
| 214 | struct { |
| 215 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 216 | u16 ieee_address:6; /* 111100 default(bits 10-15) */ |
| 217 | u16 model_no:6; /* 000001 default(bits 4-9) */ |
| 218 | u16 rev_no:4; /* 0010 default(bits 0-3) */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 219 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 220 | u16 rev_no:4; /* 0010 default(bits 0-3) */ |
| 221 | u16 model_no:6; /* 000001 default(bits 4-9) */ |
| 222 | u16 ieee_address:6; /* 111100 default(bits 10-15) */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 223 | #endif |
| 224 | } bits; |
| 225 | } MI_IDR2_t, *PMI_IDR2_t; |
| 226 | |
| 227 | /* MI Register 4: Auto-negotiation advertisement register */ |
| 228 | typedef union _MI_ANAR_t { |
| 229 | u16 value; |
| 230 | struct { |
| 231 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 232 | u16 np_indication:1; /* bit 15 */ |
| 233 | u16 res2:1; /* bit 14 */ |
| 234 | u16 remote_fault:1; /* bit 13 */ |
| 235 | u16 res1:1; /* bit 12 */ |
| 236 | u16 cap_asmpause:1; /* bit 11 */ |
| 237 | u16 cap_pause:1; /* bit 10 */ |
| 238 | u16 cap_100T4:1; /* bit 9 */ |
| 239 | u16 cap_100fdx:1; /* bit 8 */ |
| 240 | u16 cap_100hdx:1; /* bit 7 */ |
| 241 | u16 cap_10fdx:1; /* bit 6 */ |
| 242 | u16 cap_10hdx:1; /* bit 5 */ |
| 243 | u16 selector:5; /* bits 0-4 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 244 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 245 | u16 selector:5; /* bits 0-4 */ |
| 246 | u16 cap_10hdx:1; /* bit 5 */ |
| 247 | u16 cap_10fdx:1; /* bit 6 */ |
| 248 | u16 cap_100hdx:1; /* bit 7 */ |
| 249 | u16 cap_100fdx:1; /* bit 8 */ |
| 250 | u16 cap_100T4:1; /* bit 9 */ |
| 251 | u16 cap_pause:1; /* bit 10 */ |
| 252 | u16 cap_asmpause:1; /* bit 11 */ |
| 253 | u16 res1:1; /* bit 12 */ |
| 254 | u16 remote_fault:1; /* bit 13 */ |
| 255 | u16 res2:1; /* bit 14 */ |
| 256 | u16 np_indication:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 257 | #endif |
| 258 | } bits; |
| 259 | } MI_ANAR_t, *PMI_ANAR_t; |
| 260 | |
| 261 | /* MI Register 5: Auto-negotiation link partner advertisement register */ |
| 262 | typedef struct _MI_ANLPAR_t { |
| 263 | u16 value; |
| 264 | struct { |
| 265 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 266 | u16 np_indication:1; /* bit 15 */ |
| 267 | u16 acknowledge:1; /* bit 14 */ |
| 268 | u16 remote_fault:1; /* bit 13 */ |
| 269 | u16 res1:1; /* bit 12 */ |
| 270 | u16 cap_asmpause:1; /* bit 11 */ |
| 271 | u16 cap_pause:1; /* bit 10 */ |
| 272 | u16 cap_100T4:1; /* bit 9 */ |
| 273 | u16 cap_100fdx:1; /* bit 8 */ |
| 274 | u16 cap_100hdx:1; /* bit 7 */ |
| 275 | u16 cap_10fdx:1; /* bit 6 */ |
| 276 | u16 cap_10hdx:1; /* bit 5 */ |
| 277 | u16 selector:5; /* bits 0-4 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 278 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 279 | u16 selector:5; /* bits 0-4 */ |
| 280 | u16 cap_10hdx:1; /* bit 5 */ |
| 281 | u16 cap_10fdx:1; /* bit 6 */ |
| 282 | u16 cap_100hdx:1; /* bit 7 */ |
| 283 | u16 cap_100fdx:1; /* bit 8 */ |
| 284 | u16 cap_100T4:1; /* bit 9 */ |
| 285 | u16 cap_pause:1; /* bit 10 */ |
| 286 | u16 cap_asmpause:1; /* bit 11 */ |
| 287 | u16 res1:1; /* bit 12 */ |
| 288 | u16 remote_fault:1; /* bit 13 */ |
| 289 | u16 acknowledge:1; /* bit 14 */ |
| 290 | u16 np_indication:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 291 | #endif |
| 292 | } bits; |
| 293 | } MI_ANLPAR_t, *PMI_ANLPAR_t; |
| 294 | |
| 295 | /* MI Register 6: Auto-negotiation expansion register */ |
| 296 | typedef union _MI_ANER_t { |
| 297 | u16 value; |
| 298 | struct { |
| 299 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 300 | u16 res:11; /* bits 5-15 */ |
| 301 | u16 pdf:1; /* bit 4 */ |
| 302 | u16 lp_np_able:1; /* bit 3 */ |
| 303 | u16 np_able:1; /* bit 2 */ |
| 304 | u16 page_rx:1; /* bit 1 */ |
| 305 | u16 lp_an_able:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 306 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 307 | u16 lp_an_able:1; /* bit 0 */ |
| 308 | u16 page_rx:1; /* bit 1 */ |
| 309 | u16 np_able:1; /* bit 2 */ |
| 310 | u16 lp_np_able:1; /* bit 3 */ |
| 311 | u16 pdf:1; /* bit 4 */ |
| 312 | u16 res:11; /* bits 5-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 313 | #endif |
| 314 | } bits; |
| 315 | } MI_ANER_t, *PMI_ANER_t; |
| 316 | |
| 317 | /* MI Register 7: Auto-negotiation next page transmit reg(0x07) */ |
| 318 | typedef union _MI_ANNPTR_t { |
| 319 | u16 value; |
| 320 | struct { |
| 321 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 322 | u16 np:1; /* bit 15 */ |
| 323 | u16 res1:1; /* bit 14 */ |
| 324 | u16 msg_page:1; /* bit 13 */ |
| 325 | u16 ack2:1; /* bit 12 */ |
| 326 | u16 toggle:1; /* bit 11 */ |
| 327 | u16 msg:11; /* bits 0-10 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 328 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 329 | u16 msg:11; /* bits 0-10 */ |
| 330 | u16 toggle:1; /* bit 11 */ |
| 331 | u16 ack2:1; /* bit 12 */ |
| 332 | u16 msg_page:1; /* bit 13 */ |
| 333 | u16 res1:1; /* bit 14 */ |
| 334 | u16 np:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 335 | #endif |
| 336 | } bits; |
| 337 | } MI_ANNPTR_t, *PMI_ANNPTR_t; |
| 338 | |
| 339 | /* MI Register 8: Link Partner Next Page Reg(0x08) */ |
| 340 | typedef union _MI_LPNPR_t { |
| 341 | u16 value; |
| 342 | struct { |
| 343 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 344 | u16 np:1; /* bit 15 */ |
| 345 | u16 ack:1; /* bit 14 */ |
| 346 | u16 msg_page:1; /* bit 13 */ |
| 347 | u16 ack2:1; /* bit 12 */ |
| 348 | u16 toggle:1; /* bit 11 */ |
| 349 | u16 msg:11; /* bits 0-10 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 350 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 351 | u16 msg:11; /* bits 0-10 */ |
| 352 | u16 toggle:1; /* bit 11 */ |
| 353 | u16 ack2:1; /* bit 12 */ |
| 354 | u16 msg_page:1; /* bit 13 */ |
| 355 | u16 ack:1; /* bit 14 */ |
| 356 | u16 np:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 357 | #endif |
| 358 | } bits; |
| 359 | } MI_LPNPR_t, *PMI_LPNPR_t; |
| 360 | |
| 361 | /* MI Register 9: 1000BaseT Control Reg(0x09) */ |
| 362 | typedef union _MI_GCR_t { |
| 363 | u16 value; |
| 364 | struct { |
| 365 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 366 | u16 test_mode:3; /* bits 13-15 */ |
| 367 | u16 ms_config_en:1; /* bit 12 */ |
| 368 | u16 ms_value:1; /* bit 11 */ |
| 369 | u16 port_type:1; /* bit 10 */ |
| 370 | u16 link_1000fdx:1; /* bit 9 */ |
| 371 | u16 link_1000hdx:1; /* bit 8 */ |
| 372 | u16 res:8; /* bit 0-7 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 373 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 374 | u16 res:8; /* bit 0-7 */ |
| 375 | u16 link_1000hdx:1; /* bit 8 */ |
| 376 | u16 link_1000fdx:1; /* bit 9 */ |
| 377 | u16 port_type:1; /* bit 10 */ |
| 378 | u16 ms_value:1; /* bit 11 */ |
| 379 | u16 ms_config_en:1; /* bit 12 */ |
| 380 | u16 test_mode:3; /* bits 13-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 381 | #endif |
| 382 | } bits; |
| 383 | } MI_GCR_t, *PMI_GCR_t; |
| 384 | |
| 385 | /* MI Register 10: 1000BaseT Status Reg(0x0A) */ |
| 386 | typedef union _MI_GSR_t { |
| 387 | u16 value; |
| 388 | struct { |
| 389 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 390 | u16 ms_config_fault:1; /* bit 15 */ |
| 391 | u16 ms_resolve:1; /* bit 14 */ |
| 392 | u16 local_rx_status:1; /* bit 13 */ |
| 393 | u16 remote_rx_status:1; /* bit 12 */ |
| 394 | u16 link_1000fdx:1; /* bit 11 */ |
| 395 | u16 link_1000hdx:1; /* bit 10 */ |
| 396 | u16 res:2; /* bits 8-9 */ |
| 397 | u16 idle_err_cnt:8; /* bits 0-7 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 398 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 399 | u16 idle_err_cnt:8; /* bits 0-7 */ |
| 400 | u16 res:2; /* bits 8-9 */ |
| 401 | u16 link_1000hdx:1; /* bit 10 */ |
| 402 | u16 link_1000fdx:1; /* bit 11 */ |
| 403 | u16 remote_rx_status:1; /* bit 12 */ |
| 404 | u16 local_rx_status:1; /* bit 13 */ |
| 405 | u16 ms_resolve:1; /* bit 14 */ |
| 406 | u16 ms_config_fault:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 407 | #endif |
| 408 | } bits; |
| 409 | } MI_GSR_t, *PMI_GSR_t; |
| 410 | |
| 411 | /* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */ |
| 412 | typedef union _MI_RES_t { |
| 413 | u16 value; |
| 414 | struct { |
| 415 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 416 | u16 res15:1; /* bit 15 */ |
| 417 | u16 res14:1; /* bit 14 */ |
| 418 | u16 res13:1; /* bit 13 */ |
| 419 | u16 res12:1; /* bit 12 */ |
| 420 | u16 res11:1; /* bit 11 */ |
| 421 | u16 res10:1; /* bit 10 */ |
| 422 | u16 res9:1; /* bit 9 */ |
| 423 | u16 res8:1; /* bit 8 */ |
| 424 | u16 res7:1; /* bit 7 */ |
| 425 | u16 res6:1; /* bit 6 */ |
| 426 | u16 res5:1; /* bit 5 */ |
| 427 | u16 res4:1; /* bit 4 */ |
| 428 | u16 res3:1; /* bit 3 */ |
| 429 | u16 res2:1; /* bit 2 */ |
| 430 | u16 res1:1; /* bit 1 */ |
| 431 | u16 res0:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 432 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 433 | u16 res0:1; /* bit 0 */ |
| 434 | u16 res1:1; /* bit 1 */ |
| 435 | u16 res2:1; /* bit 2 */ |
| 436 | u16 res3:1; /* bit 3 */ |
| 437 | u16 res4:1; /* bit 4 */ |
| 438 | u16 res5:1; /* bit 5 */ |
| 439 | u16 res6:1; /* bit 6 */ |
| 440 | u16 res7:1; /* bit 7 */ |
| 441 | u16 res8:1; /* bit 8 */ |
| 442 | u16 res9:1; /* bit 9 */ |
| 443 | u16 res10:1; /* bit 10 */ |
| 444 | u16 res11:1; /* bit 11 */ |
| 445 | u16 res12:1; /* bit 12 */ |
| 446 | u16 res13:1; /* bit 13 */ |
| 447 | u16 res14:1; /* bit 14 */ |
| 448 | u16 res15:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 449 | #endif |
| 450 | } bits; |
| 451 | } MI_RES_t, *PMI_RES_t; |
| 452 | |
| 453 | /* MI Register 15: Extended status Reg(0x0F) */ |
| 454 | typedef union _MI_ESR_t { |
| 455 | u16 value; |
| 456 | struct { |
| 457 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 458 | u16 link_1000Xfdx:1; /* bit 15 */ |
| 459 | u16 link_1000Xhdx:1; /* bit 14 */ |
| 460 | u16 link_1000fdx:1; /* bit 13 */ |
| 461 | u16 link_1000hdx:1; /* bit 12 */ |
| 462 | u16 res:12; /* bit 0-11 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 463 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 464 | u16 res:12; /* bit 0-11 */ |
| 465 | u16 link_1000hdx:1; /* bit 12 */ |
| 466 | u16 link_1000fdx:1; /* bit 13 */ |
| 467 | u16 link_1000Xhdx:1; /* bit 14 */ |
| 468 | u16 link_1000Xfdx:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 469 | #endif |
| 470 | } bits; |
| 471 | } MI_ESR_t, *PMI_ESR_t; |
| 472 | |
| 473 | /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */ |
| 474 | |
| 475 | /* MI Register 19: Loopback Control Reg(0x13) */ |
| 476 | typedef union _MI_LCR_t { |
| 477 | u16 value; |
| 478 | struct { |
| 479 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 480 | u16 mii_en:1; /* bit 15 */ |
| 481 | u16 pcs_en:1; /* bit 14 */ |
| 482 | u16 pmd_en:1; /* bit 13 */ |
| 483 | u16 all_digital_en:1; /* bit 12 */ |
| 484 | u16 replica_en:1; /* bit 11 */ |
| 485 | u16 line_driver_en:1; /* bit 10 */ |
| 486 | u16 res:10; /* bit 0-9 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 487 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 488 | u16 res:10; /* bit 0-9 */ |
| 489 | u16 line_driver_en:1; /* bit 10 */ |
| 490 | u16 replica_en:1; /* bit 11 */ |
| 491 | u16 all_digital_en:1; /* bit 12 */ |
| 492 | u16 pmd_en:1; /* bit 13 */ |
| 493 | u16 pcs_en:1; /* bit 14 */ |
| 494 | u16 mii_en:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 495 | #endif |
| 496 | } bits; |
| 497 | } MI_LCR_t, *PMI_LCR_t; |
| 498 | |
| 499 | /* MI Register 20: Reserved Reg(0x14) */ |
| 500 | |
| 501 | /* MI Register 21: Management Interface Control Reg(0x15) */ |
| 502 | typedef union _MI_MICR_t { |
| 503 | u16 value; |
| 504 | struct { |
| 505 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 506 | u16 res1:5; /* bits 11-15 */ |
| 507 | u16 mi_error_count:7; /* bits 4-10 */ |
| 508 | u16 res2:1; /* bit 3 */ |
| 509 | u16 ignore_10g_fr:1; /* bit 2 */ |
| 510 | u16 res3:1; /* bit 1 */ |
| 511 | u16 preamble_supress_en:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 512 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 513 | u16 preamble_supress_en:1; /* bit 0 */ |
| 514 | u16 res3:1; /* bit 1 */ |
| 515 | u16 ignore_10g_fr:1; /* bit 2 */ |
| 516 | u16 res2:1; /* bit 3 */ |
| 517 | u16 mi_error_count:7; /* bits 4-10 */ |
| 518 | u16 res1:5; /* bits 11-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 519 | #endif |
| 520 | } bits; |
| 521 | } MI_MICR_t, *PMI_MICR_t; |
| 522 | |
| 523 | /* MI Register 22: PHY Configuration Reg(0x16) */ |
| 524 | typedef union _MI_PHY_CONFIG_t { |
| 525 | u16 value; |
| 526 | struct { |
| 527 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 528 | u16 crs_tx_en:1; /* bit 15 */ |
| 529 | u16 res1:1; /* bit 14 */ |
| 530 | u16 tx_fifo_depth:2; /* bits 12-13 */ |
| 531 | u16 speed_downshift:2; /* bits 10-11 */ |
| 532 | u16 pbi_detect:1; /* bit 9 */ |
| 533 | u16 tbi_rate:1; /* bit 8 */ |
| 534 | u16 alternate_np:1; /* bit 7 */ |
| 535 | u16 group_mdio_en:1; /* bit 6 */ |
| 536 | u16 tx_clock_en:1; /* bit 5 */ |
| 537 | u16 sys_clock_en:1; /* bit 4 */ |
| 538 | u16 res2:1; /* bit 3 */ |
| 539 | u16 mac_if_mode:3; /* bits 0-2 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 540 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 541 | u16 mac_if_mode:3; /* bits 0-2 */ |
| 542 | u16 res2:1; /* bit 3 */ |
| 543 | u16 sys_clock_en:1; /* bit 4 */ |
| 544 | u16 tx_clock_en:1; /* bit 5 */ |
| 545 | u16 group_mdio_en:1; /* bit 6 */ |
| 546 | u16 alternate_np:1; /* bit 7 */ |
| 547 | u16 tbi_rate:1; /* bit 8 */ |
| 548 | u16 pbi_detect:1; /* bit 9 */ |
| 549 | u16 speed_downshift:2; /* bits 10-11 */ |
| 550 | u16 tx_fifo_depth:2; /* bits 12-13 */ |
| 551 | u16 res1:1; /* bit 14 */ |
| 552 | u16 crs_tx_en:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 553 | #endif |
| 554 | } bits; |
| 555 | } MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t; |
| 556 | |
| 557 | /* MI Register 23: PHY CONTROL Reg(0x17) */ |
| 558 | typedef union _MI_PHY_CONTROL_t { |
| 559 | u16 value; |
| 560 | struct { |
| 561 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 562 | u16 res1:1; /* bit 15 */ |
| 563 | u16 tdr_en:1; /* bit 14 */ |
| 564 | u16 res2:1; /* bit 13 */ |
| 565 | u16 downshift_attempts:2; /* bits 11-12 */ |
| 566 | u16 res3:5; /* bit 6-10 */ |
| 567 | u16 jabber_10baseT:1; /* bit 5 */ |
| 568 | u16 sqe_10baseT:1; /* bit 4 */ |
| 569 | u16 tp_loopback_10baseT:1; /* bit 3 */ |
| 570 | u16 preamble_gen_en:1; /* bit 2 */ |
| 571 | u16 res4:1; /* bit 1 */ |
| 572 | u16 force_int:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 573 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 574 | u16 force_int:1; /* bit 0 */ |
| 575 | u16 res4:1; /* bit 1 */ |
| 576 | u16 preamble_gen_en:1; /* bit 2 */ |
| 577 | u16 tp_loopback_10baseT:1; /* bit 3 */ |
| 578 | u16 sqe_10baseT:1; /* bit 4 */ |
| 579 | u16 jabber_10baseT:1; /* bit 5 */ |
| 580 | u16 res3:5; /* bit 6-10 */ |
| 581 | u16 downshift_attempts:2; /* bits 11-12 */ |
| 582 | u16 res2:1; /* bit 13 */ |
| 583 | u16 tdr_en:1; /* bit 14 */ |
| 584 | u16 res1:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 585 | #endif |
| 586 | } bits; |
| 587 | } MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t; |
| 588 | |
| 589 | /* MI Register 24: Interrupt Mask Reg(0x18) */ |
| 590 | typedef union _MI_IMR_t { |
| 591 | u16 value; |
| 592 | struct { |
| 593 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 594 | u16 res1:6; /* bits 10-15 */ |
| 595 | u16 mdio_sync_lost:1; /* bit 9 */ |
| 596 | u16 autoneg_status:1; /* bit 8 */ |
| 597 | u16 hi_bit_err:1; /* bit 7 */ |
| 598 | u16 np_rx:1; /* bit 6 */ |
| 599 | u16 err_counter_full:1; /* bit 5 */ |
| 600 | u16 fifo_over_underflow:1; /* bit 4 */ |
| 601 | u16 rx_status:1; /* bit 3 */ |
| 602 | u16 link_status:1; /* bit 2 */ |
| 603 | u16 automatic_speed:1; /* bit 1 */ |
| 604 | u16 int_en:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 605 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 606 | u16 int_en:1; /* bit 0 */ |
| 607 | u16 automatic_speed:1; /* bit 1 */ |
| 608 | u16 link_status:1; /* bit 2 */ |
| 609 | u16 rx_status:1; /* bit 3 */ |
| 610 | u16 fifo_over_underflow:1; /* bit 4 */ |
| 611 | u16 err_counter_full:1; /* bit 5 */ |
| 612 | u16 np_rx:1; /* bit 6 */ |
| 613 | u16 hi_bit_err:1; /* bit 7 */ |
| 614 | u16 autoneg_status:1; /* bit 8 */ |
| 615 | u16 mdio_sync_lost:1; /* bit 9 */ |
| 616 | u16 res1:6; /* bits 10-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 617 | #endif |
| 618 | } bits; |
| 619 | } MI_IMR_t, *PMI_IMR_t; |
| 620 | |
| 621 | /* MI Register 25: Interrupt Status Reg(0x19) */ |
| 622 | typedef union _MI_ISR_t { |
| 623 | u16 value; |
| 624 | struct { |
| 625 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 626 | u16 res1:6; /* bits 10-15 */ |
| 627 | u16 mdio_sync_lost:1; /* bit 9 */ |
| 628 | u16 autoneg_status:1; /* bit 8 */ |
| 629 | u16 hi_bit_err:1; /* bit 7 */ |
| 630 | u16 np_rx:1; /* bit 6 */ |
| 631 | u16 err_counter_full:1; /* bit 5 */ |
| 632 | u16 fifo_over_underflow:1; /* bit 4 */ |
| 633 | u16 rx_status:1; /* bit 3 */ |
| 634 | u16 link_status:1; /* bit 2 */ |
| 635 | u16 automatic_speed:1; /* bit 1 */ |
| 636 | u16 int_en:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 637 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 638 | u16 int_en:1; /* bit 0 */ |
| 639 | u16 automatic_speed:1; /* bit 1 */ |
| 640 | u16 link_status:1; /* bit 2 */ |
| 641 | u16 rx_status:1; /* bit 3 */ |
| 642 | u16 fifo_over_underflow:1; /* bit 4 */ |
| 643 | u16 err_counter_full:1; /* bit 5 */ |
| 644 | u16 np_rx:1; /* bit 6 */ |
| 645 | u16 hi_bit_err:1; /* bit 7 */ |
| 646 | u16 autoneg_status:1; /* bit 8 */ |
| 647 | u16 mdio_sync_lost:1; /* bit 9 */ |
| 648 | u16 res1:6; /* bits 10-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 649 | #endif |
| 650 | } bits; |
| 651 | } MI_ISR_t, *PMI_ISR_t; |
| 652 | |
| 653 | /* MI Register 26: PHY Status Reg(0x1A) */ |
| 654 | typedef union _MI_PSR_t { |
| 655 | u16 value; |
| 656 | struct { |
| 657 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 658 | u16 res1:1; /* bit 15 */ |
| 659 | u16 autoneg_fault:2; /* bit 13-14 */ |
| 660 | u16 autoneg_status:1; /* bit 12 */ |
| 661 | u16 mdi_x_status:1; /* bit 11 */ |
| 662 | u16 polarity_status:1; /* bit 10 */ |
| 663 | u16 speed_status:2; /* bits 8-9 */ |
| 664 | u16 duplex_status:1; /* bit 7 */ |
| 665 | u16 link_status:1; /* bit 6 */ |
| 666 | u16 tx_status:1; /* bit 5 */ |
| 667 | u16 rx_status:1; /* bit 4 */ |
| 668 | u16 collision_status:1; /* bit 3 */ |
| 669 | u16 autoneg_en:1; /* bit 2 */ |
| 670 | u16 pause_en:1; /* bit 1 */ |
| 671 | u16 asymmetric_dir:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 672 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 673 | u16 asymmetric_dir:1; /* bit 0 */ |
| 674 | u16 pause_en:1; /* bit 1 */ |
| 675 | u16 autoneg_en:1; /* bit 2 */ |
| 676 | u16 collision_status:1; /* bit 3 */ |
| 677 | u16 rx_status:1; /* bit 4 */ |
| 678 | u16 tx_status:1; /* bit 5 */ |
| 679 | u16 link_status:1; /* bit 6 */ |
| 680 | u16 duplex_status:1; /* bit 7 */ |
| 681 | u16 speed_status:2; /* bits 8-9 */ |
| 682 | u16 polarity_status:1; /* bit 10 */ |
| 683 | u16 mdi_x_status:1; /* bit 11 */ |
| 684 | u16 autoneg_status:1; /* bit 12 */ |
| 685 | u16 autoneg_fault:2; /* bit 13-14 */ |
| 686 | u16 res1:1; /* bit 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 687 | #endif |
| 688 | } bits; |
| 689 | } MI_PSR_t, *PMI_PSR_t; |
| 690 | |
| 691 | /* MI Register 27: LED Control Reg 1(0x1B) */ |
| 692 | typedef union _MI_LCR1_t { |
| 693 | u16 value; |
| 694 | struct { |
| 695 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 696 | u16 res1:2; /* bits 14-15 */ |
| 697 | u16 led_dup_indicate:2; /* bits 12-13 */ |
| 698 | u16 led_10baseT:2; /* bits 10-11 */ |
| 699 | u16 led_collision:2; /* bits 8-9 */ |
| 700 | u16 res2:2; /* bits 6-7 */ |
| 701 | u16 res3:2; /* bits 4-5 */ |
| 702 | u16 pulse_dur:2; /* bits 2-3 */ |
| 703 | u16 pulse_stretch1:1; /* bit 1 */ |
| 704 | u16 pulse_stretch0:1; /* bit 0 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 705 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 706 | u16 pulse_stretch0:1; /* bit 0 */ |
| 707 | u16 pulse_stretch1:1; /* bit 1 */ |
| 708 | u16 pulse_dur:2; /* bits 2-3 */ |
| 709 | u16 res3:2; /* bits 4-5 */ |
| 710 | u16 res2:2; /* bits 6-7 */ |
| 711 | u16 led_collision:2; /* bits 8-9 */ |
| 712 | u16 led_10baseT:2; /* bits 10-11 */ |
| 713 | u16 led_dup_indicate:2; /* bits 12-13 */ |
| 714 | u16 res1:2; /* bits 14-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 715 | #endif |
| 716 | } bits; |
| 717 | } MI_LCR1_t, *PMI_LCR1_t; |
| 718 | |
| 719 | /* MI Register 28: LED Control Reg 2(0x1C) */ |
| 720 | typedef union _MI_LCR2_t { |
| 721 | u16 value; |
| 722 | struct { |
| 723 | #ifdef _BIT_FIELDS_HTOL |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 724 | u16 led_link:4; /* bits 12-15 */ |
| 725 | u16 led_tx_rx:4; /* bits 8-11 */ |
| 726 | u16 led_100BaseTX:4; /* bits 4-7 */ |
| 727 | u16 led_1000BaseT:4; /* bits 0-3 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 728 | #else |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 729 | u16 led_1000BaseT:4; /* bits 0-3 */ |
| 730 | u16 led_100BaseTX:4; /* bits 4-7 */ |
| 731 | u16 led_tx_rx:4; /* bits 8-11 */ |
| 732 | u16 led_link:4; /* bits 12-15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 733 | #endif |
| 734 | } bits; |
| 735 | } MI_LCR2_t, *PMI_LCR2_t; |
| 736 | |
| 737 | /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */ |
| 738 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 739 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 740 | /* Prototypes for ET1310_phy.c */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 741 | /* Defines for PHY access routines */ |
| 742 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 743 | /* Define bit operation flags */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 744 | #define TRUEPHY_BIT_CLEAR 0 |
| 745 | #define TRUEPHY_BIT_SET 1 |
| 746 | #define TRUEPHY_BIT_READ 2 |
| 747 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 748 | /* Define read/write operation flags */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 749 | #ifndef TRUEPHY_READ |
| 750 | #define TRUEPHY_READ 0 |
| 751 | #define TRUEPHY_WRITE 1 |
| 752 | #define TRUEPHY_MASK 2 |
| 753 | #endif |
| 754 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 755 | /* Define speeds */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 756 | #define TRUEPHY_SPEED_10MBPS 0 |
| 757 | #define TRUEPHY_SPEED_100MBPS 1 |
| 758 | #define TRUEPHY_SPEED_1000MBPS 2 |
| 759 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 760 | /* Define duplex modes */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 761 | #define TRUEPHY_DUPLEX_HALF 0 |
| 762 | #define TRUEPHY_DUPLEX_FULL 1 |
| 763 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 764 | /* Define master/slave configuration values */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 765 | #define TRUEPHY_CFG_SLAVE 0 |
| 766 | #define TRUEPHY_CFG_MASTER 1 |
| 767 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 768 | /* Define MDI/MDI-X settings */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 769 | #define TRUEPHY_MDI 0 |
| 770 | #define TRUEPHY_MDIX 1 |
| 771 | #define TRUEPHY_AUTO_MDI_MDIX 2 |
| 772 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 773 | /* Define 10Base-T link polarities */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 774 | #define TRUEPHY_POLARITY_NORMAL 0 |
| 775 | #define TRUEPHY_POLARITY_INVERTED 1 |
| 776 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 777 | /* Define auto-negotiation results */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 778 | #define TRUEPHY_ANEG_NOT_COMPLETE 0 |
| 779 | #define TRUEPHY_ANEG_COMPLETE 1 |
| 780 | #define TRUEPHY_ANEG_DISABLED 2 |
| 781 | |
| 782 | /* Define duplex advertisment flags */ |
| 783 | #define TRUEPHY_ADV_DUPLEX_NONE 0x00 |
| 784 | #define TRUEPHY_ADV_DUPLEX_FULL 0x01 |
| 785 | #define TRUEPHY_ADV_DUPLEX_HALF 0x02 |
| 786 | #define TRUEPHY_ADV_DUPLEX_BOTH \ |
| 787 | (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF) |
| 788 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 789 | #define PHY_CONTROL 0x00 /* #define TRU_MI_CONTROL_REGISTER 0 */ |
| 790 | #define PHY_STATUS 0x01 /* #define TRU_MI_STATUS_REGISTER 1 */ |
| 791 | #define PHY_ID_1 0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2 */ |
| 792 | #define PHY_ID_2 0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3 */ |
| 793 | #define PHY_AUTO_ADVERTISEMENT 0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER 4 */ |
| 794 | #define PHY_AUTO_LINK_PARTNER 0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5 */ |
| 795 | #define PHY_AUTO_EXPANSION 0x06 /* #define TRU_MI_EXPANSION_REGISTER 6 */ |
| 796 | #define PHY_AUTO_NEXT_PAGE_TX 0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7 */ |
| 797 | #define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8 */ |
| 798 | #define PHY_1000_CONTROL 0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER 9 */ |
| 799 | #define PHY_1000_STATUS 0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER 10 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 800 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 801 | #define PHY_EXTENDED_STATUS 0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER 15 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 802 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 803 | /* some defines for modem registers that seem to be 'reserved' */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 804 | #define PHY_INDEX_REG 0x10 |
| 805 | #define PHY_DATA_REG 0x11 |
| 806 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 807 | #define PHY_MPHY_CONTROL_REG 0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER 18 */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 808 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 809 | #define PHY_LOOPBACK_CONTROL 0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19 */ |
| 810 | /* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20 */ |
| 811 | #define PHY_REGISTER_MGMT_CONTROL 0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21 */ |
| 812 | #define PHY_CONFIG 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER 22 */ |
| 813 | #define PHY_PHY_CONTROL 0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER 23 */ |
| 814 | #define PHY_INTERRUPT_MASK 0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER 24 */ |
| 815 | #define PHY_INTERRUPT_STATUS 0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER 25 */ |
| 816 | #define PHY_PHY_STATUS 0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER 26 */ |
| 817 | #define PHY_LED_1 0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER 27 */ |
| 818 | #define PHY_LED_2 0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER 28 */ |
| 819 | /* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */ |
| 820 | /* #define TRU_VMI_TIMING_CONTROL_REGISTER */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 821 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 822 | #endif /* _ET1310_PHY_H_ */ |