Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. |
| 3 | * Linux device driver for RTL8192U |
| 4 | * |
| 5 | * Based on the r8187 driver, which is: |
| 6 | * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of version 2 of the GNU General Public License as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA |
| 19 | * |
| 20 | * The full GNU General Public License is included in this distribution in the |
| 21 | * file called LICENSE. |
| 22 | * |
| 23 | * Contact Information: |
| 24 | * wlanfae <wlanfae@realtek.com> |
| 25 | ******************************************************************************/ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 26 | |
| 27 | #ifndef R819xU_H |
| 28 | #define R819xU_H |
| 29 | |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/kernel.h> |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 32 | #include <linux/init.h> |
| 33 | #include <linux/ioport.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/types.h> |
| 36 | #include <linux/slab.h> |
| 37 | #include <linux/netdevice.h> |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 38 | #include <linux/usb.h> |
| 39 | #include <linux/etherdevice.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/rtnetlink.h> //for rtnl_lock() |
| 42 | #include <linux/wireless.h> |
| 43 | #include <linux/timer.h> |
| 44 | #include <linux/proc_fs.h> // Necessary because we use the proc fs |
| 45 | #include <linux/if_arp.h> |
| 46 | #include <linux/random.h> |
| 47 | #include <linux/version.h> |
| 48 | #include <asm/io.h> |
Bartlomiej Zolnierkiewicz | 1ec9e48 | 2009-06-13 18:35:04 +0200 | [diff] [blame] | 49 | |
Bartlomiej Zolnierkiewicz | 2a7d71a | 2009-06-12 18:29:19 +0200 | [diff] [blame] | 50 | #include "ieee80211/ieee80211.h" |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 51 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 52 | #include "r8192S_firmware.h" |
Florian Schilhabel | 5c2af91 | 2010-05-13 13:55:25 +0200 | [diff] [blame] | 53 | #include "r8192SU_led.h" |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 54 | |
Florian Schilhabel | e3133b2 | 2010-03-06 20:44:33 +0100 | [diff] [blame] | 55 | /* EEPROM defs for use with linux/eeprom_93cx6.h */ |
| 56 | #define RTL819X_EEPROM_CMD_READ (1 << 0) |
| 57 | #define RTL819X_EEPROM_CMD_WRITE (1 << 1) |
| 58 | #define RTL819X_EEPROM_CMD_CK (1 << 2) |
| 59 | #define RTL819X_EEPROM_CMD_CS (1 << 3) |
| 60 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 61 | #define RTL819xU_MODULE_NAME "rtl819xU" |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 62 | #define FALSE 0 |
| 63 | #define TRUE 1 |
| 64 | #define MAX_KEY_LEN 61 |
| 65 | #define KEY_BUF_SIZE 5 |
| 66 | |
| 67 | #define BIT0 0x00000001 |
| 68 | #define BIT1 0x00000002 |
| 69 | #define BIT2 0x00000004 |
| 70 | #define BIT3 0x00000008 |
| 71 | #define BIT4 0x00000010 |
| 72 | #define BIT5 0x00000020 |
| 73 | #define BIT6 0x00000040 |
| 74 | #define BIT7 0x00000080 |
| 75 | #define BIT8 0x00000100 |
| 76 | #define BIT9 0x00000200 |
| 77 | #define BIT10 0x00000400 |
| 78 | #define BIT11 0x00000800 |
| 79 | #define BIT12 0x00001000 |
| 80 | #define BIT13 0x00002000 |
| 81 | #define BIT14 0x00004000 |
| 82 | #define BIT15 0x00008000 |
| 83 | #define BIT16 0x00010000 |
| 84 | #define BIT17 0x00020000 |
| 85 | #define BIT18 0x00040000 |
| 86 | #define BIT19 0x00080000 |
| 87 | #define BIT20 0x00100000 |
| 88 | #define BIT21 0x00200000 |
| 89 | #define BIT22 0x00400000 |
| 90 | #define BIT23 0x00800000 |
| 91 | #define BIT24 0x01000000 |
| 92 | #define BIT25 0x02000000 |
| 93 | #define BIT26 0x04000000 |
| 94 | #define BIT27 0x08000000 |
| 95 | #define BIT28 0x10000000 |
| 96 | #define BIT29 0x20000000 |
| 97 | #define BIT30 0x40000000 |
| 98 | #define BIT31 0x80000000 |
| 99 | |
| 100 | // Rx smooth factor |
| 101 | #define Rx_Smooth_Factor 20 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 102 | #define DMESG(x,a...) |
| 103 | #define DMESGW(x,a...) |
| 104 | #define DMESGE(x,a...) |
| 105 | extern u32 rt_global_debug_component; |
| 106 | #define RT_TRACE(component, x, args...) \ |
| 107 | do { if(rt_global_debug_component & component) \ |
| 108 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \ |
| 109 | ##args);\ |
| 110 | }while(0); |
| 111 | //---------------------------------------------------------------------- |
| 112 | //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15. |
| 113 | ////---------------------------------------------------------------------- |
| 114 | #define RX_DESC_SIZE 24 |
| 115 | #define RX_DRV_INFO_SIZE_UNIT 8 |
| 116 | |
| 117 | #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\ |
| 118 | (_ieee->pairwise_key_type==KEY_TYPE_CCMP)) |
| 119 | |
| 120 | #define COMP_TRACE BIT0 // For function call tracing. |
| 121 | #define COMP_DBG BIT1 // Only for temporary debug message. |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 122 | #define COMP_MLME BIT1 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 123 | #define COMP_INIT BIT2 // during driver initialization / halt / reset. |
| 124 | |
| 125 | |
| 126 | #define COMP_RECV BIT3 // Reveive part data path. |
| 127 | #define COMP_SEND BIT4 // Send part path. |
| 128 | #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02. |
| 129 | #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related. |
| 130 | #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS. |
| 131 | #define COMP_SWBW BIT8 // For bandwidth switch. |
| 132 | #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING |
| 133 | #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21. |
| 134 | #define COMP_QOS BIT11 // For QoS. |
| 135 | #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. |
| 136 | #define COMP_LPS BIT13 // For Radio Measurement. |
| 137 | #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko. |
| 138 | #define COMP_PHY BIT15 |
| 139 | #define COMP_CH BIT16 //channel setting debug |
| 140 | #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko. |
| 141 | #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko. |
| 142 | #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko. |
| 143 | #define COMP_SEC BIT20 // Event handling |
| 144 | #define COMP_LED BIT21 // For LED. |
| 145 | #define COMP_RF BIT22 // For RF. |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 146 | #define COMP_RXDESC BIT23 |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 147 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 148 | #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 149 | |
| 150 | #define COMP_FIRMWARE BIT24 //for firmware downloading |
| 151 | #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11 |
| 152 | #define COMP_AMSDU BIT26 // For A-MSDU Debugging |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 153 | #define COMP_PS BIT26 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 154 | |
| 155 | #define COMP_SCAN BIT27 |
| 156 | #define COMP_CMD BIT28 |
| 157 | #define COMP_DOWN BIT29 //for rm driver module |
| 158 | #define COMP_RESET BIT30 //for silent reset |
| 159 | #define COMP_ERR BIT31 //for error out, always on |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 160 | |
| 161 | #define RTL819x_DEBUG |
| 162 | #ifdef RTL819x_DEBUG |
| 163 | #define assert(expr) \ |
| 164 | if (!(expr)) { \ |
| 165 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
| 166 | #expr,__FILE__,__FUNCTION__,__LINE__); \ |
| 167 | } |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 168 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 169 | #define RT_DEBUG_DATA(level, data, datalen) \ |
| 170 | do{ if ((rt_global_debug_component & (level)) == (level)) \ |
| 171 | { \ |
| 172 | int i; \ |
| 173 | u8* pdata = (u8*) data; \ |
| 174 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ |
| 175 | for(i=0; i<(int)(datalen); i++) \ |
| 176 | { \ |
| 177 | printk("%2x ", pdata[i]); \ |
| 178 | if ((i+1)%16 == 0) printk("\n"); \ |
| 179 | } \ |
| 180 | printk("\n"); \ |
| 181 | } \ |
| 182 | } while (0) |
| 183 | #else |
| 184 | #define assert(expr) do {} while (0) |
| 185 | #define RT_DEBUG_DATA(level, data, datalen) do {} while(0) |
| 186 | #endif /* RTL8169_DEBUG */ |
| 187 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 188 | //2TODO: We should define 8192S firmware related macro settings here!! |
| 189 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R |
| 190 | #define RTL819X_TOTAL_RF_PATH 2 |
| 191 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 192 | #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG |
| 193 | #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array |
| 194 | #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray |
| 195 | #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 196 | #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array |
| 197 | #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array |
| 198 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 199 | #define Rtl819XFwImageArray Rtl8192SUFwImgArray |
| 200 | #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array |
| 201 | #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array |
| 202 | #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray |
| 203 | #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray |
| 204 | #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray |
| 205 | #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray |
| 206 | #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG |
| 207 | #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array |
| 208 | #define Rtl819XRadioB_Array Rtl8192SURadioB_Array |
| 209 | #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array |
| 210 | #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array |
| 211 | #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 212 | // |
| 213 | // Queue Select Value in TxDesc |
| 214 | // |
| 215 | #define QSLT_BK 0x1 |
| 216 | #define QSLT_BE 0x0 |
| 217 | #define QSLT_VI 0x4 |
| 218 | #define QSLT_VO 0x6 |
| 219 | #define QSLT_BEACON 0x10 |
| 220 | #define QSLT_HIGH 0x11 |
| 221 | #define QSLT_MGNT 0x12 |
| 222 | #define QSLT_CMD 0x13 |
| 223 | |
| 224 | #define DESC90_RATE1M 0x00 |
| 225 | #define DESC90_RATE2M 0x01 |
| 226 | #define DESC90_RATE5_5M 0x02 |
| 227 | #define DESC90_RATE11M 0x03 |
| 228 | #define DESC90_RATE6M 0x04 |
| 229 | #define DESC90_RATE9M 0x05 |
| 230 | #define DESC90_RATE12M 0x06 |
| 231 | #define DESC90_RATE18M 0x07 |
| 232 | #define DESC90_RATE24M 0x08 |
| 233 | #define DESC90_RATE36M 0x09 |
| 234 | #define DESC90_RATE48M 0x0a |
| 235 | #define DESC90_RATE54M 0x0b |
| 236 | #define DESC90_RATEMCS0 0x00 |
| 237 | #define DESC90_RATEMCS1 0x01 |
| 238 | #define DESC90_RATEMCS2 0x02 |
| 239 | #define DESC90_RATEMCS3 0x03 |
| 240 | #define DESC90_RATEMCS4 0x04 |
| 241 | #define DESC90_RATEMCS5 0x05 |
| 242 | #define DESC90_RATEMCS6 0x06 |
| 243 | #define DESC90_RATEMCS7 0x07 |
| 244 | #define DESC90_RATEMCS8 0x08 |
| 245 | #define DESC90_RATEMCS9 0x09 |
| 246 | #define DESC90_RATEMCS10 0x0a |
| 247 | #define DESC90_RATEMCS11 0x0b |
| 248 | #define DESC90_RATEMCS12 0x0c |
| 249 | #define DESC90_RATEMCS13 0x0d |
| 250 | #define DESC90_RATEMCS14 0x0e |
| 251 | #define DESC90_RATEMCS15 0x0f |
| 252 | #define DESC90_RATEMCS32 0x20 |
| 253 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 254 | // CCK Rates, TxHT = 0 |
| 255 | #define DESC92S_RATE1M 0x00 |
| 256 | #define DESC92S_RATE2M 0x01 |
| 257 | #define DESC92S_RATE5_5M 0x02 |
| 258 | #define DESC92S_RATE11M 0x03 |
| 259 | |
| 260 | // OFDM Rates, TxHT = 0 |
| 261 | #define DESC92S_RATE6M 0x04 |
| 262 | #define DESC92S_RATE9M 0x05 |
| 263 | #define DESC92S_RATE12M 0x06 |
| 264 | #define DESC92S_RATE18M 0x07 |
| 265 | #define DESC92S_RATE24M 0x08 |
| 266 | #define DESC92S_RATE36M 0x09 |
| 267 | #define DESC92S_RATE48M 0x0a |
| 268 | #define DESC92S_RATE54M 0x0b |
| 269 | |
| 270 | // MCS Rates, TxHT = 1 |
| 271 | #define DESC92S_RATEMCS0 0x0c |
| 272 | #define DESC92S_RATEMCS1 0x0d |
| 273 | #define DESC92S_RATEMCS2 0x0e |
| 274 | #define DESC92S_RATEMCS3 0x0f |
| 275 | #define DESC92S_RATEMCS4 0x10 |
| 276 | #define DESC92S_RATEMCS5 0x11 |
| 277 | #define DESC92S_RATEMCS6 0x12 |
| 278 | #define DESC92S_RATEMCS7 0x13 |
| 279 | #define DESC92S_RATEMCS8 0x14 |
| 280 | #define DESC92S_RATEMCS9 0x15 |
| 281 | #define DESC92S_RATEMCS10 0x16 |
| 282 | #define DESC92S_RATEMCS11 0x17 |
| 283 | #define DESC92S_RATEMCS12 0x18 |
| 284 | #define DESC92S_RATEMCS13 0x19 |
| 285 | #define DESC92S_RATEMCS14 0x1a |
| 286 | #define DESC92S_RATEMCS15 0x1b |
| 287 | #define DESC92S_RATEMCS15_SG 0x1c |
| 288 | #define DESC92S_RATEMCS32 0x20 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 289 | |
| 290 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R |
| 291 | |
| 292 | #define IEEE80211_WATCH_DOG_TIME 2000 |
| 293 | #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 294 | //for txpowertracking |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 295 | #define OFDM_Table_Length 19 |
| 296 | #define CCK_Table_length 12 |
| 297 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 298 | // |
| 299 | //Tx Descriptor for RLT8192SU(Normal mode) |
| 300 | // |
| 301 | typedef struct _tx_desc_819x_usb { |
| 302 | // DWORD 0 |
| 303 | u16 PktSize;//:16; |
| 304 | u8 Offset;//:8; |
| 305 | u8 Type:2; // Reserved for MAC header Frame Type subfield. |
| 306 | u8 LastSeg:1; |
| 307 | u8 FirstSeg:1; |
| 308 | u8 LINIP:1; |
| 309 | u8 AMSDU:1; |
| 310 | u8 GF:1; |
| 311 | u8 OWN:1; |
| 312 | |
| 313 | // DWORD 1 |
| 314 | u8 MacID:5; |
| 315 | u8 MoreData:1; |
| 316 | u8 MOREFRAG:1; |
| 317 | u8 PIFS:1; |
| 318 | u8 QueueSelect:5; |
| 319 | u8 AckPolicy:2; |
| 320 | u8 NoACM:1; |
| 321 | u8 NonQos:1; |
| 322 | u8 KeyID:2; |
| 323 | u8 OUI:1; |
| 324 | u8 PktType:1; |
| 325 | u8 EnDescID:1; |
| 326 | u8 SecType:2; |
| 327 | u8 HTC:1; //padding0 |
| 328 | u8 WDS:1; //padding1 |
| 329 | u8 PktOffset:5; //padding_len (hw) |
| 330 | u8 HWPC:1; |
| 331 | |
| 332 | // DWORD 2 |
| 333 | u32 DataRetryLmt:6; |
| 334 | u32 RetryLmtEn:1; |
| 335 | u32 TSFL:5; |
| 336 | u32 RTSRC:6; // Reserved for HW RTS Retry Count. |
| 337 | u32 DATARC:6; // Reserved for HW DATA Retry Count. |
| 338 | u32 Rsvd1:5; |
| 339 | u32 AllowAggregation:1; |
| 340 | u32 BK:1; //Aggregation break. |
| 341 | u32 OwnMAC:1; |
| 342 | |
| 343 | // DWORD 3 |
| 344 | u8 NextHeadPage;//:8; |
| 345 | u8 TailPage;//:8; |
| 346 | u16 Seq:12; |
| 347 | u16 Frag:4; |
| 348 | |
| 349 | // DWORD 4 |
| 350 | u32 RTSRate:6; |
| 351 | u32 DisRTSFB:1; |
| 352 | u32 RTSRateFBLmt:4; |
| 353 | u32 CTS2Self:1; |
| 354 | u32 RTSEn:1; |
| 355 | u32 RaBRSRID:3; //Rate adaptive BRSR ID. |
| 356 | u32 TxHT:1; |
| 357 | u32 TxShort:1;//for data |
| 358 | u32 TxBandwidth:1; |
| 359 | u32 TxSubCarrier:2; |
| 360 | u32 STBC:2; |
| 361 | u32 RD:1; |
| 362 | u32 RTSHT:1; |
| 363 | u32 RTSShort:1; |
| 364 | u32 RTSBW:1; |
| 365 | u32 RTSSubcarrier:2; |
| 366 | u32 RTSSTBC:2; |
| 367 | u32 USERATE:1; |
| 368 | // DWORD 5 |
| 369 | u32 PktID:9; |
| 370 | u32 TxRate:6; |
| 371 | u32 DISFB:1; |
| 372 | u32 DataRateFBLmt:5; |
| 373 | u32 TxAGC:11; |
| 374 | |
| 375 | // DWORD 6 |
| 376 | u16 IPChkSum;//:16; |
| 377 | u16 TCPChkSum;//:16; |
| 378 | |
| 379 | // DWORD 7 |
| 380 | //u16 TxBuffSize;//:16;//pcie |
| 381 | u16 TxBufferSize; |
| 382 | u16 IPHdrOffset:8; |
| 383 | u16 Rsvd2:7; |
| 384 | u16 TCPEn:1; |
| 385 | }tx_desc_819x_usb, *ptx_desc_819x_usb; |
| 386 | typedef struct _tx_status_desc_8192s_usb{ |
| 387 | |
| 388 | //DWORD 0 |
| 389 | u8 TxRate:6; |
| 390 | u8 Rsvd1:1; |
| 391 | u8 BandWidth:1; |
| 392 | u8 RTSRate:6; |
| 393 | u8 AGGLS:1; |
| 394 | u8 AGG:1; |
| 395 | u8 RTSRC:6; |
| 396 | u8 DataRC:6; |
| 397 | u8 FailCause:2; |
| 398 | u8 TxOK:1; |
| 399 | u8 Own:1; |
| 400 | |
| 401 | //DWORD 1 |
| 402 | u16 Seq:12; |
| 403 | u8 QueueSel:5; |
| 404 | u8 MACID:5; |
| 405 | u8 PwrMgt:1; |
| 406 | u8 MoreData:1; |
| 407 | u8 Rsvd2; |
| 408 | |
| 409 | //DWORD 2 |
| 410 | u8 RxAGC1; |
| 411 | u8 RxAGC2; |
| 412 | u8 RxAGC3; |
| 413 | u8 RxAGC4; |
| 414 | }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 415 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 416 | |
| 417 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 418 | // |
| 419 | //Tx Descriptor for RLT8192SU(Load FW mode) |
| 420 | // |
| 421 | typedef struct _tx_desc_cmd_819x_usb{ |
| 422 | // DWORD 0 |
| 423 | u16 PktSize; |
| 424 | u8 Offset; |
| 425 | u8 Rsvd0:4; |
| 426 | u8 LINIP:1; |
| 427 | u8 Rsvd1:2; |
| 428 | u8 OWN:1; |
| 429 | |
| 430 | // DWORD 1, 2, 3, 4, 5, 6 are all reserved. |
| 431 | u32 Rsvd2; |
| 432 | u32 Rsvd3; |
| 433 | u32 Rsvd4; |
| 434 | u32 Rsvd5; |
| 435 | u32 Rsvd6; |
| 436 | u32 Rsvd7; |
| 437 | |
| 438 | // DWORD 7 |
| 439 | u16 TxBuffSize;//pcie |
| 440 | u16 Rsvd8; |
| 441 | }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; |
| 442 | // |
| 443 | //H2C Command for RLT8192SU(Host TxCmd) |
| 444 | // |
| 445 | typedef struct _tx_h2c_desc_cmd_8192s_usb{ |
| 446 | // DWORD 0 |
| 447 | u32 PktSize:16; |
| 448 | u32 Offset:8; |
| 449 | u32 Rsvd0:7; |
| 450 | u32 OWN:1; |
| 451 | |
| 452 | // DWORD 1 |
| 453 | u32 Rsvd1:8; |
| 454 | u32 QSEL:5; |
| 455 | u32 Rsvd2:19; |
| 456 | |
| 457 | // DWORD 2 |
| 458 | u32 Rsvd3; |
| 459 | |
| 460 | // DWORD 3 |
| 461 | u32 NextHeadPage:8; |
| 462 | u32 TailPage:8; |
| 463 | u32 Rsvd4:16; |
| 464 | |
| 465 | // DWORD 4, 5, 6, 7 |
| 466 | u32 Rsvd5; |
| 467 | u32 Rsvd6; |
| 468 | u32 Rsvd7; |
| 469 | u32 Rsvd8; |
| 470 | }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb; |
| 471 | |
| 472 | |
| 473 | typedef struct _tx_h2c_cmd_hdr_8192s_usb{ |
| 474 | // DWORD 0 |
| 475 | u32 CmdLen:16; |
| 476 | u32 ElementID:8; |
| 477 | u32 CmdSeq:8; |
| 478 | |
| 479 | // DWORD 1 |
| 480 | u32 Rsvd0; |
| 481 | }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 482 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 483 | typedef struct _tx_fwinfo_819x_usb{ |
| 484 | //DWORD 0 |
| 485 | u8 TxRate:7; |
| 486 | u8 CtsEnable:1; |
| 487 | u8 RtsRate:7; |
| 488 | u8 RtsEnable:1; |
| 489 | u8 TxHT:1; |
| 490 | u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS |
| 491 | u8 TxBandwidth:1; // This is used for HT MCS rate only. |
| 492 | u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. |
| 493 | u8 STBC:2; |
| 494 | u8 AllowAggregation:1; |
| 495 | u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate |
| 496 | u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS |
| 497 | u8 RtsBandwidth:1; // This is used for HT MCS rate only. |
| 498 | u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. |
| 499 | u8 RtsSTBC:2; |
| 500 | u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration |
| 501 | |
| 502 | //DWORD 1 |
| 503 | u32 RxMF:2; |
| 504 | u32 RxAMD:3; |
| 505 | u32 Reserved1:3; |
| 506 | u32 TxAGCOffSet:4;//TxAGCOffset:4; |
| 507 | u32 TxAGCSign:1; |
| 508 | u32 Tx_INFO_RSVD:6; |
| 509 | u32 PacketID:13; |
| 510 | }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 511 | |
| 512 | typedef struct rtl8192_rx_info { |
| 513 | struct urb *urb; |
| 514 | struct net_device *dev; |
| 515 | u8 out_pipe; |
| 516 | }rtl8192_rx_info ; |
| 517 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 518 | typedef struct rx_desc_819x_usb{ |
| 519 | //DWORD 0 |
| 520 | u16 Length:14; |
| 521 | u16 CRC32:1; |
| 522 | u16 ICV:1; |
| 523 | u8 RxDrvInfoSize:4; |
| 524 | u8 Security:3; |
| 525 | u8 Qos:1; |
| 526 | u8 Shift:2; |
| 527 | u8 PHYStatus:1; |
| 528 | u8 SWDec:1; |
| 529 | u8 LastSeg:1; |
| 530 | u8 FirstSeg:1; |
| 531 | u8 EOR:1; |
| 532 | u8 Own:1; |
| 533 | |
| 534 | //DWORD 1 |
| 535 | u16 MACID:5; |
| 536 | u16 TID:4; |
| 537 | u16 HwRsvd:5; |
| 538 | u16 PAGGR:1; |
| 539 | u16 FAGGR:1; |
| 540 | u8 A1_FIT:4; |
| 541 | u8 A2_FIT:4; |
| 542 | u8 PAM:1; |
| 543 | u8 PWR:1; |
| 544 | u8 MoreData:1; |
| 545 | u8 MoreFrag:1; |
| 546 | u8 Type:2; |
| 547 | u8 MC:1; |
| 548 | u8 BC:1; |
| 549 | |
| 550 | //DWORD 2 |
| 551 | u16 Seq:12; |
| 552 | u16 Frag:4; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 553 | u8 NextPktLen;//:8; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 554 | u8 Rsvd0:6; |
| 555 | u8 NextIND:1; |
| 556 | u8 Rsvd1:1; |
| 557 | |
| 558 | //DWORD 3 |
| 559 | u8 RxMCS:6; |
| 560 | u8 RxHT:1; |
| 561 | u8 AMSDU:1; |
| 562 | u8 SPLCP:1; |
| 563 | u8 BW:1; |
| 564 | u8 HTC:1; |
| 565 | u8 TCPChkRpt:1; |
| 566 | u8 IPChkRpt:1; |
| 567 | u8 TCPChkValID:1; |
| 568 | u8 HwPCErr:1; |
| 569 | u8 HwPCInd:1; |
| 570 | u16 IV0;//:16; |
| 571 | |
| 572 | //DWORD 4 |
| 573 | u32 IV1; |
| 574 | |
| 575 | //DWORD 5 |
| 576 | u32 TSFL; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 577 | }rx_desc_819x_usb, *prx_desc_819x_usb; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 578 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 579 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 580 | // |
| 581 | // Driver info are written to the begining of the RxBuffer |
| 582 | // |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 583 | typedef struct rx_drvinfo_819x_usb{ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 584 | u8 gain_trsw[4]; |
| 585 | |
| 586 | //DWORD 1 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 587 | u8 pwdb_all; |
| 588 | u8 cfosho[4]; |
| 589 | |
| 590 | //DWORD 2 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 591 | u8 cfotail[4]; |
| 592 | |
| 593 | //DWORD 3 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 594 | char rxevm[2]; |
| 595 | char rxsnr[4]; |
| 596 | |
| 597 | //DWORD 4 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 598 | u8 pdsnr[2]; |
| 599 | |
| 600 | //DWORD 5 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 601 | u8 csi_current[2]; |
| 602 | u8 csi_target[2]; |
| 603 | |
| 604 | //DWORD 6 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 605 | u8 sigevm; |
| 606 | u8 max_ex_pwr; |
| 607 | u8 ex_intf_flag:1; |
| 608 | u8 sgi_en:1; |
| 609 | u8 rxsc:2; |
| 610 | u8 reserve:4; |
| 611 | |
| 612 | }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 613 | |
| 614 | #define HWSET_MAX_SIZE_92S 128 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 615 | #define MAX_802_11_HEADER_LENGTH 40 |
| 616 | #define MAX_PKT_AGG_NUM 256 |
| 617 | #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 618 | |
| 619 | #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */ |
| 620 | #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 621 | #define ENCRYPTION_MAX_OVERHEAD 128 |
| 622 | #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 623 | #define MAX_FRAGMENT_COUNT 8 |
| 624 | #ifdef RTL8192U |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 625 | #define MAX_TRANSMIT_BUFFER_SIZE 8000 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 626 | #else |
| 627 | #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) |
| 628 | #endif |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 629 | #define scrclng 4 // octets for crc32 (FCS, ICV) |
| 630 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 631 | #define HAL_DM_DIG_DISABLE BIT0 |
| 632 | #define HAL_DM_HIPWR_DISABLE BIT1 |
| 633 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 634 | typedef enum rf_optype |
| 635 | { |
| 636 | RF_OP_By_SW_3wire = 0, |
| 637 | RF_OP_By_FW, |
| 638 | RF_OP_MAX |
| 639 | }rf_op_type; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 640 | |
| 641 | /* for rtl819x */ |
| 642 | typedef enum _RT_STATUS{ |
| 643 | RT_STATUS_SUCCESS = 0, |
| 644 | RT_STATUS_FAILURE = 1, |
| 645 | RT_STATUS_PENDING = 2, |
| 646 | RT_STATUS_RESOURCE = 3 |
| 647 | }RT_STATUS,*PRT_STATUS; |
| 648 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 649 | typedef enum _RTL8192SUSB_LOOPBACK{ |
| 650 | RTL8192SU_NO_LOOPBACK = 0, |
| 651 | RTL8192SU_MAC_LOOPBACK = 1, |
| 652 | RTL8192SU_DMA_LOOPBACK = 2, |
| 653 | RTL8192SU_CCK_LOOPBACK = 3, |
| 654 | }RTL8192SUSB_LOOPBACK_E; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 655 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 656 | #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP |
| 657 | |
| 658 | |
| 659 | /* Firmware Queue Layout */ |
| 660 | #define NUM_OF_FIRMWARE_QUEUE 10 |
| 661 | #define NUM_OF_PAGES_IN_FW 0x100 |
| 662 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 663 | |
| 664 | #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020 |
| 665 | #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020 |
| 666 | #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040 |
| 667 | #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040 |
| 668 | #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 |
| 669 | #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4 |
| 670 | #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20 |
| 671 | #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 |
| 672 | #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 |
| 673 | #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18 |
| 674 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 675 | |
| 676 | #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 |
| 677 | #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 |
| 678 | #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 |
| 679 | #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 |
| 680 | #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 |
| 681 | #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 |
| 682 | #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 |
| 683 | #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 |
| 684 | #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 685 | |
| 686 | #define DEFAULT_FRAG_THRESHOLD 2342U |
| 687 | #define MIN_FRAG_THRESHOLD 256U |
| 688 | #define DEFAULT_BEACONINTERVAL 0x64U |
| 689 | #define DEFAULT_BEACON_ESSID "Rtl819xU" |
| 690 | |
| 691 | #define DEFAULT_SSID "" |
| 692 | #define DEFAULT_RETRY_RTS 7 |
| 693 | #define DEFAULT_RETRY_DATA 7 |
| 694 | #define PRISM_HDR_SIZE 64 |
| 695 | |
| 696 | #define PHY_RSSI_SLID_WIN_MAX 100 |
| 697 | |
| 698 | |
| 699 | typedef enum _WIRELESS_MODE { |
| 700 | WIRELESS_MODE_UNKNOWN = 0x00, |
| 701 | WIRELESS_MODE_A = 0x01, |
| 702 | WIRELESS_MODE_B = 0x02, |
| 703 | WIRELESS_MODE_G = 0x04, |
| 704 | WIRELESS_MODE_AUTO = 0x08, |
| 705 | WIRELESS_MODE_N_24G = 0x10, |
| 706 | WIRELESS_MODE_N_5G = 0x20 |
| 707 | } WIRELESS_MODE; |
| 708 | |
| 709 | |
| 710 | #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 |
| 711 | |
| 712 | typedef struct buffer |
| 713 | { |
| 714 | struct buffer *next; |
| 715 | u32 *buf; |
| 716 | |
| 717 | } buffer; |
| 718 | |
| 719 | typedef struct rtl_reg_debug{ |
| 720 | unsigned int cmd; |
| 721 | struct { |
| 722 | unsigned char type; |
| 723 | unsigned char addr; |
| 724 | unsigned char page; |
| 725 | unsigned char length; |
| 726 | } head; |
| 727 | unsigned char buf[0xff]; |
| 728 | }rtl_reg_debug; |
| 729 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 730 | typedef struct _rt_9x_tx_rate_history { |
| 731 | u32 cck[4]; |
| 732 | u32 ofdm[8]; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 733 | u32 ht_mcs[4][16]; |
| 734 | }rt_tx_rahis_t, *prt_tx_rahis_t; |
| 735 | typedef struct _RT_SMOOTH_DATA_4RF { |
| 736 | char elements[4][100];//array to store values |
| 737 | u32 index; //index to current array to store |
| 738 | u32 TotalNum; //num of valid elements |
| 739 | u32 TotalVal[4]; //sum of valid elements |
| 740 | }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; |
| 741 | |
| 742 | #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size |
| 743 | //stats seems messed up, clean it ASAP |
| 744 | typedef struct Stats |
| 745 | { |
| 746 | unsigned long txrdu; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 747 | unsigned long rxok; |
| 748 | unsigned long rxframgment; |
| 749 | unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query |
| 750 | unsigned long rxurberr; |
| 751 | unsigned long rxstaterr; |
| 752 | unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa |
| 753 | unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI |
| 754 | unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) |
| 755 | unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40) |
| 756 | unsigned long numpacket_matchbssid; // debug use only. |
| 757 | unsigned long numpacket_toself; // debug use only. |
| 758 | unsigned long num_process_phyinfo; // debug use only. |
| 759 | unsigned long numqry_phystatus; |
| 760 | unsigned long numqry_phystatusCCK; |
| 761 | unsigned long numqry_phystatusHT; |
| 762 | unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate |
| 763 | unsigned long txnperr; |
| 764 | unsigned long txnpdrop; |
| 765 | unsigned long txresumed; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 766 | unsigned long txnpokint; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 767 | unsigned long txoverflow; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 768 | unsigned long txlpokint; |
| 769 | unsigned long txlpdrop; |
| 770 | unsigned long txlperr; |
| 771 | unsigned long txbeokint; |
| 772 | unsigned long txbedrop; |
| 773 | unsigned long txbeerr; |
| 774 | unsigned long txbkokint; |
| 775 | unsigned long txbkdrop; |
| 776 | unsigned long txbkerr; |
| 777 | unsigned long txviokint; |
| 778 | unsigned long txvidrop; |
| 779 | unsigned long txvierr; |
| 780 | unsigned long txvookint; |
| 781 | unsigned long txvodrop; |
| 782 | unsigned long txvoerr; |
| 783 | unsigned long txbeaconokint; |
| 784 | unsigned long txbeacondrop; |
| 785 | unsigned long txbeaconerr; |
| 786 | unsigned long txmanageokint; |
| 787 | unsigned long txmanagedrop; |
| 788 | unsigned long txmanageerr; |
| 789 | unsigned long txdatapkt; |
| 790 | unsigned long txfeedback; |
| 791 | unsigned long txfeedbackok; |
| 792 | |
| 793 | unsigned long txoktotal; |
| 794 | unsigned long txokbytestotal; |
| 795 | unsigned long txokinperiod; |
| 796 | unsigned long txmulticast; |
| 797 | unsigned long txbytesmulticast; |
| 798 | unsigned long txbroadcast; |
| 799 | unsigned long txbytesbroadcast; |
| 800 | unsigned long txunicast; |
| 801 | unsigned long txbytesunicast; |
| 802 | |
| 803 | unsigned long rxoktotal; |
| 804 | unsigned long rxbytesunicast; |
| 805 | unsigned long txfeedbackfail; |
| 806 | unsigned long txerrtotal; |
| 807 | unsigned long txerrbytestotal; |
| 808 | unsigned long txerrmulticast; |
| 809 | unsigned long txerrbroadcast; |
| 810 | unsigned long txerrunicast; |
| 811 | unsigned long txretrycount; |
| 812 | unsigned long txfeedbackretry; |
| 813 | u8 last_packet_rate; |
| 814 | unsigned long slide_signal_strength[100]; |
| 815 | unsigned long slide_evm[100]; |
| 816 | unsigned long slide_rssi_total; // For recording sliding window's RSSI value |
| 817 | unsigned long slide_evm_total; // For recording sliding window's EVM value |
| 818 | long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct. |
| 819 | long signal_quality; |
| 820 | long last_signal_strength_inpercent; |
| 821 | long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now. |
| 822 | u8 rx_rssi_percentage[4]; |
| 823 | u8 rx_evm_percentage[2]; |
| 824 | long rxSNRdB[4]; |
| 825 | rt_tx_rahis_t txrate; |
| 826 | u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi |
| 827 | u32 Slide_Beacon_Total; //cosa add for beacon rssi |
| 828 | RT_SMOOTH_DATA_4RF cck_adc_pwdb; |
| 829 | |
| 830 | u32 CurrentShowTxate; |
| 831 | } Stats; |
| 832 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 833 | // Bandwidth Offset |
| 834 | #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 |
| 835 | #define HAL_PRIME_CHNL_OFFSET_LOWER 1 |
| 836 | #define HAL_PRIME_CHNL_OFFSET_UPPER 2 |
| 837 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 838 | typedef struct ChnlAccessSetting { |
| 839 | u16 SIFS_Timer; |
| 840 | u16 DIFS_Timer; |
| 841 | u16 SlotTimeTimer; |
| 842 | u16 EIFS_Timer; |
| 843 | u16 CWminIndex; |
| 844 | u16 CWmaxIndex; |
| 845 | }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; |
| 846 | |
| 847 | typedef struct _BB_REGISTER_DEFINITION{ |
| 848 | u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] |
| 849 | u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] |
| 850 | u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] |
| 851 | u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] |
| 852 | u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] |
| 853 | u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] |
| 854 | u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] |
| 855 | u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] |
| 856 | u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] |
| 857 | u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] |
| 858 | u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] |
| 859 | u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] |
| 860 | u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] |
| 861 | u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] |
| 862 | u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] |
| 863 | u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] |
| 864 | u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] |
| 865 | u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B |
| 866 | }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; |
| 867 | |
| 868 | typedef enum _RT_RF_TYPE_819xU{ |
| 869 | RF_TYPE_MIN = 0, |
| 870 | RF_8225, |
| 871 | RF_8256, |
| 872 | RF_8258, |
| 873 | RF_6052=4, // 4 11b/g/n RF |
| 874 | RF_PSEUDO_11N = 5, |
| 875 | }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; |
| 876 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 877 | typedef enum _RF_POWER_STATE{ |
| 878 | RF_ON, |
| 879 | RF_SLEEP, |
| 880 | RF_OFF, |
| 881 | RF_SHUT_DOWN, |
| 882 | }RF_POWER_STATE, *PRF_POWER_STATE; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 883 | |
| 884 | typedef struct _rate_adaptive |
| 885 | { |
| 886 | u8 rate_adaptive_disabled; |
| 887 | u8 ratr_state; |
| 888 | u16 reserve; |
| 889 | |
| 890 | u32 high_rssi_thresh_for_ra; |
| 891 | u32 high2low_rssi_thresh_for_ra; |
| 892 | u8 low2high_rssi_thresh_for_ra40M; |
| 893 | u32 low_rssi_thresh_for_ra40M; |
| 894 | u8 low2high_rssi_thresh_for_ra20M; |
| 895 | u32 low_rssi_thresh_for_ra20M; |
| 896 | u32 upper_rssi_threshold_ratr; |
| 897 | u32 middle_rssi_threshold_ratr; |
| 898 | u32 low_rssi_threshold_ratr; |
| 899 | u32 low_rssi_threshold_ratr_40M; |
| 900 | u32 low_rssi_threshold_ratr_20M; |
| 901 | u8 ping_rssi_enable; //cosa add for test |
| 902 | u32 ping_rssi_ratr; //cosa add for test |
| 903 | u32 ping_rssi_thresh_for_ra;//cosa add for test |
| 904 | u32 last_ratr; |
| 905 | |
| 906 | } rate_adaptive, *prate_adaptive; |
| 907 | |
| 908 | #define TxBBGainTableLength 37 |
| 909 | #define CCKTxBBGainTableLength 23 |
| 910 | |
| 911 | typedef struct _txbbgain_struct |
| 912 | { |
| 913 | long txbb_iq_amplifygain; |
| 914 | u32 txbbgain_value; |
| 915 | } txbbgain_struct, *ptxbbgain_struct; |
| 916 | |
| 917 | typedef struct _ccktxbbgain_struct |
| 918 | { |
| 919 | //The Value is from a22 to a29 one Byte one time is much Safer |
| 920 | u8 ccktxbb_valuearray[8]; |
| 921 | } ccktxbbgain_struct,*pccktxbbgain_struct; |
| 922 | |
| 923 | |
| 924 | typedef struct _init_gain |
| 925 | { |
| 926 | u8 xaagccore1; |
| 927 | u8 xbagccore1; |
| 928 | u8 xcagccore1; |
| 929 | u8 xdagccore1; |
| 930 | u8 cca; |
| 931 | |
| 932 | } init_gain, *pinit_gain; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 933 | |
| 934 | typedef struct _phy_ofdm_rx_status_report_819xusb |
| 935 | { |
| 936 | u8 trsw_gain_X[4]; |
| 937 | u8 pwdb_all; |
| 938 | u8 cfosho_X[4]; |
| 939 | u8 cfotail_X[4]; |
| 940 | u8 rxevm_X[2]; |
| 941 | u8 rxsnr_X[4]; |
| 942 | u8 pdsnr_X[2]; |
| 943 | u8 csi_current_X[2]; |
| 944 | u8 csi_target_X[2]; |
| 945 | u8 sigevm; |
| 946 | u8 max_ex_pwr; |
| 947 | u8 sgi_en; |
| 948 | u8 rxsc_sgien_exflg; |
| 949 | }phy_sts_ofdm_819xusb_t; |
| 950 | |
| 951 | typedef struct _phy_cck_rx_status_report_819xusb |
| 952 | { |
| 953 | /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend |
| 954 | 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ |
| 955 | u8 adc_pwdb_X[4]; |
| 956 | u8 sq_rpt; |
| 957 | u8 cck_agc_rpt; |
| 958 | }phy_sts_cck_819xusb_t; |
| 959 | |
| 960 | |
| 961 | typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{ |
| 962 | u8 reserved:4; |
| 963 | u8 rxsc:2; |
| 964 | u8 sgi_en:1; |
| 965 | u8 ex_intf_flag:1; |
| 966 | }phy_ofdm_rx_status_rxsc_sgien_exintfflag; |
| 967 | |
| 968 | typedef enum _RT_CUSTOMER_ID |
| 969 | { |
| 970 | RT_CID_DEFAULT = 0, |
| 971 | RT_CID_8187_ALPHA0 = 1, |
| 972 | RT_CID_8187_SERCOMM_PS = 2, |
| 973 | RT_CID_8187_HW_LED = 3, |
| 974 | RT_CID_8187_NETGEAR = 4, |
| 975 | RT_CID_WHQL = 5, |
| 976 | RT_CID_819x_CAMEO = 6, |
| 977 | RT_CID_819x_RUNTOP = 7, |
| 978 | RT_CID_819x_Senao = 8, |
| 979 | RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. |
| 980 | RT_CID_819x_Netcore = 10, |
| 981 | RT_CID_Nettronix = 11, |
| 982 | RT_CID_DLINK = 12, |
| 983 | RT_CID_PRONET = 13, |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 984 | RT_CID_COREGA = 14, |
| 985 | RT_CID_819x_ALPHA = 15, |
| 986 | RT_CID_819x_Sitecom = 16, |
| 987 | RT_CID_CCX = 17, |
| 988 | RT_CID_819x_Lenovo = 18, |
| 989 | RT_CID_819x_QMI = 19, |
| 990 | RT_CID_819x_Edimax_Belkin = 20, |
| 991 | RT_CID_819x_Sercomm_Belkin = 21, |
| 992 | RT_CID_819x_CAMEO1 = 22, |
| 993 | RT_CID_819x_MSI = 23, |
| 994 | RT_CID_819x_Acer = 24, |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 995 | }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; |
| 996 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 997 | typedef enum _RT_OP_MODE{ |
| 998 | RT_OP_MODE_AP, |
| 999 | RT_OP_MODE_INFRASTRUCTURE, |
| 1000 | RT_OP_MODE_IBSS, |
| 1001 | RT_OP_MODE_NO_LINK, |
| 1002 | }RT_OP_MODE, *PRT_OP_MODE; |
| 1003 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1004 | typedef enum _RESET_TYPE { |
| 1005 | RESET_TYPE_NORESET = 0x00, |
| 1006 | RESET_TYPE_NORMAL = 0x01, |
| 1007 | RESET_TYPE_SILENT = 0x02 |
| 1008 | } RESET_TYPE; |
| 1009 | |
| 1010 | /* The simple tx command OP code. */ |
| 1011 | typedef enum _tag_TxCmd_Config_Index{ |
| 1012 | TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, |
| 1013 | TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, |
| 1014 | TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, |
| 1015 | TXCMD_SET_TX_DURATION = 0xFF900003, |
| 1016 | TXCMD_SET_RX_RSSI = 0xFF900004, |
| 1017 | TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, |
| 1018 | TXCMD_XXXX_CTRL, |
| 1019 | }DCMD_TXCMD_OP; |
| 1020 | |
| 1021 | typedef enum{ |
| 1022 | NIC_8192U = 1, |
| 1023 | NIC_8190P = 2, |
| 1024 | NIC_8192E = 3, |
| 1025 | NIC_8192SE = 4, |
| 1026 | NIC_8192SU = 5, |
| 1027 | } nic_t; |
| 1028 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1029 | struct rtl819x_ops{ |
| 1030 | nic_t nic_type; |
| 1031 | void (* rtl819x_read_eeprom_info)(struct net_device *dev); |
| 1032 | short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb); |
| 1033 | short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb); |
| 1034 | void (* rtl819x_rx_nomal)(struct sk_buff* skb); |
| 1035 | void (* rtl819x_rx_cmd)(struct sk_buff *skb); |
| 1036 | bool (* rtl819x_adapter_start)(struct net_device *dev); |
| 1037 | void (* rtl819x_link_change)(struct net_device *dev); |
| 1038 | void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation); |
| 1039 | void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe); |
| 1040 | }; |
| 1041 | |
| 1042 | typedef struct r8192_priv |
| 1043 | { |
| 1044 | struct rtl819x_ops* ops; |
| 1045 | struct usb_device *udev; |
Florian Schilhabel | 495c57f | 2010-05-04 14:24:35 +0200 | [diff] [blame] | 1046 | /* added for maintain info from eeprom */ |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1047 | short epromtype; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1048 | u16 eeprom_vid; |
| 1049 | u16 eeprom_pid; |
| 1050 | u8 eeprom_CustomerID; |
| 1051 | u8 eeprom_SubCustomerID; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1052 | u16 eeprom_ChannelPlan; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1053 | RT_CUSTOMER_ID CustomerID; |
Florian Schilhabel | 5c2af91 | 2010-05-13 13:55:25 +0200 | [diff] [blame] | 1054 | LED_STRATEGY_819xUsb LedStrategy; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1055 | u8 txqueue_to_outpipemap[9]; |
| 1056 | u8 RtOutPipes[16]; |
| 1057 | u8 RtInPipes[16]; |
| 1058 | u8 ep_in_num; |
| 1059 | u8 ep_out_num; |
| 1060 | u8 ep_num; |
| 1061 | int irq; |
| 1062 | struct ieee80211_device *ieee80211; |
| 1063 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1064 | u8 RATRTableBitmap; |
| 1065 | |
| 1066 | u32 IC_Cut; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1067 | short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1068 | u32 card_8192_version; /* if TCR reports card V B/C this discriminates */ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1069 | short enable_gpio0; |
| 1070 | enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type; |
| 1071 | short hw_plcp_len; |
| 1072 | short plcp_preamble_mode; |
| 1073 | |
| 1074 | spinlock_t irq_lock; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1075 | spinlock_t tx_lock; |
| 1076 | spinlock_t ps_lock; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1077 | struct mutex mutex; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1078 | bool ps_force; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1079 | spinlock_t rf_lock; //used to lock rf write operation added by wb |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1080 | spinlock_t rf_ps_lock; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1081 | |
| 1082 | u16 irq_mask; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1083 | short chan; |
| 1084 | short sens; |
| 1085 | short max_sens; |
| 1086 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1087 | short up; |
| 1088 | short crcmon; //if 1 allow bad crc frame reception in monitor mode |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1089 | bool bSurpriseRemoved; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1090 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1091 | struct semaphore wx_sem; |
| 1092 | struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1093 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1094 | u8 rf_type; //0 means 1T2R, 1 means 2T4R |
| 1095 | RT_RF_TYPE_819xU rf_chip; |
| 1096 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1097 | short (*rf_set_sens)(struct net_device *dev,short sens); |
| 1098 | u8 (*rf_set_chan)(struct net_device *dev,u8 ch); |
| 1099 | void (*rf_close)(struct net_device *dev); |
| 1100 | void (*rf_init)(struct net_device *dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1101 | short promisc; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1102 | u32 mc_filter[2]; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1103 | /*stats*/ |
| 1104 | struct Stats stats; |
| 1105 | struct iw_statistics wstats; |
| 1106 | struct proc_dir_entry *dir_dev; |
| 1107 | |
| 1108 | /*RX stuff*/ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1109 | struct urb **rx_urb; |
| 1110 | struct urb **rx_cmd_urb; |
| 1111 | |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1112 | /* for Rx process */ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1113 | struct sk_buff_head rx_queue; |
| 1114 | struct sk_buff_head skb_queue; |
Bartlomiej Zolnierkiewicz | 1ec9e48 | 2009-06-13 18:35:04 +0200 | [diff] [blame] | 1115 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1116 | struct work_struct qos_activate; |
Bartlomiej Zolnierkiewicz | 1ec9e48 | 2009-06-13 18:35:04 +0200 | [diff] [blame] | 1117 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1118 | short tx_urb_index; |
| 1119 | atomic_t tx_pending[0x10];//UART_PRIORITY+1 |
| 1120 | |
| 1121 | |
| 1122 | struct tasklet_struct irq_rx_tasklet; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1123 | struct tasklet_struct irq_tx_tasklet; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1124 | struct urb *rxurb_task; |
| 1125 | |
| 1126 | //2 Tx Related variables |
| 1127 | u16 ShortRetryLimit; |
| 1128 | u16 LongRetryLimit; |
| 1129 | u32 TransmitConfig; |
| 1130 | u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27. |
| 1131 | |
| 1132 | u32 LastRxDescTSFHigh; |
| 1133 | u32 LastRxDescTSFLow; |
| 1134 | |
| 1135 | |
| 1136 | //2 Rx Related variables |
| 1137 | u16 EarlyRxThreshold; |
| 1138 | u32 ReceiveConfig; |
| 1139 | u8 AcmControl; |
| 1140 | |
| 1141 | u8 RFProgType; |
| 1142 | |
| 1143 | u8 retry_data; |
| 1144 | u8 retry_rts; |
| 1145 | u16 rts; |
| 1146 | |
| 1147 | struct ChnlAccessSetting ChannelAccessSetting; |
Bartlomiej Zolnierkiewicz | 1ec9e48 | 2009-06-13 18:35:04 +0200 | [diff] [blame] | 1148 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1149 | struct work_struct reset_wq; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1150 | struct work_struct mcast_wq; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1151 | |
| 1152 | /**********************************************************/ |
| 1153 | //for rtl819xUsb |
| 1154 | u16 basic_rate; |
| 1155 | u8 short_preamble; |
| 1156 | u8 slot_time; |
| 1157 | bool bDcut; |
| 1158 | bool bCurrentRxAggrEnable; |
| 1159 | u8 Rf_Mode; //add for Firmware RF -R/W switch |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1160 | u8 FwRsvdTxPageCfg; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1161 | prt_firmware pFirmware; |
Florian Schilhabel | 638b5ac | 2010-07-14 14:42:25 +0200 | [diff] [blame] | 1162 | RTL8192SUSB_LOOPBACK_E LoopbackMode; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1163 | bool usb_error; |
| 1164 | |
| 1165 | u16 EEPROMTxPowerDiff; |
| 1166 | u8 EEPROMThermalMeter; |
| 1167 | u8 EEPROMPwDiff; |
| 1168 | u8 EEPROMCrystalCap; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1169 | u8 EEPROMBluetoothCoexist; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1170 | u8 EEPROM_Def_Ver; |
| 1171 | u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14 |
| 1172 | u8 EEPROMTxPowerLevelCCK_V1[3]; |
| 1173 | u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14 |
| 1174 | u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G |
| 1175 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1176 | u8 EEPROMOptional; |
| 1177 | u8 ShowRateMode; |
| 1178 | bool bForcedShowRxRate; |
| 1179 | |
| 1180 | u32 RfRegChnlVal[2]; |
| 1181 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1182 | bool bDmDisableProtect; |
| 1183 | bool bIgnoreDiffRateTxPowerOffset; |
| 1184 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1185 | // For EEPROM TX Power Index like 8190 series |
| 1186 | u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7 |
| 1187 | u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 |
| 1188 | u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7 |
| 1189 | u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 |
| 1190 | |
| 1191 | // F92S new definition |
| 1192 | //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14] |
| 1193 | u8 RfCckChnlAreaTxPwr[2][3]; |
| 1194 | u8 RfOfdmChnlAreaTxPwr1T[2][3]; |
| 1195 | u8 RfOfdmChnlAreaTxPwr2T[2][3]; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1196 | |
| 1197 | // Add For EEPROM Efuse switch and Efuse Shadow map Setting |
| 1198 | bool EepromOrEfuse; |
| 1199 | bool bBootFromEfuse; // system boot form EFUSE |
| 1200 | u8 EfuseMap[2][HWSET_MAX_SIZE_92S]; |
Florian Schilhabel | a6f81aa | 2010-07-14 14:43:26 +0200 | [diff] [blame] | 1201 | u16 EfuseUsedBytes; |
| 1202 | u8 EfuseUsedPercentage; |
| 1203 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1204 | |
| 1205 | u8 EEPROMUsbOption; |
| 1206 | u8 EEPROMUsbPhyParam[5]; |
| 1207 | u8 EEPROMTxPwrBase; |
| 1208 | u8 EEPROMBoardType; |
| 1209 | bool bBootFromEEPROM; // system boot from EEPROM |
| 1210 | u8 EEPROMTSSI_A; |
| 1211 | u8 EEPROMTSSI_B; |
| 1212 | u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B. |
| 1213 | u8 EEPROMTxPwrTkMode; |
| 1214 | |
| 1215 | u8 bTXPowerDataReadFromEEPORM; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1216 | u8 EEPROMRegulatory; |
| 1217 | u8 EEPROMPwrGroup[2][3]; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1218 | |
| 1219 | u8 EEPROMVersion; |
| 1220 | u8 EEPROMUsbEndPointNumber; |
| 1221 | |
| 1222 | bool AutoloadFailFlag; |
| 1223 | u8 RfTxPwrLevelCck[2][14]; |
| 1224 | u8 RfTxPwrLevelOfdm1T[2][14]; |
| 1225 | u8 RfTxPwrLevelOfdm2T[2][14]; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1226 | // new EEPROM format. |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1227 | u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff |
| 1228 | u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff |
| 1229 | u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel |
| 1230 | u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel |
| 1231 | u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel |
| 1232 | u8 TxPwrbandEdgeFlag; // Band edge enable flag |
| 1233 | |
| 1234 | // L1 and L2 high power threshold. |
| 1235 | u8 MidHighPwrTHR_L1; |
| 1236 | u8 MidHighPwrTHR_L2; |
| 1237 | u8 TxPwrSafetyFlag; // for Tx power safety spec |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1238 | |
| 1239 | /*PHY related*/ |
| 1240 | BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D |
| 1241 | // Read/write are allow for following hardware information variables |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1242 | u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1243 | u32 CCKTxPowerLevelOriginalOffset; |
| 1244 | u8 TxPowerLevelCCK[14]; // CCK channel 1~14 |
| 1245 | u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 |
| 1246 | u8 TxPowerLevelOFDM5G[14]; // OFDM 5G |
| 1247 | u32 Pwr_Track; |
| 1248 | u8 TxPowerDiff; |
| 1249 | u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1250 | u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 |
| 1251 | u8 ThermalValue; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1252 | u8 CrystalCap; // CrystalCap. |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1253 | u8 BluetoothCoexist; |
| 1254 | u8 ExternalPA; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1255 | |
| 1256 | u8 CckPwEnl; |
| 1257 | // Use to calculate PWBD. |
| 1258 | u8 bCckHighPower; |
| 1259 | long undecorated_smoothed_pwdb; |
| 1260 | |
| 1261 | //for set channel |
| 1262 | u8 SwChnlInProgress; |
| 1263 | u8 SwChnlStage; |
| 1264 | u8 SwChnlStep; |
| 1265 | u8 SetBWModeInProgress; |
| 1266 | HT_CHANNEL_WIDTH CurrentChannelBW; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1267 | bool bChnlPlanFromHW; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1268 | u8 ChannelPlan; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1269 | u16 RegChannelPlan; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1270 | u8 pwrGroupCnt; |
| 1271 | // 8190 40MHz mode |
| 1272 | // |
| 1273 | u8 nCur40MhzPrimeSC; // Control channel sub-carrier |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1274 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1275 | u32 RfReg0Value[4]; |
| 1276 | u8 NumTotalRFPath; |
| 1277 | bool brfpath_rxenable[4]; |
| 1278 | //RF set related |
| 1279 | bool SetRFPowerStateInProgress; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1280 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1281 | struct timer_list watch_dog_timer; |
| 1282 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1283 | bool bdynamic_txpower; //bDynamicTxPower |
| 1284 | bool bDynamicTxHighPower; // Tx high power state |
| 1285 | bool bDynamicTxLowPower; // Tx low power state |
| 1286 | bool bLastDTPFlag_High; |
| 1287 | bool bLastDTPFlag_Low; |
| 1288 | |
| 1289 | bool bstore_last_dtpflag; |
| 1290 | bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1291 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1292 | rate_adaptive rate_adaptive; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1293 | // TX power tracking |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1294 | txbbgain_struct txbbgain_table[TxBBGainTableLength]; |
| 1295 | u8 EEPROMTxPowerTrackEnable; |
| 1296 | u8 txpower_count;//For 6 sec do tracking again |
| 1297 | bool btxpower_trackingInit; |
| 1298 | u8 OFDM_index; |
| 1299 | u8 CCK_index; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1300 | u8 Record_CCK_20Mindex; |
| 1301 | u8 Record_CCK_40Mindex; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1302 | // CCK TX Power Tracking |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1303 | ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; |
| 1304 | ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; |
| 1305 | u8 rfa_txpowertrackingindex; |
| 1306 | u8 rfa_txpowertrackingindex_real; |
| 1307 | u8 rfa_txpowertracking_default; |
| 1308 | u8 rfc_txpowertrackingindex; |
| 1309 | u8 rfc_txpowertrackingindex_real; |
| 1310 | |
| 1311 | s8 cck_present_attentuation; |
| 1312 | u8 cck_present_attentuation_20Mdefault; |
| 1313 | u8 cck_present_attentuation_40Mdefault; |
| 1314 | char cck_present_attentuation_difference; |
| 1315 | bool btxpower_tracking; |
| 1316 | bool bcck_in_ch14; |
| 1317 | bool btxpowerdata_readfromEEPORM; |
| 1318 | u16 TSSI_13dBm; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1319 | u8 CCKPresentAttentuation_20Mdefault; |
| 1320 | u8 CCKPresentAttentuation_40Mdefault; |
| 1321 | char CCKPresentAttentuation_difference; |
| 1322 | char CCKPresentAttentuation; |
| 1323 | bool bDMInitialGainEnable; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1324 | //For Backup Initial Gain |
| 1325 | init_gain initgain_backup; |
| 1326 | u8 DefaultInitialGain[4]; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1327 | // For EDCA Turbo mode |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1328 | bool bis_any_nonbepkts; |
| 1329 | bool bcurrent_turbo_EDCA; |
| 1330 | bool bis_cur_rdlstate; |
| 1331 | struct timer_list fsync_timer; |
| 1332 | bool bfsync_processing; // 500ms Fsync timer is active or not |
| 1333 | u32 rate_record; |
| 1334 | u32 rateCountDiffRecord; |
| 1335 | u32 ContiuneDiffCount; |
| 1336 | bool bswitch_fsync; |
| 1337 | |
| 1338 | u8 framesync; |
| 1339 | u32 framesyncC34; |
| 1340 | u8 framesyncMonitor; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1341 | // RX related |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1342 | u16 nrxAMPDU_size; |
| 1343 | u8 nrxAMPDU_aggr_num; |
| 1344 | |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1345 | // gpio |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1346 | bool bHwRadioOff; |
| 1347 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1348 | bool isRFOff; |
| 1349 | bool bInPowerSaveMode; |
| 1350 | |
| 1351 | bool RFChangeInProgress; |
| 1352 | bool RegRfOff; |
| 1353 | u8 bHwRfOffAction; |
| 1354 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1355 | u32 reset_count; |
| 1356 | bool bpbc_pressed; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1357 | // debug |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1358 | u32 txpower_checkcnt; |
| 1359 | u32 txpower_tracking_callback_cnt; |
| 1360 | u8 thermal_read_val[40]; |
| 1361 | u8 thermal_readback_index; |
| 1362 | u32 ccktxpower_adjustcnt_not_ch14; |
| 1363 | u32 ccktxpower_adjustcnt_ch14; |
| 1364 | u8 tx_fwinfo_force_subcarriermode; |
| 1365 | u8 tx_fwinfo_force_subcarrierval; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1366 | // silent reset |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1367 | RESET_TYPE ResetProgress; |
| 1368 | bool bForcedSilentReset; |
| 1369 | bool bDisableNormalResetCheck; |
| 1370 | u16 TxCounter; |
| 1371 | u16 RxCounter; |
| 1372 | int IrpPendingCount; |
| 1373 | bool bResetInProgress; |
| 1374 | bool force_reset; |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1375 | bool force_lps; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1376 | u8 InitialGainOperateType; |
| 1377 | |
| 1378 | u16 SifsTime; |
| 1379 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1380 | struct delayed_work update_beacon_wq; |
| 1381 | struct delayed_work watch_dog_wq; |
| 1382 | struct delayed_work txpower_tracking_wq; |
| 1383 | struct delayed_work rfpath_check_wq; |
| 1384 | struct delayed_work gpio_change_rf_wq; |
| 1385 | struct delayed_work initialgain_operate_wq; |
Bartlomiej Zolnierkiewicz | 1ec9e48 | 2009-06-13 18:35:04 +0200 | [diff] [blame] | 1386 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1387 | struct workqueue_struct *priv_wq; |
Florian Schilhabel | 03dff62 | 2010-07-14 14:44:34 +0200 | [diff] [blame] | 1388 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1389 | u32 IntrMask; |
| 1390 | // RF and BB access related synchronization flags. |
| 1391 | bool bChangeBBInProgress; // BaseBand RW is still in progress. |
| 1392 | bool bChangeRFInProgress; // RF RW is still in progress. |
| 1393 | |
| 1394 | u32 CCKTxPowerAdjustCntCh14; //debug only |
| 1395 | u32 CCKTxPowerAdjustCntNotCh14; //debug only |
| 1396 | u32 TXPowerTrackingCallbackCnt; //debug only |
| 1397 | u32 TxPowerCheckCnt; //debug only |
| 1398 | u32 RFWritePageCnt[3]; //debug only |
| 1399 | u32 RFReadPageCnt[3]; //debug only |
| 1400 | u8 ThermalReadBackIndex; //debug only |
| 1401 | u8 ThermalReadVal[40]; //debug only |
| 1402 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1403 | // not realize true, just define it, set it 0 default, because some func use it |
| 1404 | bool bInHctTest; |
| 1405 | |
| 1406 | // The current Tx Power Level |
| 1407 | u8 CurrentCckTxPwrIdx; |
| 1408 | u8 CurrentOfdm24GTxPwrIdx; |
| 1409 | |
| 1410 | // For pass 92S common phycfg.c compiler |
| 1411 | u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14 |
| 1412 | u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14 |
| 1413 | u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14 |
| 1414 | u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14 |
| 1415 | u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff |
| 1416 | char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a |
| 1417 | |
| 1418 | bool bRFSiOrPi;//0=si, 1=pi. |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1419 | |
| 1420 | bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only |
| 1421 | u8 CurrentFwCmdIO; |
| 1422 | |
| 1423 | u8 MinSpaceCfg; |
| 1424 | |
| 1425 | u16 rf_pathmap; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1426 | |
Florian Schilhabel | 5c2af91 | 2010-05-13 13:55:25 +0200 | [diff] [blame] | 1427 | /* added for led control */ |
| 1428 | PLED_819xUsb pLed; |
| 1429 | LED_819xUsb SwLed0; |
| 1430 | LED_819xUsb SwLed1; |
| 1431 | u8 bRegUseLed; |
Florian Schilhabel | 638b5ac | 2010-07-14 14:42:25 +0200 | [diff] [blame] | 1432 | struct work_struct BlinkWorkItem; |
Florian Schilhabel | 5c2af91 | 2010-05-13 13:55:25 +0200 | [diff] [blame] | 1433 | /* added for led control */ |
| 1434 | u16 FwCmdIOMap; |
| 1435 | u32 FwCmdIOParam; |
Florian Schilhabel | 638b5ac | 2010-07-14 14:42:25 +0200 | [diff] [blame] | 1436 | u8 DMFlag; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1437 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1438 | |
| 1439 | |
| 1440 | |
| 1441 | }r8192_priv; |
| 1442 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1443 | //for rtl8187B |
| 1444 | typedef enum{ |
| 1445 | BULK_PRIORITY = 0x01, |
| 1446 | //RSVD0, |
| 1447 | //RSVD1, |
| 1448 | LOW_PRIORITY, |
| 1449 | NORM_PRIORITY, |
| 1450 | VO_PRIORITY, |
| 1451 | VI_PRIORITY, //0x05 |
| 1452 | BE_PRIORITY, |
| 1453 | BK_PRIORITY, |
| 1454 | RSVD2, |
| 1455 | RSVD3, |
| 1456 | BEACON_PRIORITY, //0x0A |
| 1457 | HIGH_PRIORITY, |
| 1458 | MANAGE_PRIORITY, |
| 1459 | RSVD4, |
| 1460 | RSVD5, |
| 1461 | UART_PRIORITY //0x0F |
| 1462 | } priority_t; |
| 1463 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1464 | #ifdef JOHN_HWSEC |
| 1465 | struct ssid_thread { |
| 1466 | struct net_device *dev; |
| 1467 | u8 name[IW_ESSID_MAX_SIZE + 1]; |
| 1468 | }; |
| 1469 | #endif |
| 1470 | |
Florian Schilhabel | d9c5cc9 | 2010-07-14 14:45:17 +0200 | [diff] [blame] | 1471 | void LedControl8192SUsb(struct net_device *dev, LED_CTL_MODE LedAction); |
| 1472 | void InitSwLeds(struct net_device *dev); |
| 1473 | void DeInitSwLeds(struct net_device *dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1474 | short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb); |
| 1475 | short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb); |
| 1476 | bool FirmwareDownload92S(struct net_device *dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1477 | |
| 1478 | short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); |
| 1479 | short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); |
| 1480 | |
| 1481 | u32 read_cam(struct net_device *dev, u8 addr); |
| 1482 | void write_cam(struct net_device *dev, u8 addr, u32 data); |
| 1483 | |
| 1484 | u8 read_nic_byte(struct net_device *dev, int x); |
| 1485 | u8 read_nic_byte_E(struct net_device *dev, int x); |
| 1486 | u32 read_nic_dword(struct net_device *dev, int x); |
| 1487 | u16 read_nic_word(struct net_device *dev, int x) ; |
| 1488 | void write_nic_byte(struct net_device *dev, int x,u8 y); |
| 1489 | void write_nic_byte_E(struct net_device *dev, int x,u8 y); |
| 1490 | void write_nic_word(struct net_device *dev, int x,u16 y); |
| 1491 | void write_nic_dword(struct net_device *dev, int x,u32 y); |
| 1492 | void force_pci_posting(struct net_device *dev); |
| 1493 | |
| 1494 | void rtl8192_rtx_disable(struct net_device *); |
| 1495 | void rtl8192_rx_enable(struct net_device *); |
| 1496 | void rtl8192_tx_enable(struct net_device *); |
| 1497 | |
| 1498 | void rtl8192_disassociate(struct net_device *dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1499 | void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a); |
| 1500 | |
| 1501 | void rtl8192_set_anaparam(struct net_device *dev,u32 a); |
| 1502 | void rtl8185_set_anaparam2(struct net_device *dev,u32 a); |
| 1503 | void rtl8192_update_msr(struct net_device *dev); |
| 1504 | int rtl8192_down(struct net_device *dev); |
| 1505 | int rtl8192_up(struct net_device *dev); |
| 1506 | void rtl8192_commit(struct net_device *dev); |
| 1507 | void rtl8192_set_chan(struct net_device *dev,short ch); |
| 1508 | void write_phy(struct net_device *dev, u8 adr, u8 data); |
| 1509 | void write_phy_cck(struct net_device *dev, u8 adr, u32 data); |
| 1510 | void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); |
| 1511 | void rtl8185_tx_antenna(struct net_device *dev, u8 ant); |
| 1512 | void rtl8192_set_rxconf(struct net_device *dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1513 | extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate); |
| 1514 | void CamResetAllEntry(struct net_device* dev); |
| 1515 | void EnableHWSecurityConfig8192(struct net_device *dev); |
| 1516 | void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent ); |
| 1517 | short rtl8192_is_tx_queue_empty(struct net_device *dev); |
| 1518 | |
| 1519 | #endif |