Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra114-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 4 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 5 | #include "skeleton.dtsi" |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 6 | |
| 7 | / { |
| 8 | compatible = "nvidia,tegra114"; |
| 9 | interrupt-parent = <&gic>; |
| 10 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 11 | aliases { |
| 12 | serial0 = &uarta; |
| 13 | serial1 = &uartb; |
| 14 | serial2 = &uartc; |
| 15 | serial3 = &uartd; |
| 16 | }; |
| 17 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 18 | gic: interrupt-controller { |
| 19 | compatible = "arm,cortex-a15-gic"; |
| 20 | #interrupt-cells = <3>; |
| 21 | interrupt-controller; |
| 22 | reg = <0x50041000 0x1000>, |
| 23 | <0x50042000 0x1000>, |
| 24 | <0x50044000 0x2000>, |
| 25 | <0x50046000 0x2000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 26 | interrupts = <GIC_PPI 9 |
| 27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | timer@60005000 { |
| 31 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 32 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 33 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 34 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 35 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 36 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 37 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 38 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 39 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | tegra_car: clock { |
Peter De Schrijver | 672d889 | 2013-04-03 17:40:48 +0300 | [diff] [blame] | 43 | compatible = "nvidia,tegra114-car"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 44 | reg = <0x60006000 0x1000>; |
| 45 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 46 | #reset-cells = <1>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 47 | }; |
| 48 | |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 49 | apbdma: dma { |
| 50 | compatible = "nvidia,tegra114-apbdma"; |
| 51 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 52 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 53 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 54 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 55 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 56 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 59 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 66 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 68 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 84 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 85 | resets = <&tegra_car 34>; |
| 86 | reset-names = "dma"; |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 87 | }; |
| 88 | |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 89 | ahb: ahb { |
| 90 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| 91 | reg = <0x6000c004 0x14c>; |
| 92 | }; |
| 93 | |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 94 | gpio: gpio { |
| 95 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 96 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 97 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 98 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 105 | #gpio-cells = <2>; |
| 106 | gpio-controller; |
| 107 | #interrupt-cells = <2>; |
| 108 | interrupt-controller; |
| 109 | }; |
| 110 | |
Laxman Dewangan | 031b77a | 2013-01-29 18:26:20 +0530 | [diff] [blame] | 111 | pinmux: pinmux { |
| 112 | compatible = "nvidia,tegra114-pinmux"; |
| 113 | reg = <0x70000868 0x148 /* Pad control registers */ |
| 114 | 0x70003000 0x40c>; /* Mux registers */ |
| 115 | }; |
| 116 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 117 | /* |
| 118 | * There are two serial driver i.e. 8250 based simple serial |
| 119 | * driver and APB DMA based serial driver for higher baudrate |
| 120 | * and performace. To enable the 8250 based driver, the compatible |
| 121 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| 122 | * the APB DMA based serial driver, the comptible is |
| 123 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| 124 | */ |
| 125 | uarta: serial@70006000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 126 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 127 | reg = <0x70006000 0x40>; |
| 128 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 129 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 130 | nvidia,dma-request-selector = <&apbdma 8>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 131 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 132 | resets = <&tegra_car 6>; |
| 133 | reset-names = "serial"; |
| 134 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 135 | }; |
| 136 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 137 | uartb: serial@70006040 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 138 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 139 | reg = <0x70006040 0x40>; |
| 140 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 141 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 142 | nvidia,dma-request-selector = <&apbdma 9>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 143 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 144 | resets = <&tegra_car 7>; |
| 145 | reset-names = "serial"; |
| 146 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 147 | }; |
| 148 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 149 | uartc: serial@70006200 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 150 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 151 | reg = <0x70006200 0x100>; |
| 152 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 153 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 154 | nvidia,dma-request-selector = <&apbdma 10>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 155 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 156 | resets = <&tegra_car 55>; |
| 157 | reset-names = "serial"; |
| 158 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 159 | }; |
| 160 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 161 | uartd: serial@70006300 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 162 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 163 | reg = <0x70006300 0x100>; |
| 164 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 165 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 166 | nvidia,dma-request-selector = <&apbdma 19>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 167 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 168 | resets = <&tegra_car 65>; |
| 169 | reset-names = "serial"; |
| 170 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 171 | }; |
| 172 | |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 173 | pwm: pwm { |
| 174 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 175 | reg = <0x7000a000 0x100>; |
| 176 | #pwm-cells = <2>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 177 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 178 | resets = <&tegra_car 17>; |
| 179 | reset-names = "pwm"; |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 180 | status = "disabled"; |
| 181 | }; |
| 182 | |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 183 | i2c@7000c000 { |
| 184 | compatible = "nvidia,tegra114-i2c"; |
| 185 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 186 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 187 | #address-cells = <1>; |
| 188 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 189 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 190 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 191 | resets = <&tegra_car 12>; |
| 192 | reset-names = "i2c"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 193 | status = "disabled"; |
| 194 | }; |
| 195 | |
| 196 | i2c@7000c400 { |
| 197 | compatible = "nvidia,tegra114-i2c"; |
| 198 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 199 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 200 | #address-cells = <1>; |
| 201 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 202 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 203 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 204 | resets = <&tegra_car 54>; |
| 205 | reset-names = "i2c"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 206 | status = "disabled"; |
| 207 | }; |
| 208 | |
| 209 | i2c@7000c500 { |
| 210 | compatible = "nvidia,tegra114-i2c"; |
| 211 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 212 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 213 | #address-cells = <1>; |
| 214 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 215 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 216 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 217 | resets = <&tegra_car 67>; |
| 218 | reset-names = "i2c"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
| 222 | i2c@7000c700 { |
| 223 | compatible = "nvidia,tegra114-i2c"; |
| 224 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 225 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 226 | #address-cells = <1>; |
| 227 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 228 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 229 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 230 | resets = <&tegra_car 103>; |
| 231 | reset-names = "i2c"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 232 | status = "disabled"; |
| 233 | }; |
| 234 | |
| 235 | i2c@7000d000 { |
| 236 | compatible = "nvidia,tegra114-i2c"; |
| 237 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 238 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 239 | #address-cells = <1>; |
| 240 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 241 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 242 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 243 | resets = <&tegra_car 47>; |
| 244 | reset-names = "i2c"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 248 | spi@7000d400 { |
| 249 | compatible = "nvidia,tegra114-spi"; |
| 250 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 251 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 252 | nvidia,dma-request-selector = <&apbdma 15>; |
| 253 | #address-cells = <1>; |
| 254 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 255 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 256 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 257 | resets = <&tegra_car 41>; |
| 258 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 259 | status = "disabled"; |
| 260 | }; |
| 261 | |
| 262 | spi@7000d600 { |
| 263 | compatible = "nvidia,tegra114-spi"; |
| 264 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 265 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 266 | nvidia,dma-request-selector = <&apbdma 16>; |
| 267 | #address-cells = <1>; |
| 268 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 269 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 270 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 271 | resets = <&tegra_car 44>; |
| 272 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 273 | status = "disabled"; |
| 274 | }; |
| 275 | |
| 276 | spi@7000d800 { |
| 277 | compatible = "nvidia,tegra114-spi"; |
| 278 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 279 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 280 | nvidia,dma-request-selector = <&apbdma 17>; |
| 281 | #address-cells = <1>; |
| 282 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 283 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 284 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 285 | resets = <&tegra_car 46>; |
| 286 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 287 | status = "disabled"; |
| 288 | }; |
| 289 | |
| 290 | spi@7000da00 { |
| 291 | compatible = "nvidia,tegra114-spi"; |
| 292 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 293 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 294 | nvidia,dma-request-selector = <&apbdma 18>; |
| 295 | #address-cells = <1>; |
| 296 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 297 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 298 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 299 | resets = <&tegra_car 68>; |
| 300 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 301 | status = "disabled"; |
| 302 | }; |
| 303 | |
| 304 | spi@7000dc00 { |
| 305 | compatible = "nvidia,tegra114-spi"; |
| 306 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 307 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 308 | nvidia,dma-request-selector = <&apbdma 27>; |
| 309 | #address-cells = <1>; |
| 310 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 311 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 312 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 313 | resets = <&tegra_car 104>; |
| 314 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 315 | status = "disabled"; |
| 316 | }; |
| 317 | |
| 318 | spi@7000de00 { |
| 319 | compatible = "nvidia,tegra114-spi"; |
| 320 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 321 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 322 | nvidia,dma-request-selector = <&apbdma 28>; |
| 323 | #address-cells = <1>; |
| 324 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 325 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 326 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 327 | resets = <&tegra_car 105>; |
| 328 | reset-names = "spi"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 329 | status = "disabled"; |
| 330 | }; |
| 331 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 332 | rtc { |
| 333 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 334 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 335 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 336 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 337 | }; |
| 338 | |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 339 | kbc { |
| 340 | compatible = "nvidia,tegra114-kbc"; |
| 341 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 342 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 343 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 344 | resets = <&tegra_car 36>; |
| 345 | reset-names = "kbc"; |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 346 | status = "disabled"; |
| 347 | }; |
| 348 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 349 | pmc { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 350 | compatible = "nvidia,tegra114-pmc"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 351 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 352 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 353 | clock-names = "pclk", "clk32k_in"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 354 | }; |
| 355 | |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 356 | iommu { |
| 357 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
Hiroshi Doyu | 4cca9593 | 2013-10-30 17:17:48 -0600 | [diff] [blame] | 358 | reg = <0x70019010 0x02c |
| 359 | 0x700191f0 0x010 |
| 360 | 0x70019228 0x074>; |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 361 | nvidia,#asids = <4>; |
| 362 | dma-window = <0 0x40000000>; |
| 363 | nvidia,swgroups = <0x18659fe>; |
| 364 | nvidia,ahb = <&ahb>; |
| 365 | }; |
| 366 | |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 367 | ahub { |
| 368 | compatible = "nvidia,tegra114-ahub"; |
| 369 | reg = <0x70080000 0x200>, |
| 370 | <0x70080200 0x100>, |
| 371 | <0x70081000 0x200>; |
| 372 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 373 | nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, |
| 374 | <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, |
| 375 | <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, |
| 376 | <&apbdma 29>; |
| 377 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
| 378 | <&tegra_car TEGRA114_CLK_APBIF>, |
| 379 | <&tegra_car TEGRA114_CLK_I2S0>, |
| 380 | <&tegra_car TEGRA114_CLK_I2S1>, |
| 381 | <&tegra_car TEGRA114_CLK_I2S2>, |
| 382 | <&tegra_car TEGRA114_CLK_I2S3>, |
| 383 | <&tegra_car TEGRA114_CLK_I2S4>, |
| 384 | <&tegra_car TEGRA114_CLK_DAM0>, |
| 385 | <&tegra_car TEGRA114_CLK_DAM1>, |
| 386 | <&tegra_car TEGRA114_CLK_DAM2>, |
| 387 | <&tegra_car TEGRA114_CLK_SPDIF_IN>, |
| 388 | <&tegra_car TEGRA114_CLK_AMX>, |
| 389 | <&tegra_car TEGRA114_CLK_ADX>; |
| 390 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 391 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 392 | "spdif_in", "amx", "adx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 393 | resets = <&tegra_car 106>, /* d_audio */ |
| 394 | <&tegra_car 107>, /* apbif */ |
| 395 | <&tegra_car 30>, /* i2s0 */ |
| 396 | <&tegra_car 11>, /* i2s1 */ |
| 397 | <&tegra_car 18>, /* i2s2 */ |
| 398 | <&tegra_car 101>, /* i2s3 */ |
| 399 | <&tegra_car 102>, /* i2s4 */ |
| 400 | <&tegra_car 108>, /* dam0 */ |
| 401 | <&tegra_car 109>, /* dam1 */ |
| 402 | <&tegra_car 110>, /* dam2 */ |
| 403 | <&tegra_car 10>, /* spdif */ |
| 404 | <&tegra_car 153>, /* amx */ |
| 405 | <&tegra_car 154>; /* adx */ |
| 406 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 407 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 408 | "spdif", "amx", "adx"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 409 | ranges; |
| 410 | #address-cells = <1>; |
| 411 | #size-cells = <1>; |
| 412 | |
| 413 | tegra_i2s0: i2s@70080300 { |
| 414 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 415 | reg = <0x70080300 0x100>; |
| 416 | nvidia,ahub-cif-ids = <4 4>; |
| 417 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 418 | resets = <&tegra_car 30>; |
| 419 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 420 | status = "disabled"; |
| 421 | }; |
| 422 | |
| 423 | tegra_i2s1: i2s@70080400 { |
| 424 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 425 | reg = <0x70080400 0x100>; |
| 426 | nvidia,ahub-cif-ids = <5 5>; |
| 427 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 428 | resets = <&tegra_car 11>; |
| 429 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 430 | status = "disabled"; |
| 431 | }; |
| 432 | |
| 433 | tegra_i2s2: i2s@70080500 { |
| 434 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 435 | reg = <0x70080500 0x100>; |
| 436 | nvidia,ahub-cif-ids = <6 6>; |
| 437 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 438 | resets = <&tegra_car 18>; |
| 439 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 440 | status = "disabled"; |
| 441 | }; |
| 442 | |
| 443 | tegra_i2s3: i2s@70080600 { |
| 444 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 445 | reg = <0x70080600 0x100>; |
| 446 | nvidia,ahub-cif-ids = <7 7>; |
| 447 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 448 | resets = <&tegra_car 101>; |
| 449 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
| 453 | tegra_i2s4: i2s@70080700 { |
| 454 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 455 | reg = <0x70080700 0x100>; |
| 456 | nvidia,ahub-cif-ids = <8 8>; |
| 457 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 458 | resets = <&tegra_car 102>; |
| 459 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 460 | status = "disabled"; |
| 461 | }; |
| 462 | }; |
| 463 | |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 464 | sdhci@78000000 { |
| 465 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 466 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 467 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 468 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 469 | resets = <&tegra_car 14>; |
| 470 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 471 | status = "disable"; |
| 472 | }; |
| 473 | |
| 474 | sdhci@78000200 { |
| 475 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 476 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 477 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 478 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 479 | resets = <&tegra_car 9>; |
| 480 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 481 | status = "disable"; |
| 482 | }; |
| 483 | |
| 484 | sdhci@78000400 { |
| 485 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 486 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 487 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 488 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 489 | resets = <&tegra_car 69>; |
| 490 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 491 | status = "disable"; |
| 492 | }; |
| 493 | |
| 494 | sdhci@78000600 { |
| 495 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 496 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 497 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 498 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 499 | resets = <&tegra_car 15>; |
| 500 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 501 | status = "disable"; |
| 502 | }; |
| 503 | |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 504 | usb@7d000000 { |
| 505 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 506 | reg = <0x7d000000 0x4000>; |
| 507 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 508 | phy_type = "utmi"; |
| 509 | clocks = <&tegra_car TEGRA114_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 510 | resets = <&tegra_car 22>; |
| 511 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 512 | nvidia,phy = <&phy1>; |
| 513 | status = "disabled"; |
| 514 | }; |
| 515 | |
| 516 | phy1: usb-phy@7d000000 { |
| 517 | compatible = "nvidia,tegra30-usb-phy"; |
| 518 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 519 | phy_type = "utmi"; |
| 520 | clocks = <&tegra_car TEGRA114_CLK_USBD>, |
| 521 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 522 | <&tegra_car TEGRA114_CLK_USBD>; |
| 523 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 524 | nvidia,hssync-start-delay = <0>; |
| 525 | nvidia,idle-wait-delay = <17>; |
| 526 | nvidia,elastic-limit = <16>; |
| 527 | nvidia,term-range-adj = <6>; |
| 528 | nvidia,xcvr-setup = <9>; |
| 529 | nvidia,xcvr-lsfslew = <0>; |
| 530 | nvidia,xcvr-lsrslew = <3>; |
| 531 | nvidia,hssquelch-level = <2>; |
| 532 | nvidia,hsdiscon-level = <5>; |
| 533 | nvidia,xcvr-hsslew = <12>; |
| 534 | status = "disabled"; |
| 535 | }; |
| 536 | |
| 537 | usb@7d008000 { |
| 538 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 539 | reg = <0x7d008000 0x4000>; |
| 540 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 541 | phy_type = "utmi"; |
| 542 | clocks = <&tegra_car TEGRA114_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame^] | 543 | resets = <&tegra_car 59>; |
| 544 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 545 | nvidia,phy = <&phy3>; |
| 546 | status = "disabled"; |
| 547 | }; |
| 548 | |
| 549 | phy3: usb-phy@7d008000 { |
| 550 | compatible = "nvidia,tegra30-usb-phy"; |
| 551 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 552 | phy_type = "utmi"; |
| 553 | clocks = <&tegra_car TEGRA114_CLK_USB3>, |
| 554 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 555 | <&tegra_car TEGRA114_CLK_USBD>; |
| 556 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 557 | nvidia,hssync-start-delay = <0>; |
| 558 | nvidia,idle-wait-delay = <17>; |
| 559 | nvidia,elastic-limit = <16>; |
| 560 | nvidia,term-range-adj = <6>; |
| 561 | nvidia,xcvr-setup = <9>; |
| 562 | nvidia,xcvr-lsfslew = <0>; |
| 563 | nvidia,xcvr-lsrslew = <3>; |
| 564 | nvidia,hssquelch-level = <2>; |
| 565 | nvidia,hsdiscon-level = <5>; |
| 566 | nvidia,xcvr-hsslew = <12>; |
| 567 | status = "disabled"; |
| 568 | }; |
| 569 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 570 | cpus { |
| 571 | #address-cells = <1>; |
| 572 | #size-cells = <0>; |
| 573 | |
| 574 | cpu@0 { |
| 575 | device_type = "cpu"; |
| 576 | compatible = "arm,cortex-a15"; |
| 577 | reg = <0>; |
| 578 | }; |
| 579 | |
| 580 | cpu@1 { |
| 581 | device_type = "cpu"; |
| 582 | compatible = "arm,cortex-a15"; |
| 583 | reg = <1>; |
| 584 | }; |
| 585 | |
| 586 | cpu@2 { |
| 587 | device_type = "cpu"; |
| 588 | compatible = "arm,cortex-a15"; |
| 589 | reg = <2>; |
| 590 | }; |
| 591 | |
| 592 | cpu@3 { |
| 593 | device_type = "cpu"; |
| 594 | compatible = "arm,cortex-a15"; |
| 595 | reg = <3>; |
| 596 | }; |
| 597 | }; |
| 598 | |
| 599 | timer { |
| 600 | compatible = "arm,armv7-timer"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 601 | interrupts = |
| 602 | <GIC_PPI 13 |
| 603 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 604 | <GIC_PPI 14 |
| 605 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 606 | <GIC_PPI 11 |
| 607 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 608 | <GIC_PPI 10 |
| 609 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 610 | }; |
| 611 | }; |