Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 1 | /* |
| 2 | * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver |
| 3 | * |
| 4 | * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License version |
| 8 | * 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * Author: Yang, Bin <bin.yang@intel.com> |
| 16 | */ |
| 17 | |
| 18 | #include <linux/interrupt.h> |
Paul Gortmaker | f1fb9c6 | 2015-04-30 21:47:39 -0400 | [diff] [blame] | 19 | #include <linux/module.h> |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/gpio.h> |
Lee Jones | 8dbf2aa | 2014-06-19 15:40:41 +0100 | [diff] [blame] | 22 | #include <linux/seq_file.h> |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 23 | #include <linux/bitops.h> |
| 24 | #include <linux/regmap.h> |
| 25 | #include <linux/mfd/intel_soc_pmic.h> |
| 26 | |
| 27 | #define CRYSTALCOVE_GPIO_NUM 16 |
Shobhit Kumar | e189ca5 | 2015-03-12 22:01:26 +0530 | [diff] [blame] | 28 | #define CRYSTALCOVE_VGPIO_NUM 95 |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 29 | |
| 30 | #define UPDATE_IRQ_TYPE BIT(0) |
| 31 | #define UPDATE_IRQ_MASK BIT(1) |
| 32 | |
| 33 | #define GPIO0IRQ 0x0b |
| 34 | #define GPIO1IRQ 0x0c |
| 35 | #define MGPIO0IRQS0 0x19 |
| 36 | #define MGPIO1IRQS0 0x1a |
| 37 | #define MGPIO0IRQSX 0x1b |
| 38 | #define MGPIO1IRQSX 0x1c |
| 39 | #define GPIO0P0CTLO 0x2b |
| 40 | #define GPIO0P0CTLI 0x33 |
| 41 | #define GPIO1P0CTLO 0x3b |
| 42 | #define GPIO1P0CTLI 0x43 |
Shobhit Kumar | e189ca5 | 2015-03-12 22:01:26 +0530 | [diff] [blame] | 43 | #define GPIOPANELCTL 0x52 |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 44 | |
| 45 | #define CTLI_INTCNT_DIS (0) |
| 46 | #define CTLI_INTCNT_NE (1 << 1) |
| 47 | #define CTLI_INTCNT_PE (2 << 1) |
| 48 | #define CTLI_INTCNT_BE (3 << 1) |
| 49 | |
| 50 | #define CTLO_DIR_IN (0) |
| 51 | #define CTLO_DIR_OUT (1 << 5) |
| 52 | |
| 53 | #define CTLO_DRV_CMOS (0) |
| 54 | #define CTLO_DRV_OD (1 << 4) |
| 55 | |
| 56 | #define CTLO_DRV_REN (1 << 3) |
| 57 | |
| 58 | #define CTLO_RVAL_2KDW (0) |
| 59 | #define CTLO_RVAL_2KUP (1 << 1) |
| 60 | #define CTLO_RVAL_50KDW (2 << 1) |
| 61 | #define CTLO_RVAL_50KUP (3 << 1) |
| 62 | |
| 63 | #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) |
| 64 | #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) |
| 65 | |
| 66 | enum ctrl_register { |
| 67 | CTRL_IN, |
| 68 | CTRL_OUT, |
| 69 | }; |
| 70 | |
| 71 | /** |
| 72 | * struct crystalcove_gpio - Crystal Cove GPIO controller |
| 73 | * @buslock: for bus lock/sync and unlock. |
| 74 | * @chip: the abstract gpio_chip structure. |
| 75 | * @regmap: the regmap from the parent device. |
| 76 | * @update: pending IRQ setting update, to be written to the chip upon unlock. |
| 77 | * @intcnt_value: the Interrupt Detect value to be written. |
| 78 | * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. |
| 79 | */ |
| 80 | struct crystalcove_gpio { |
| 81 | struct mutex buslock; /* irq_bus_lock */ |
| 82 | struct gpio_chip chip; |
| 83 | struct regmap *regmap; |
| 84 | int update; |
| 85 | int intcnt_value; |
| 86 | bool set_irq_mask; |
| 87 | }; |
| 88 | |
| 89 | static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc) |
| 90 | { |
| 91 | return container_of(gc, struct crystalcove_gpio, chip); |
| 92 | } |
| 93 | |
| 94 | static inline int to_reg(int gpio, enum ctrl_register reg_type) |
| 95 | { |
| 96 | int reg; |
| 97 | |
Daniel Lockyer | 38e003f | 2015-06-10 14:26:27 +0100 | [diff] [blame] | 98 | if (gpio == 94) |
Shobhit Kumar | e189ca5 | 2015-03-12 22:01:26 +0530 | [diff] [blame] | 99 | return GPIOPANELCTL; |
Shobhit Kumar | e189ca5 | 2015-03-12 22:01:26 +0530 | [diff] [blame] | 100 | |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 101 | if (reg_type == CTRL_IN) { |
| 102 | if (gpio < 8) |
| 103 | reg = GPIO0P0CTLI; |
| 104 | else |
| 105 | reg = GPIO1P0CTLI; |
| 106 | } else { |
| 107 | if (gpio < 8) |
| 108 | reg = GPIO0P0CTLO; |
| 109 | else |
| 110 | reg = GPIO1P0CTLO; |
| 111 | } |
| 112 | |
| 113 | return reg + gpio % 8; |
| 114 | } |
| 115 | |
| 116 | static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, |
| 117 | int gpio) |
| 118 | { |
| 119 | u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0; |
| 120 | int mask = BIT(gpio % 8); |
| 121 | |
| 122 | if (cg->set_irq_mask) |
| 123 | regmap_update_bits(cg->regmap, mirqs0, mask, mask); |
| 124 | else |
| 125 | regmap_update_bits(cg->regmap, mirqs0, mask, 0); |
| 126 | } |
| 127 | |
| 128 | static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) |
| 129 | { |
| 130 | int reg = to_reg(gpio, CTRL_IN); |
| 131 | |
| 132 | regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); |
| 133 | } |
| 134 | |
| 135 | static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) |
| 136 | { |
| 137 | struct crystalcove_gpio *cg = to_cg(chip); |
| 138 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 139 | if (gpio > CRYSTALCOVE_VGPIO_NUM) |
| 140 | return 0; |
| 141 | |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 142 | return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT), |
| 143 | CTLO_INPUT_SET); |
| 144 | } |
| 145 | |
| 146 | static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, |
| 147 | int value) |
| 148 | { |
| 149 | struct crystalcove_gpio *cg = to_cg(chip); |
| 150 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 151 | if (gpio > CRYSTALCOVE_VGPIO_NUM) |
| 152 | return 0; |
| 153 | |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 154 | return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT), |
| 155 | CTLO_OUTPUT_SET | value); |
| 156 | } |
| 157 | |
| 158 | static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio) |
| 159 | { |
| 160 | struct crystalcove_gpio *cg = to_cg(chip); |
| 161 | int ret; |
| 162 | unsigned int val; |
| 163 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 164 | if (gpio > CRYSTALCOVE_VGPIO_NUM) |
| 165 | return 0; |
| 166 | |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 167 | ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val); |
| 168 | if (ret) |
| 169 | return ret; |
| 170 | |
| 171 | return val & 0x1; |
| 172 | } |
| 173 | |
| 174 | static void crystalcove_gpio_set(struct gpio_chip *chip, |
| 175 | unsigned gpio, int value) |
| 176 | { |
| 177 | struct crystalcove_gpio *cg = to_cg(chip); |
| 178 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 179 | if (gpio > CRYSTALCOVE_VGPIO_NUM) |
| 180 | return; |
| 181 | |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 182 | if (value) |
| 183 | regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1); |
| 184 | else |
| 185 | regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0); |
| 186 | } |
| 187 | |
| 188 | static int crystalcove_irq_type(struct irq_data *data, unsigned type) |
| 189 | { |
| 190 | struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); |
| 191 | |
| 192 | switch (type) { |
| 193 | case IRQ_TYPE_NONE: |
| 194 | cg->intcnt_value = CTLI_INTCNT_DIS; |
| 195 | break; |
| 196 | case IRQ_TYPE_EDGE_BOTH: |
| 197 | cg->intcnt_value = CTLI_INTCNT_BE; |
| 198 | break; |
| 199 | case IRQ_TYPE_EDGE_RISING: |
| 200 | cg->intcnt_value = CTLI_INTCNT_PE; |
| 201 | break; |
| 202 | case IRQ_TYPE_EDGE_FALLING: |
| 203 | cg->intcnt_value = CTLI_INTCNT_NE; |
| 204 | break; |
| 205 | default: |
| 206 | return -EINVAL; |
| 207 | } |
| 208 | |
| 209 | cg->update |= UPDATE_IRQ_TYPE; |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | static void crystalcove_bus_lock(struct irq_data *data) |
| 215 | { |
| 216 | struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); |
| 217 | |
| 218 | mutex_lock(&cg->buslock); |
| 219 | } |
| 220 | |
| 221 | static void crystalcove_bus_sync_unlock(struct irq_data *data) |
| 222 | { |
| 223 | struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); |
| 224 | int gpio = data->hwirq; |
| 225 | |
| 226 | if (cg->update & UPDATE_IRQ_TYPE) |
| 227 | crystalcove_update_irq_ctrl(cg, gpio); |
| 228 | if (cg->update & UPDATE_IRQ_MASK) |
| 229 | crystalcove_update_irq_mask(cg, gpio); |
| 230 | cg->update = 0; |
| 231 | |
| 232 | mutex_unlock(&cg->buslock); |
| 233 | } |
| 234 | |
| 235 | static void crystalcove_irq_unmask(struct irq_data *data) |
| 236 | { |
| 237 | struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); |
| 238 | |
| 239 | cg->set_irq_mask = false; |
| 240 | cg->update |= UPDATE_IRQ_MASK; |
| 241 | } |
| 242 | |
| 243 | static void crystalcove_irq_mask(struct irq_data *data) |
| 244 | { |
| 245 | struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); |
| 246 | |
| 247 | cg->set_irq_mask = true; |
| 248 | cg->update |= UPDATE_IRQ_MASK; |
| 249 | } |
| 250 | |
| 251 | static struct irq_chip crystalcove_irqchip = { |
| 252 | .name = "Crystal Cove", |
| 253 | .irq_mask = crystalcove_irq_mask, |
| 254 | .irq_unmask = crystalcove_irq_unmask, |
| 255 | .irq_set_type = crystalcove_irq_type, |
| 256 | .irq_bus_lock = crystalcove_bus_lock, |
| 257 | .irq_bus_sync_unlock = crystalcove_bus_sync_unlock, |
Aaron Lu | 61e749d | 2015-05-28 10:58:49 +0800 | [diff] [blame] | 258 | .flags = IRQCHIP_SKIP_SET_WAKE, |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) |
| 262 | { |
| 263 | struct crystalcove_gpio *cg = data; |
| 264 | unsigned int p0, p1; |
| 265 | int pending; |
| 266 | int gpio; |
| 267 | unsigned int virq; |
| 268 | |
| 269 | if (regmap_read(cg->regmap, GPIO0IRQ, &p0) || |
| 270 | regmap_read(cg->regmap, GPIO1IRQ, &p1)) |
| 271 | return IRQ_NONE; |
| 272 | |
| 273 | regmap_write(cg->regmap, GPIO0IRQ, p0); |
| 274 | regmap_write(cg->regmap, GPIO1IRQ, p1); |
| 275 | |
| 276 | pending = p0 | p1 << 8; |
| 277 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 278 | for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) { |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 279 | if (pending & BIT(gpio)) { |
| 280 | virq = irq_find_mapping(cg->chip.irqdomain, gpio); |
Aaron Lu | e733a2f | 2015-01-12 10:09:32 +0800 | [diff] [blame] | 281 | handle_nested_irq(virq); |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 282 | } |
| 283 | } |
| 284 | |
| 285 | return IRQ_HANDLED; |
| 286 | } |
| 287 | |
| 288 | static void crystalcove_gpio_dbg_show(struct seq_file *s, |
| 289 | struct gpio_chip *chip) |
| 290 | { |
| 291 | struct crystalcove_gpio *cg = to_cg(chip); |
| 292 | int gpio, offset; |
| 293 | unsigned int ctlo, ctli, mirqs0, mirqsx, irq; |
| 294 | |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 295 | for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) { |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 296 | regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); |
| 297 | regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli); |
| 298 | regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0, |
| 299 | &mirqs0); |
| 300 | regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX, |
| 301 | &mirqsx); |
| 302 | regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ, |
| 303 | &irq); |
| 304 | |
| 305 | offset = gpio % 8; |
| 306 | seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n", |
| 307 | gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", |
| 308 | ctli & 0x1 ? "hi" : "lo", |
| 309 | ctli & CTLI_INTCNT_NE ? "fall" : " ", |
| 310 | ctli & CTLI_INTCNT_PE ? "rise" : " ", |
| 311 | ctlo, |
| 312 | mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask", |
| 313 | mirqsx & BIT(offset) ? "sx mask " : "sx unmask", |
| 314 | irq & BIT(offset) ? "pending" : " "); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | static int crystalcove_gpio_probe(struct platform_device *pdev) |
| 319 | { |
| 320 | int irq = platform_get_irq(pdev, 0); |
| 321 | struct crystalcove_gpio *cg; |
| 322 | int retval; |
| 323 | struct device *dev = pdev->dev.parent; |
| 324 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
| 325 | |
| 326 | if (irq < 0) |
| 327 | return irq; |
| 328 | |
| 329 | cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL); |
| 330 | if (!cg) |
| 331 | return -ENOMEM; |
| 332 | |
| 333 | platform_set_drvdata(pdev, cg); |
| 334 | |
| 335 | mutex_init(&cg->buslock); |
| 336 | cg->chip.label = KBUILD_MODNAME; |
| 337 | cg->chip.direction_input = crystalcove_gpio_dir_in; |
| 338 | cg->chip.direction_output = crystalcove_gpio_dir_out; |
| 339 | cg->chip.get = crystalcove_gpio_get; |
| 340 | cg->chip.set = crystalcove_gpio_set; |
| 341 | cg->chip.base = -1; |
Aaron Lu | dcdc301 | 2014-09-25 10:57:26 +0800 | [diff] [blame] | 342 | cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM; |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 343 | cg->chip.can_sleep = true; |
| 344 | cg->chip.dev = dev; |
| 345 | cg->chip.dbg_show = crystalcove_gpio_dbg_show; |
| 346 | cg->regmap = pmic->regmap; |
| 347 | |
| 348 | retval = gpiochip_add(&cg->chip); |
| 349 | if (retval) { |
| 350 | dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval); |
| 351 | return retval; |
| 352 | } |
| 353 | |
| 354 | gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0, |
| 355 | handle_simple_irq, IRQ_TYPE_NONE); |
| 356 | |
| 357 | retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler, |
| 358 | IRQF_ONESHOT, KBUILD_MODNAME, cg); |
| 359 | |
| 360 | if (retval) { |
| 361 | dev_warn(&pdev->dev, "request irq failed: %d\n", retval); |
| 362 | goto out_remove_gpio; |
| 363 | } |
| 364 | |
| 365 | return 0; |
| 366 | |
| 367 | out_remove_gpio: |
Linus Walleij | da26d5d | 2014-09-16 15:11:41 -0700 | [diff] [blame] | 368 | gpiochip_remove(&cg->chip); |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 369 | return retval; |
| 370 | } |
| 371 | |
| 372 | static int crystalcove_gpio_remove(struct platform_device *pdev) |
| 373 | { |
| 374 | struct crystalcove_gpio *cg = platform_get_drvdata(pdev); |
| 375 | int irq = platform_get_irq(pdev, 0); |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 376 | |
Linus Walleij | da26d5d | 2014-09-16 15:11:41 -0700 | [diff] [blame] | 377 | gpiochip_remove(&cg->chip); |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 378 | if (irq >= 0) |
| 379 | free_irq(irq, cg); |
Linus Walleij | da26d5d | 2014-09-16 15:11:41 -0700 | [diff] [blame] | 380 | return 0; |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 381 | } |
| 382 | |
| 383 | static struct platform_driver crystalcove_gpio_driver = { |
| 384 | .probe = crystalcove_gpio_probe, |
| 385 | .remove = crystalcove_gpio_remove, |
| 386 | .driver = { |
| 387 | .name = "crystal_cove_gpio", |
Zhu, Lejun | 104fb1d | 2014-06-03 13:26:04 +0800 | [diff] [blame] | 388 | }, |
| 389 | }; |
| 390 | |
| 391 | module_platform_driver(crystalcove_gpio_driver); |
| 392 | |
| 393 | MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>"); |
| 394 | MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver"); |
| 395 | MODULE_LICENSE("GPL v2"); |