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David S. Miller99c4a632009-09-25 12:14:43 -07001/*
2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
3 *
4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
Marc Kleine-Buddedbe91322010-10-21 01:01:13 +00005 * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de>
David S. Miller99c4a632009-09-25 12:14:43 -07006 *
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
10 *
11 * Send feedback to <socketcan-users@lists.berlios.de>
12 *
13 *
14 * Your platform definition file should specify something like:
15 *
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
18 * };
19 *
20 * at91_add_device_can(&ek_can_data);
21 *
22 */
23
24#include <linux/clk.h>
25#include <linux/errno.h>
26#include <linux/if_arp.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
32#include <linux/platform_device.h>
33#include <linux/skbuff.h>
34#include <linux/spinlock.h>
35#include <linux/string.h>
36#include <linux/types.h>
37
David S. Miller99c4a632009-09-25 12:14:43 -070038#include <linux/can/dev.h>
39#include <linux/can/error.h>
40
41#include <mach/board.h>
42
43#define DRV_NAME "at91_can"
44#define AT91_NAPI_WEIGHT 12
45
46/*
47 * RX/TX Mailbox split
48 * don't dare to touch
49 */
50#define AT91_MB_RX_NUM 12
51#define AT91_MB_TX_SHIFT 2
52
53#define AT91_MB_RX_FIRST 0
54#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
55
56#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
57#define AT91_MB_RX_SPLIT 8
58#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
59#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
60
61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
64
65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
69
70/* Common registers */
71enum at91_reg {
72 AT91_MR = 0x000,
73 AT91_IER = 0x004,
74 AT91_IDR = 0x008,
75 AT91_IMR = 0x00C,
76 AT91_SR = 0x010,
77 AT91_BR = 0x014,
78 AT91_TIM = 0x018,
79 AT91_TIMESTP = 0x01C,
80 AT91_ECR = 0x020,
81 AT91_TCR = 0x024,
82 AT91_ACR = 0x028,
83};
84
85/* Mailbox registers (0 <= i <= 15) */
86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
94
95/* Register bits */
96#define AT91_MR_CANEN BIT(0)
97#define AT91_MR_LPM BIT(1)
98#define AT91_MR_ABM BIT(2)
99#define AT91_MR_OVL BIT(3)
100#define AT91_MR_TEOF BIT(4)
101#define AT91_MR_TTM BIT(5)
102#define AT91_MR_TIMFRZ BIT(6)
103#define AT91_MR_DRPT BIT(7)
104
105#define AT91_SR_RBSY BIT(29)
106
107#define AT91_MMR_PRIO_SHIFT (16)
108
109#define AT91_MID_MIDE BIT(29)
110
111#define AT91_MSR_MRTR BIT(20)
112#define AT91_MSR_MABT BIT(22)
113#define AT91_MSR_MRDY BIT(23)
114#define AT91_MSR_MMI BIT(24)
115
116#define AT91_MCR_MRTR BIT(20)
117#define AT91_MCR_MTCR BIT(23)
118
119/* Mailbox Modes */
120enum at91_mb_mode {
121 AT91_MB_MODE_DISABLED = 0,
122 AT91_MB_MODE_RX = 1,
123 AT91_MB_MODE_RX_OVRWR = 2,
124 AT91_MB_MODE_TX = 3,
125 AT91_MB_MODE_CONSUMER = 4,
126 AT91_MB_MODE_PRODUCER = 5,
127};
128
129/* Interrupt mask bits */
130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
131 - (1 << AT91_MB_RX_FIRST))
132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
133 - (1 << AT91_MB_TX_FIRST))
134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
135
136#define AT91_IRQ_ERRA (1 << 16)
137#define AT91_IRQ_WARN (1 << 17)
138#define AT91_IRQ_ERRP (1 << 18)
139#define AT91_IRQ_BOFF (1 << 19)
140#define AT91_IRQ_SLEEP (1 << 20)
141#define AT91_IRQ_WAKEUP (1 << 21)
142#define AT91_IRQ_TOVF (1 << 22)
143#define AT91_IRQ_TSTP (1 << 23)
144#define AT91_IRQ_CERR (1 << 24)
145#define AT91_IRQ_SERR (1 << 25)
146#define AT91_IRQ_AERR (1 << 26)
147#define AT91_IRQ_FERR (1 << 27)
148#define AT91_IRQ_BERR (1 << 28)
149
150#define AT91_IRQ_ERR_ALL (0x1fff0000)
151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
154 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
155
156#define AT91_IRQ_ALL (0x1fffffff)
157
158struct at91_priv {
159 struct can_priv can; /* must be the first member! */
160 struct net_device *dev;
161 struct napi_struct napi;
162
163 void __iomem *reg_base;
164
165 u32 reg_sr;
166 unsigned int tx_next;
167 unsigned int tx_echo;
168 unsigned int rx_next;
169
170 struct clk *clk;
171 struct at91_can_data *pdata;
172};
173
174static struct can_bittiming_const at91_bittiming_const = {
175 .tseg1_min = 4,
176 .tseg1_max = 16,
177 .tseg2_min = 2,
178 .tseg2_max = 8,
179 .sjw_max = 4,
180 .brp_min = 2,
181 .brp_max = 128,
182 .brp_inc = 1,
183};
184
185static inline int get_tx_next_mb(const struct at91_priv *priv)
186{
187 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
188}
189
190static inline int get_tx_next_prio(const struct at91_priv *priv)
191{
192 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
193}
194
195static inline int get_tx_echo_mb(const struct at91_priv *priv)
196{
197 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
198}
199
200static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
201{
202 return readl(priv->reg_base + reg);
203}
204
205static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
206 u32 value)
207{
208 writel(value, priv->reg_base + reg);
209}
210
211static inline void set_mb_mode_prio(const struct at91_priv *priv,
212 unsigned int mb, enum at91_mb_mode mode, int prio)
213{
214 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
215}
216
217static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
218 enum at91_mb_mode mode)
219{
220 set_mb_mode_prio(priv, mb, mode, 0);
221}
222
David S. Miller99c4a632009-09-25 12:14:43 -0700223/*
224 * Swtich transceiver on or off
225 */
226static void at91_transceiver_switch(const struct at91_priv *priv, int on)
227{
228 if (priv->pdata && priv->pdata->transceiver_switch)
229 priv->pdata->transceiver_switch(on);
230}
231
232static void at91_setup_mailboxes(struct net_device *dev)
233{
234 struct at91_priv *priv = netdev_priv(dev);
235 unsigned int i;
236
237 /*
238 * The first 12 mailboxes are used as a reception FIFO. The
239 * last mailbox is configured with overwrite option. The
240 * overwrite flag indicates a FIFO overflow.
241 */
242 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
243 set_mb_mode(priv, i, AT91_MB_MODE_RX);
244 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
245
Marc Kleine-Budde8a0e0a42010-10-21 01:01:14 +0000246 /* reset acceptance mask and id register */
247 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) {
248 at91_write(priv, AT91_MAM(i), 0x0 );
249 at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
250 }
251
David S. Miller99c4a632009-09-25 12:14:43 -0700252 /* The last 4 mailboxes are used for transmitting. */
253 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
254 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
255
256 /* Reset tx and rx helper pointers */
257 priv->tx_next = priv->tx_echo = priv->rx_next = 0;
258}
259
260static int at91_set_bittiming(struct net_device *dev)
261{
262 const struct at91_priv *priv = netdev_priv(dev);
263 const struct can_bittiming *bt = &priv->can.bittiming;
264 u32 reg_br;
265
Marc Kleine-Buddedbe91322010-10-21 01:01:13 +0000266 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
267 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
David S. Miller99c4a632009-09-25 12:14:43 -0700268 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
269 ((bt->phase_seg2 - 1) << 0);
270
271 dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br);
272
273 at91_write(priv, AT91_BR, reg_br);
274
275 return 0;
276}
277
278static void at91_chip_start(struct net_device *dev)
279{
280 struct at91_priv *priv = netdev_priv(dev);
281 u32 reg_mr, reg_ier;
282
283 /* disable interrupts */
284 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
285
286 /* disable chip */
287 reg_mr = at91_read(priv, AT91_MR);
288 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
289
290 at91_setup_mailboxes(dev);
291 at91_transceiver_switch(priv, 1);
292
293 /* enable chip */
294 at91_write(priv, AT91_MR, AT91_MR_CANEN);
295
296 priv->can.state = CAN_STATE_ERROR_ACTIVE;
297
298 /* Enable interrupts */
299 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
300 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
301 at91_write(priv, AT91_IER, reg_ier);
302}
303
304static void at91_chip_stop(struct net_device *dev, enum can_state state)
305{
306 struct at91_priv *priv = netdev_priv(dev);
307 u32 reg_mr;
308
309 /* disable interrupts */
310 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
311
312 reg_mr = at91_read(priv, AT91_MR);
313 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
314
315 at91_transceiver_switch(priv, 0);
316 priv->can.state = state;
317}
318
319/*
320 * theory of operation:
321 *
322 * According to the datasheet priority 0 is the highest priority, 15
323 * is the lowest. If two mailboxes have the same priority level the
324 * message of the mailbox with the lowest number is sent first.
325 *
326 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
327 * the next mailbox with prio 0, and so on, until all mailboxes are
328 * used. Then we start from the beginning with mailbox
329 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
330 * prio 1. When we reach the last mailbox with prio 15, we have to
331 * stop sending, waiting for all messages to be delivered, then start
332 * again with mailbox AT91_MB_TX_FIRST prio 0.
333 *
334 * We use the priv->tx_next as counter for the next transmission
335 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
336 * encode the mailbox number, the upper 4 bits the mailbox priority:
337 *
338 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
339 * (mb - AT91_MB_TX_FIRST);
340 *
341 */
342static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
343{
344 struct at91_priv *priv = netdev_priv(dev);
345 struct net_device_stats *stats = &dev->stats;
346 struct can_frame *cf = (struct can_frame *)skb->data;
347 unsigned int mb, prio;
348 u32 reg_mid, reg_mcr;
349
Oliver Hartkopp3ccd4c62010-01-12 02:00:46 -0800350 if (can_dropped_invalid_skb(dev, skb))
351 return NETDEV_TX_OK;
352
David S. Miller99c4a632009-09-25 12:14:43 -0700353 mb = get_tx_next_mb(priv);
354 prio = get_tx_next_prio(priv);
355
356 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
357 netif_stop_queue(dev);
358
359 dev_err(dev->dev.parent,
360 "BUG! TX buffer full when queue awake!\n");
361 return NETDEV_TX_BUSY;
362 }
363
364 if (cf->can_id & CAN_EFF_FLAG)
365 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
366 else
367 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
368
369 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
370 (cf->can_dlc << 16) | AT91_MCR_MTCR;
371
372 /* disable MB while writing ID (see datasheet) */
373 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
374 at91_write(priv, AT91_MID(mb), reg_mid);
375 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
376
377 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
378 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
379
380 /* This triggers transmission */
381 at91_write(priv, AT91_MCR(mb), reg_mcr);
382
383 stats->tx_bytes += cf->can_dlc;
David S. Miller99c4a632009-09-25 12:14:43 -0700384
385 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
386 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
387
388 /*
389 * we have to stop the queue and deliver all messages in case
390 * of a prio+mb counter wrap around. This is the case if
391 * tx_next buffer prio and mailbox equals 0.
392 *
393 * also stop the queue if next buffer is still in use
394 * (== not ready)
395 */
396 priv->tx_next++;
397 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
398 AT91_MSR_MRDY) ||
399 (priv->tx_next & AT91_NEXT_MASK) == 0)
400 netif_stop_queue(dev);
401
402 /* Enable interrupt for this mailbox */
403 at91_write(priv, AT91_IER, 1 << mb);
404
405 return NETDEV_TX_OK;
406}
407
408/**
409 * at91_activate_rx_low - activate lower rx mailboxes
410 * @priv: a91 context
411 *
412 * Reenables the lower mailboxes for reception of new CAN messages
413 */
414static inline void at91_activate_rx_low(const struct at91_priv *priv)
415{
416 u32 mask = AT91_MB_RX_LOW_MASK;
417 at91_write(priv, AT91_TCR, mask);
418}
419
420/**
421 * at91_activate_rx_mb - reactive single rx mailbox
422 * @priv: a91 context
423 * @mb: mailbox to reactivate
424 *
425 * Reenables given mailbox for reception of new CAN messages
426 */
427static inline void at91_activate_rx_mb(const struct at91_priv *priv,
428 unsigned int mb)
429{
430 u32 mask = 1 << mb;
431 at91_write(priv, AT91_TCR, mask);
432}
433
434/**
435 * at91_rx_overflow_err - send error frame due to rx overflow
436 * @dev: net device
437 */
438static void at91_rx_overflow_err(struct net_device *dev)
439{
440 struct net_device_stats *stats = &dev->stats;
441 struct sk_buff *skb;
442 struct can_frame *cf;
443
444 dev_dbg(dev->dev.parent, "RX buffer overflow\n");
445 stats->rx_over_errors++;
446 stats->rx_errors++;
447
448 skb = alloc_can_err_skb(dev, &cf);
449 if (unlikely(!skb))
450 return;
451
452 cf->can_id |= CAN_ERR_CRTL;
453 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
454 netif_receive_skb(skb);
455
456 stats->rx_packets++;
457 stats->rx_bytes += cf->can_dlc;
458}
459
460/**
461 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
462 * @dev: net device
463 * @mb: mailbox number to read from
464 * @cf: can frame where to store message
465 *
466 * Reads a CAN message from the given mailbox and stores data into
467 * given can frame. "mb" and "cf" must be valid.
468 */
469static void at91_read_mb(struct net_device *dev, unsigned int mb,
470 struct can_frame *cf)
471{
472 const struct at91_priv *priv = netdev_priv(dev);
473 u32 reg_msr, reg_mid;
474
475 reg_mid = at91_read(priv, AT91_MID(mb));
476 if (reg_mid & AT91_MID_MIDE)
477 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
478 else
479 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
480
481 reg_msr = at91_read(priv, AT91_MSR(mb));
482 if (reg_msr & AT91_MSR_MRTR)
483 cf->can_id |= CAN_RTR_FLAG;
Oliver Hartkoppc7cd6062009-12-12 04:13:21 +0000484 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
David S. Miller99c4a632009-09-25 12:14:43 -0700485
486 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
487 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
488
Marc Kleine-Budde8a0e0a42010-10-21 01:01:14 +0000489 /* allow RX of extended frames */
490 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
491
David S. Miller99c4a632009-09-25 12:14:43 -0700492 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
493 at91_rx_overflow_err(dev);
494}
495
496/**
497 * at91_read_msg - read CAN message from mailbox
498 * @dev: net device
499 * @mb: mail box to read from
500 *
501 * Reads a CAN message from given mailbox, and put into linux network
502 * RX queue, does all housekeeping chores (stats, ...)
503 */
504static void at91_read_msg(struct net_device *dev, unsigned int mb)
505{
506 struct net_device_stats *stats = &dev->stats;
507 struct can_frame *cf;
508 struct sk_buff *skb;
509
510 skb = alloc_can_skb(dev, &cf);
511 if (unlikely(!skb)) {
512 stats->rx_dropped++;
513 return;
514 }
515
516 at91_read_mb(dev, mb, cf);
517 netif_receive_skb(skb);
518
519 stats->rx_packets++;
520 stats->rx_bytes += cf->can_dlc;
521}
522
523/**
524 * at91_poll_rx - read multiple CAN messages from mailboxes
525 * @dev: net device
526 * @quota: max number of pkgs we're allowed to receive
527 *
528 * Theory of Operation:
529 *
530 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
531 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
532 *
533 * Like it or not, but the chip always saves a received CAN message
534 * into the first free mailbox it finds (starting with the
535 * lowest). This makes it very difficult to read the messages in the
536 * right order from the chip. This is how we work around that problem:
537 *
538 * The first message goes into mb nr. 0 and issues an interrupt. All
539 * rx ints are disabled in the interrupt handler and a napi poll is
540 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
541 * receive another message).
542 *
543 * lower mbxs upper
544 * ______^______ __^__
545 * / \ / \
546 * +-+-+-+-+-+-+-+-++-+-+-+-+
547 * |x|x|x|x|x|x|x|x|| | | | |
548 * +-+-+-+-+-+-+-+-++-+-+-+-+
549 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
550 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
551 *
552 * The variable priv->rx_next points to the next mailbox to read a
553 * message from. As long we're in the lower mailboxes we just read the
554 * mailbox but not reenable it.
555 *
556 * With completion of the last of the lower mailboxes, we reenable the
557 * whole first group, but continue to look for filled mailboxes in the
558 * upper mailboxes. Imagine the second group like overflow mailboxes,
559 * which takes CAN messages if the lower goup is full. While in the
560 * upper group we reenable the mailbox right after reading it. Giving
561 * the chip more room to store messages.
562 *
563 * After finishing we look again in the lower group if we've still
564 * quota.
565 *
566 */
567static int at91_poll_rx(struct net_device *dev, int quota)
568{
569 struct at91_priv *priv = netdev_priv(dev);
570 u32 reg_sr = at91_read(priv, AT91_SR);
571 const unsigned long *addr = (unsigned long *)&reg_sr;
572 unsigned int mb;
573 int received = 0;
574
575 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
576 reg_sr & AT91_MB_RX_LOW_MASK)
577 dev_info(dev->dev.parent,
578 "order of incoming frames cannot be guaranteed\n");
579
580 again:
581 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next);
582 mb < AT91_MB_RX_NUM && quota > 0;
583 reg_sr = at91_read(priv, AT91_SR),
584 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) {
585 at91_read_msg(dev, mb);
586
587 /* reactivate mailboxes */
588 if (mb == AT91_MB_RX_LOW_LAST)
589 /* all lower mailboxed, if just finished it */
590 at91_activate_rx_low(priv);
591 else if (mb > AT91_MB_RX_LOW_LAST)
592 /* only the mailbox we read */
593 at91_activate_rx_mb(priv, mb);
594
595 received++;
596 quota--;
597 }
598
599 /* upper group completed, look again in lower */
600 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
601 quota > 0 && mb >= AT91_MB_RX_NUM) {
602 priv->rx_next = 0;
603 goto again;
604 }
605
606 return received;
607}
608
609static void at91_poll_err_frame(struct net_device *dev,
610 struct can_frame *cf, u32 reg_sr)
611{
612 struct at91_priv *priv = netdev_priv(dev);
613
614 /* CRC error */
615 if (reg_sr & AT91_IRQ_CERR) {
616 dev_dbg(dev->dev.parent, "CERR irq\n");
617 dev->stats.rx_errors++;
618 priv->can.can_stats.bus_error++;
619 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
620 }
621
622 /* Stuffing Error */
623 if (reg_sr & AT91_IRQ_SERR) {
624 dev_dbg(dev->dev.parent, "SERR irq\n");
625 dev->stats.rx_errors++;
626 priv->can.can_stats.bus_error++;
627 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
628 cf->data[2] |= CAN_ERR_PROT_STUFF;
629 }
630
631 /* Acknowledgement Error */
632 if (reg_sr & AT91_IRQ_AERR) {
633 dev_dbg(dev->dev.parent, "AERR irq\n");
634 dev->stats.tx_errors++;
635 cf->can_id |= CAN_ERR_ACK;
636 }
637
638 /* Form error */
639 if (reg_sr & AT91_IRQ_FERR) {
640 dev_dbg(dev->dev.parent, "FERR irq\n");
641 dev->stats.rx_errors++;
642 priv->can.can_stats.bus_error++;
643 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
644 cf->data[2] |= CAN_ERR_PROT_FORM;
645 }
646
647 /* Bit Error */
648 if (reg_sr & AT91_IRQ_BERR) {
649 dev_dbg(dev->dev.parent, "BERR irq\n");
650 dev->stats.tx_errors++;
651 priv->can.can_stats.bus_error++;
652 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
653 cf->data[2] |= CAN_ERR_PROT_BIT;
654 }
655}
656
657static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
658{
659 struct sk_buff *skb;
660 struct can_frame *cf;
661
662 if (quota == 0)
663 return 0;
664
665 skb = alloc_can_err_skb(dev, &cf);
666 if (unlikely(!skb))
667 return 0;
668
669 at91_poll_err_frame(dev, cf, reg_sr);
670 netif_receive_skb(skb);
671
David S. Miller99c4a632009-09-25 12:14:43 -0700672 dev->stats.rx_packets++;
673 dev->stats.rx_bytes += cf->can_dlc;
674
675 return 1;
676}
677
678static int at91_poll(struct napi_struct *napi, int quota)
679{
680 struct net_device *dev = napi->dev;
681 const struct at91_priv *priv = netdev_priv(dev);
682 u32 reg_sr = at91_read(priv, AT91_SR);
683 int work_done = 0;
684
685 if (reg_sr & AT91_IRQ_MB_RX)
686 work_done += at91_poll_rx(dev, quota - work_done);
687
688 /*
689 * The error bits are clear on read,
690 * so use saved value from irq handler.
691 */
692 reg_sr |= priv->reg_sr;
693 if (reg_sr & AT91_IRQ_ERR_FRAME)
694 work_done += at91_poll_err(dev, quota - work_done, reg_sr);
695
696 if (work_done < quota) {
697 /* enable IRQs for frame errors and all mailboxes >= rx_next */
698 u32 reg_ier = AT91_IRQ_ERR_FRAME;
699 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
700
701 napi_complete(napi);
702 at91_write(priv, AT91_IER, reg_ier);
703 }
704
705 return work_done;
706}
707
708/*
709 * theory of operation:
710 *
711 * priv->tx_echo holds the number of the oldest can_frame put for
712 * transmission into the hardware, but not yet ACKed by the CAN tx
713 * complete IRQ.
714 *
715 * We iterate from priv->tx_echo to priv->tx_next and check if the
716 * packet has been transmitted, echo it back to the CAN framework. If
717 * we discover a not yet transmitted package, stop looking for more.
718 *
719 */
720static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
721{
722 struct at91_priv *priv = netdev_priv(dev);
723 u32 reg_msr;
724 unsigned int mb;
725
726 /* masking of reg_sr not needed, already done by at91_irq */
727
728 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
729 mb = get_tx_echo_mb(priv);
730
731 /* no event in mailbox? */
732 if (!(reg_sr & (1 << mb)))
733 break;
734
735 /* Disable irq for this TX mailbox */
736 at91_write(priv, AT91_IDR, 1 << mb);
737
738 /*
739 * only echo if mailbox signals us a transfer
740 * complete (MSR_MRDY). Otherwise it's a tansfer
741 * abort. "can_bus_off()" takes care about the skbs
742 * parked in the echo queue.
743 */
744 reg_msr = at91_read(priv, AT91_MSR(mb));
745 if (likely(reg_msr & AT91_MSR_MRDY &&
746 ~reg_msr & AT91_MSR_MABT)) {
747 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
748 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
749 dev->stats.tx_packets++;
750 }
751 }
752
753 /*
754 * restart queue if we don't have a wrap around but restart if
755 * we get a TX int for the last can frame directly before a
756 * wrap around.
757 */
758 if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
759 (priv->tx_echo & AT91_NEXT_MASK) == 0)
760 netif_wake_queue(dev);
761}
762
763static void at91_irq_err_state(struct net_device *dev,
764 struct can_frame *cf, enum can_state new_state)
765{
766 struct at91_priv *priv = netdev_priv(dev);
Marc Kleine-Buddeb61f6742010-10-21 01:01:16 +0000767 u32 reg_idr = 0, reg_ier = 0, reg_ecr;
David S. Miller99c4a632009-09-25 12:14:43 -0700768 u8 tec, rec;
769
770 reg_ecr = at91_read(priv, AT91_ECR);
771 rec = reg_ecr & 0xff;
772 tec = reg_ecr >> 16;
773
774 switch (priv->can.state) {
775 case CAN_STATE_ERROR_ACTIVE:
776 /*
777 * from: ERROR_ACTIVE
778 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
779 * => : there was a warning int
780 */
781 if (new_state >= CAN_STATE_ERROR_WARNING &&
782 new_state <= CAN_STATE_BUS_OFF) {
783 dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
784 priv->can.can_stats.error_warning++;
785
786 cf->can_id |= CAN_ERR_CRTL;
787 cf->data[1] = (tec > rec) ?
788 CAN_ERR_CRTL_TX_WARNING :
789 CAN_ERR_CRTL_RX_WARNING;
790 }
791 case CAN_STATE_ERROR_WARNING: /* fallthrough */
792 /*
793 * from: ERROR_ACTIVE, ERROR_WARNING
794 * to : ERROR_PASSIVE, BUS_OFF
795 * => : error passive int
796 */
797 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
798 new_state <= CAN_STATE_BUS_OFF) {
799 dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
800 priv->can.can_stats.error_passive++;
801
802 cf->can_id |= CAN_ERR_CRTL;
803 cf->data[1] = (tec > rec) ?
804 CAN_ERR_CRTL_TX_PASSIVE :
805 CAN_ERR_CRTL_RX_PASSIVE;
806 }
807 break;
808 case CAN_STATE_BUS_OFF:
809 /*
810 * from: BUS_OFF
811 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
812 */
813 if (new_state <= CAN_STATE_ERROR_PASSIVE) {
814 cf->can_id |= CAN_ERR_RESTARTED;
815
816 dev_dbg(dev->dev.parent, "restarted\n");
817 priv->can.can_stats.restarts++;
818
819 netif_carrier_on(dev);
820 netif_wake_queue(dev);
821 }
822 break;
823 default:
824 break;
825 }
826
827
828 /* process state changes depending on the new state */
829 switch (new_state) {
830 case CAN_STATE_ERROR_ACTIVE:
831 /*
832 * actually we want to enable AT91_IRQ_WARN here, but
833 * it screws up the system under certain
834 * circumstances. so just enable AT91_IRQ_ERRP, thus
835 * the "fallthrough"
836 */
837 dev_dbg(dev->dev.parent, "Error Active\n");
838 cf->can_id |= CAN_ERR_PROT;
839 cf->data[2] = CAN_ERR_PROT_ACTIVE;
840 case CAN_STATE_ERROR_WARNING: /* fallthrough */
841 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
842 reg_ier = AT91_IRQ_ERRP;
843 break;
844 case CAN_STATE_ERROR_PASSIVE:
845 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
846 reg_ier = AT91_IRQ_BOFF;
847 break;
848 case CAN_STATE_BUS_OFF:
849 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
850 AT91_IRQ_WARN | AT91_IRQ_BOFF;
851 reg_ier = 0;
852
853 cf->can_id |= CAN_ERR_BUSOFF;
854
855 dev_dbg(dev->dev.parent, "bus-off\n");
856 netif_carrier_off(dev);
857 priv->can.can_stats.bus_off++;
858
859 /* turn off chip, if restart is disabled */
860 if (!priv->can.restart_ms) {
861 at91_chip_stop(dev, CAN_STATE_BUS_OFF);
862 return;
863 }
864 break;
865 default:
866 break;
867 }
868
869 at91_write(priv, AT91_IDR, reg_idr);
870 at91_write(priv, AT91_IER, reg_ier);
871}
872
873static void at91_irq_err(struct net_device *dev)
874{
875 struct at91_priv *priv = netdev_priv(dev);
876 struct sk_buff *skb;
877 struct can_frame *cf;
878 enum can_state new_state;
879 u32 reg_sr;
880
881 reg_sr = at91_read(priv, AT91_SR);
882
883 /* we need to look at the unmasked reg_sr */
884 if (unlikely(reg_sr & AT91_IRQ_BOFF))
885 new_state = CAN_STATE_BUS_OFF;
886 else if (unlikely(reg_sr & AT91_IRQ_ERRP))
887 new_state = CAN_STATE_ERROR_PASSIVE;
888 else if (unlikely(reg_sr & AT91_IRQ_WARN))
889 new_state = CAN_STATE_ERROR_WARNING;
890 else if (likely(reg_sr & AT91_IRQ_ERRA))
891 new_state = CAN_STATE_ERROR_ACTIVE;
892 else {
893 dev_err(dev->dev.parent, "BUG! hardware in undefined state\n");
894 return;
895 }
896
897 /* state hasn't changed */
898 if (likely(new_state == priv->can.state))
899 return;
900
901 skb = alloc_can_err_skb(dev, &cf);
902 if (unlikely(!skb))
903 return;
904
905 at91_irq_err_state(dev, cf, new_state);
906 netif_rx(skb);
907
David S. Miller99c4a632009-09-25 12:14:43 -0700908 dev->stats.rx_packets++;
909 dev->stats.rx_bytes += cf->can_dlc;
910
911 priv->can.state = new_state;
912}
913
914/*
915 * interrupt handler
916 */
917static irqreturn_t at91_irq(int irq, void *dev_id)
918{
919 struct net_device *dev = dev_id;
920 struct at91_priv *priv = netdev_priv(dev);
921 irqreturn_t handled = IRQ_NONE;
922 u32 reg_sr, reg_imr;
923
924 reg_sr = at91_read(priv, AT91_SR);
925 reg_imr = at91_read(priv, AT91_IMR);
926
927 /* Ignore masked interrupts */
928 reg_sr &= reg_imr;
929 if (!reg_sr)
930 goto exit;
931
932 handled = IRQ_HANDLED;
933
934 /* Receive or error interrupt? -> napi */
935 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
936 /*
937 * The error bits are clear on read,
938 * save for later use.
939 */
940 priv->reg_sr = reg_sr;
941 at91_write(priv, AT91_IDR,
942 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
943 napi_schedule(&priv->napi);
944 }
945
946 /* Transmission complete interrupt */
947 if (reg_sr & AT91_IRQ_MB_TX)
948 at91_irq_tx(dev, reg_sr);
949
950 at91_irq_err(dev);
951
952 exit:
953 return handled;
954}
955
956static int at91_open(struct net_device *dev)
957{
958 struct at91_priv *priv = netdev_priv(dev);
959 int err;
960
961 clk_enable(priv->clk);
962
963 /* check or determine and set bittime */
964 err = open_candev(dev);
965 if (err)
966 goto out;
967
968 /* register interrupt handler */
969 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
970 dev->name, dev)) {
971 err = -EAGAIN;
972 goto out_close;
973 }
974
975 /* start chip and queuing */
976 at91_chip_start(dev);
977 napi_enable(&priv->napi);
978 netif_start_queue(dev);
979
980 return 0;
981
982 out_close:
983 close_candev(dev);
984 out:
985 clk_disable(priv->clk);
986
987 return err;
988}
989
990/*
991 * stop CAN bus activity
992 */
993static int at91_close(struct net_device *dev)
994{
995 struct at91_priv *priv = netdev_priv(dev);
996
997 netif_stop_queue(dev);
998 napi_disable(&priv->napi);
999 at91_chip_stop(dev, CAN_STATE_STOPPED);
1000
1001 free_irq(dev->irq, dev);
1002 clk_disable(priv->clk);
1003
1004 close_candev(dev);
1005
1006 return 0;
1007}
1008
1009static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1010{
1011 switch (mode) {
1012 case CAN_MODE_START:
1013 at91_chip_start(dev);
1014 netif_wake_queue(dev);
1015 break;
1016
1017 default:
1018 return -EOPNOTSUPP;
1019 }
1020
1021 return 0;
1022}
1023
1024static const struct net_device_ops at91_netdev_ops = {
1025 .ndo_open = at91_open,
1026 .ndo_stop = at91_close,
1027 .ndo_start_xmit = at91_start_xmit,
1028};
1029
Marc Kleine-Buddea9d992e2010-10-21 01:01:17 +00001030static int __devinit at91_can_probe(struct platform_device *pdev)
David S. Miller99c4a632009-09-25 12:14:43 -07001031{
1032 struct net_device *dev;
1033 struct at91_priv *priv;
1034 struct resource *res;
1035 struct clk *clk;
1036 void __iomem *addr;
1037 int err, irq;
1038
1039 clk = clk_get(&pdev->dev, "can_clk");
1040 if (IS_ERR(clk)) {
1041 dev_err(&pdev->dev, "no clock defined\n");
1042 err = -ENODEV;
1043 goto exit;
1044 }
1045
1046 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1047 irq = platform_get_irq(pdev, 0);
Uwe Kleine-König4773a472009-12-18 20:31:56 -08001048 if (!res || irq <= 0) {
David S. Miller99c4a632009-09-25 12:14:43 -07001049 err = -ENODEV;
1050 goto exit_put;
1051 }
1052
1053 if (!request_mem_region(res->start,
1054 resource_size(res),
1055 pdev->name)) {
1056 err = -EBUSY;
1057 goto exit_put;
1058 }
1059
1060 addr = ioremap_nocache(res->start, resource_size(res));
1061 if (!addr) {
1062 err = -ENOMEM;
1063 goto exit_release;
1064 }
1065
Wolfgang Grandeggera6e4bc52009-10-08 22:17:11 +00001066 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
David S. Miller99c4a632009-09-25 12:14:43 -07001067 if (!dev) {
1068 err = -ENOMEM;
1069 goto exit_iounmap;
1070 }
1071
1072 dev->netdev_ops = &at91_netdev_ops;
1073 dev->irq = irq;
1074 dev->flags |= IFF_ECHO;
1075
1076 priv = netdev_priv(dev);
1077 priv->can.clock.freq = clk_get_rate(clk);
1078 priv->can.bittiming_const = &at91_bittiming_const;
1079 priv->can.do_set_bittiming = at91_set_bittiming;
1080 priv->can.do_set_mode = at91_set_mode;
Christian Pellegrinad72c342010-01-14 07:08:34 +00001081 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
David S. Miller99c4a632009-09-25 12:14:43 -07001082 priv->reg_base = addr;
1083 priv->dev = dev;
1084 priv->clk = clk;
1085 priv->pdata = pdev->dev.platform_data;
1086
1087 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
1088
1089 dev_set_drvdata(&pdev->dev, dev);
1090 SET_NETDEV_DEV(dev, &pdev->dev);
1091
1092 err = register_candev(dev);
1093 if (err) {
1094 dev_err(&pdev->dev, "registering netdev failed\n");
1095 goto exit_free;
1096 }
1097
1098 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1099 priv->reg_base, dev->irq);
1100
1101 return 0;
1102
1103 exit_free:
Marc Kleine-Budde759a6c72010-10-21 01:01:15 +00001104 free_candev(dev);
David S. Miller99c4a632009-09-25 12:14:43 -07001105 exit_iounmap:
1106 iounmap(addr);
1107 exit_release:
1108 release_mem_region(res->start, resource_size(res));
1109 exit_put:
1110 clk_put(clk);
1111 exit:
1112 return err;
1113}
1114
1115static int __devexit at91_can_remove(struct platform_device *pdev)
1116{
1117 struct net_device *dev = platform_get_drvdata(pdev);
1118 struct at91_priv *priv = netdev_priv(dev);
1119 struct resource *res;
1120
1121 unregister_netdev(dev);
1122
1123 platform_set_drvdata(pdev, NULL);
1124
David S. Miller99c4a632009-09-25 12:14:43 -07001125 iounmap(priv->reg_base);
1126
1127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1128 release_mem_region(res->start, resource_size(res));
1129
1130 clk_put(priv->clk);
1131
Marc Kleine-Budde759a6c72010-10-21 01:01:15 +00001132 free_candev(dev);
1133
David S. Miller99c4a632009-09-25 12:14:43 -07001134 return 0;
1135}
1136
1137static struct platform_driver at91_can_driver = {
1138 .probe = at91_can_probe,
1139 .remove = __devexit_p(at91_can_remove),
1140 .driver = {
1141 .name = DRV_NAME,
1142 .owner = THIS_MODULE,
1143 },
1144};
1145
1146static int __init at91_can_module_init(void)
1147{
1148 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME);
1149 return platform_driver_register(&at91_can_driver);
1150}
1151
1152static void __exit at91_can_module_exit(void)
1153{
1154 platform_driver_unregister(&at91_can_driver);
1155 printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
1156}
1157
1158module_init(at91_can_module_init);
1159module_exit(at91_can_module_exit);
1160
1161MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1162MODULE_LICENSE("GPL v2");
1163MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver");