Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support |
| 3 | * |
| 4 | * Copyright (c) 2014 Guenter Roeck |
| 5 | * |
| 6 | * Derived from mv88e6123_61_65.c |
| 7 | * Copyright (c) 2008-2009 Marvell Semiconductor |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/jiffies.h> |
| 17 | #include <linux/list.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/netdevice.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/phy.h> |
| 22 | #include <net/dsa.h> |
| 23 | #include "mv88e6xxx.h" |
| 24 | |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 25 | static int mv88e6352_wait(struct dsa_switch *ds, int reg, u16 mask) |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 26 | { |
| 27 | unsigned long timeout = jiffies + HZ / 10; |
| 28 | |
| 29 | while (time_before(jiffies, timeout)) { |
| 30 | int ret; |
| 31 | |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 32 | ret = REG_READ(REG_GLOBAL2, reg); |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 33 | if (ret < 0) |
| 34 | return ret; |
| 35 | |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 36 | if (!(ret & mask)) |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 37 | return 0; |
| 38 | |
| 39 | usleep_range(1000, 2000); |
| 40 | } |
| 41 | return -ETIMEDOUT; |
| 42 | } |
| 43 | |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 44 | static inline int mv88e6352_phy_wait(struct dsa_switch *ds) |
| 45 | { |
| 46 | return mv88e6352_wait(ds, 0x18, 0x8000); |
| 47 | } |
| 48 | |
| 49 | static inline int mv88e6352_eeprom_load_wait(struct dsa_switch *ds) |
| 50 | { |
| 51 | return mv88e6352_wait(ds, 0x14, 0x0800); |
| 52 | } |
| 53 | |
| 54 | static inline int mv88e6352_eeprom_busy_wait(struct dsa_switch *ds) |
| 55 | { |
| 56 | return mv88e6352_wait(ds, 0x14, 0x8000); |
| 57 | } |
| 58 | |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 59 | static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum) |
| 60 | { |
| 61 | int ret; |
| 62 | |
| 63 | REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum); |
| 64 | |
| 65 | ret = mv88e6352_phy_wait(ds); |
| 66 | if (ret < 0) |
| 67 | return ret; |
| 68 | |
| 69 | return REG_READ(REG_GLOBAL2, 0x19); |
| 70 | } |
| 71 | |
| 72 | static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum, |
| 73 | u16 val) |
| 74 | { |
| 75 | REG_WRITE(REG_GLOBAL2, 0x19, val); |
| 76 | REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum); |
| 77 | |
| 78 | return mv88e6352_phy_wait(ds); |
| 79 | } |
| 80 | |
| 81 | static char *mv88e6352_probe(struct device *host_dev, int sw_addr) |
| 82 | { |
| 83 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
| 84 | int ret; |
| 85 | |
| 86 | if (bus == NULL) |
| 87 | return NULL; |
| 88 | |
| 89 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
| 90 | if (ret >= 0) { |
Guenter Roeck | 2716777 | 2014-10-29 10:44:57 -0700 | [diff] [blame] | 91 | if ((ret & 0xfff0) == 0x1760) |
| 92 | return "Marvell 88E6176"; |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 93 | if (ret == 0x3521) |
| 94 | return "Marvell 88E6352 (A0)"; |
| 95 | if (ret == 0x3522) |
| 96 | return "Marvell 88E6352 (A1)"; |
| 97 | if ((ret & 0xfff0) == 0x3520) |
| 98 | return "Marvell 88E6352"; |
| 99 | } |
| 100 | |
| 101 | return NULL; |
| 102 | } |
| 103 | |
| 104 | static int mv88e6352_switch_reset(struct dsa_switch *ds) |
| 105 | { |
| 106 | unsigned long timeout; |
| 107 | int ret; |
| 108 | int i; |
| 109 | |
| 110 | /* Set all ports to the disabled state. */ |
| 111 | for (i = 0; i < 7; i++) { |
| 112 | ret = REG_READ(REG_PORT(i), 0x04); |
| 113 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 114 | } |
| 115 | |
| 116 | /* Wait for transmit queues to drain. */ |
| 117 | usleep_range(2000, 4000); |
| 118 | |
| 119 | /* Reset the switch. Keep PPU active (bit 14, undocumented). |
| 120 | * The PPU needs to be active to support indirect phy register |
| 121 | * accesses through global registers 0x18 and 0x19. |
| 122 | */ |
| 123 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); |
| 124 | |
| 125 | /* Wait up to one second for reset to complete. */ |
| 126 | timeout = jiffies + 1 * HZ; |
| 127 | while (time_before(jiffies, timeout)) { |
| 128 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 129 | if ((ret & 0x8800) == 0x8800) |
| 130 | break; |
| 131 | usleep_range(1000, 2000); |
| 132 | } |
| 133 | if (time_after(jiffies, timeout)) |
| 134 | return -ETIMEDOUT; |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | static int mv88e6352_setup_global(struct dsa_switch *ds) |
| 140 | { |
| 141 | int ret; |
| 142 | int i; |
| 143 | |
| 144 | /* Discard packets with excessive collisions, |
| 145 | * mask all interrupt sources, enable PPU (bit 14, undocumented). |
| 146 | */ |
| 147 | REG_WRITE(REG_GLOBAL, 0x04, 0x6000); |
| 148 | |
| 149 | /* Set the default address aging time to 5 minutes, and |
| 150 | * enable address learn messages to be sent to all message |
| 151 | * ports. |
| 152 | */ |
| 153 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); |
| 154 | |
| 155 | /* Configure the priority mapping registers. */ |
| 156 | ret = mv88e6xxx_config_prio(ds); |
| 157 | if (ret < 0) |
| 158 | return ret; |
| 159 | |
| 160 | /* Configure the upstream port, and configure the upstream |
| 161 | * port as the port to which ingress and egress monitor frames |
| 162 | * are to be sent. |
| 163 | */ |
| 164 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); |
| 165 | |
| 166 | /* Disable remote management for now, and set the switch's |
| 167 | * DSA device number. |
| 168 | */ |
| 169 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); |
| 170 | |
| 171 | /* Send all frames with destination addresses matching |
| 172 | * 01:80:c2:00:00:2x to the CPU port. |
| 173 | */ |
| 174 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); |
| 175 | |
| 176 | /* Send all frames with destination addresses matching |
| 177 | * 01:80:c2:00:00:0x to the CPU port. |
| 178 | */ |
| 179 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); |
| 180 | |
| 181 | /* Disable the loopback filter, disable flow control |
| 182 | * messages, disable flood broadcast override, disable |
| 183 | * removing of provider tags, disable ATU age violation |
| 184 | * interrupts, disable tag flow control, force flow |
| 185 | * control priority to the highest, and send all special |
| 186 | * multicast frames to the CPU at the highest priority. |
| 187 | */ |
| 188 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); |
| 189 | |
| 190 | /* Program the DSA routing table. */ |
| 191 | for (i = 0; i < 32; i++) { |
| 192 | int nexthop = 0x1f; |
| 193 | |
| 194 | if (i != ds->index && i < ds->dst->pd->nr_chips) |
| 195 | nexthop = ds->pd->rtable[i] & 0x1f; |
| 196 | |
| 197 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); |
| 198 | } |
| 199 | |
| 200 | /* Clear all trunk masks. */ |
| 201 | for (i = 0; i < 8; i++) |
| 202 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f); |
| 203 | |
| 204 | /* Clear all trunk mappings. */ |
| 205 | for (i = 0; i < 16; i++) |
| 206 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); |
| 207 | |
| 208 | /* Disable ingress rate limiting by resetting all ingress |
| 209 | * rate limit registers to their initial state. |
| 210 | */ |
| 211 | for (i = 0; i < 7; i++) |
| 212 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); |
| 213 | |
| 214 | /* Initialise cross-chip port VLAN table to reset defaults. */ |
| 215 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); |
| 216 | |
| 217 | /* Clear the priority override table. */ |
| 218 | for (i = 0; i < 16; i++) |
| 219 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); |
| 220 | |
| 221 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static int mv88e6352_setup_port(struct dsa_switch *ds, int p) |
| 227 | { |
| 228 | int addr = REG_PORT(p); |
| 229 | u16 val; |
| 230 | |
| 231 | /* MAC Forcing register: don't force link, speed, duplex |
| 232 | * or flow control state to any particular values on physical |
| 233 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s |
| 234 | * full duplex. |
| 235 | */ |
| 236 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) |
| 237 | REG_WRITE(addr, 0x01, 0x003e); |
| 238 | else |
| 239 | REG_WRITE(addr, 0x01, 0x0003); |
| 240 | |
| 241 | /* Do not limit the period of time that this port can be |
| 242 | * paused for by the remote end or the period of time that |
| 243 | * this port can pause the remote end. |
| 244 | */ |
| 245 | REG_WRITE(addr, 0x02, 0x0000); |
| 246 | |
| 247 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
| 248 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
| 249 | * tunneling, determine priority by looking at 802.1p and IP |
| 250 | * priority fields (IP prio has precedence), and set STP state |
| 251 | * to Forwarding. |
| 252 | * |
| 253 | * If this is the CPU link, use DSA or EDSA tagging depending |
| 254 | * on which tagging mode was configured. |
| 255 | * |
| 256 | * If this is a link to another switch, use DSA tagging mode. |
| 257 | * |
| 258 | * If this is the upstream port for this switch, enable |
| 259 | * forwarding of unknown unicasts and multicasts. |
| 260 | */ |
| 261 | val = 0x0433; |
| 262 | if (dsa_is_cpu_port(ds, p)) { |
| 263 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
| 264 | val |= 0x3300; |
| 265 | else |
| 266 | val |= 0x0100; |
| 267 | } |
| 268 | if (ds->dsa_port_mask & (1 << p)) |
| 269 | val |= 0x0100; |
| 270 | if (p == dsa_upstream_port(ds)) |
| 271 | val |= 0x000c; |
| 272 | REG_WRITE(addr, 0x04, val); |
| 273 | |
| 274 | /* Port Control 1: disable trunking. Also, if this is the |
| 275 | * CPU port, enable learn messages to be sent to this port. |
| 276 | */ |
| 277 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); |
| 278 | |
| 279 | /* Port based VLAN map: give each port its own address |
| 280 | * database, allow the CPU port to talk to each of the 'real' |
| 281 | * ports, and allow each of the 'real' ports to only talk to |
| 282 | * the upstream port. |
| 283 | */ |
| 284 | val = (p & 0xf) << 12; |
| 285 | if (dsa_is_cpu_port(ds, p)) |
| 286 | val |= ds->phys_port_mask; |
| 287 | else |
| 288 | val |= 1 << dsa_upstream_port(ds); |
| 289 | REG_WRITE(addr, 0x06, val); |
| 290 | |
| 291 | /* Default VLAN ID and priority: don't set a default VLAN |
| 292 | * ID, and set the default packet priority to zero. |
| 293 | */ |
| 294 | REG_WRITE(addr, 0x07, 0x0000); |
| 295 | |
| 296 | /* Port Control 2: don't force a good FCS, set the maximum |
| 297 | * frame size to 10240 bytes, don't let the switch add or |
| 298 | * strip 802.1q tags, don't discard tagged or untagged frames |
| 299 | * on this port, do a destination address lookup on all |
| 300 | * received packets as usual, disable ARP mirroring and don't |
| 301 | * send a copy of all transmitted/received frames on this port |
| 302 | * to the CPU. |
| 303 | */ |
| 304 | REG_WRITE(addr, 0x08, 0x2080); |
| 305 | |
| 306 | /* Egress rate control: disable egress rate control. */ |
| 307 | REG_WRITE(addr, 0x09, 0x0001); |
| 308 | |
| 309 | /* Egress rate control 2: disable egress rate control. */ |
| 310 | REG_WRITE(addr, 0x0a, 0x0000); |
| 311 | |
| 312 | /* Port Association Vector: when learning source addresses |
| 313 | * of packets, add the address to the address database using |
| 314 | * a port bitmap that has only the bit for this port set and |
| 315 | * the other bits clear. |
| 316 | */ |
| 317 | REG_WRITE(addr, 0x0b, 1 << p); |
| 318 | |
| 319 | /* Port ATU control: disable limiting the number of address |
| 320 | * database entries that this port is allowed to use. |
| 321 | */ |
| 322 | REG_WRITE(addr, 0x0c, 0x0000); |
| 323 | |
| 324 | /* Priority Override: disable DA, SA and VTU priority override. */ |
| 325 | REG_WRITE(addr, 0x0d, 0x0000); |
| 326 | |
| 327 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ |
| 328 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); |
| 329 | |
| 330 | /* Tag Remap: use an identity 802.1p prio -> switch prio |
| 331 | * mapping. |
| 332 | */ |
| 333 | REG_WRITE(addr, 0x18, 0x3210); |
| 334 | |
| 335 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio |
| 336 | * mapping. |
| 337 | */ |
| 338 | REG_WRITE(addr, 0x19, 0x7654); |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
Guenter Roeck | 276db3b | 2014-10-29 10:44:59 -0700 | [diff] [blame] | 343 | #ifdef CONFIG_NET_DSA_HWMON |
| 344 | |
| 345 | static int mv88e6352_phy_page_read(struct dsa_switch *ds, |
| 346 | int port, int page, int reg) |
| 347 | { |
| 348 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 349 | int ret; |
| 350 | |
| 351 | mutex_lock(&ps->phy_mutex); |
| 352 | ret = __mv88e6352_phy_write(ds, port, 0x16, page); |
| 353 | if (ret < 0) |
| 354 | goto error; |
| 355 | ret = __mv88e6352_phy_read(ds, port, reg); |
| 356 | error: |
| 357 | __mv88e6352_phy_write(ds, port, 0x16, 0x0); |
| 358 | mutex_unlock(&ps->phy_mutex); |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | static int mv88e6352_phy_page_write(struct dsa_switch *ds, |
| 363 | int port, int page, int reg, int val) |
| 364 | { |
| 365 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 366 | int ret; |
| 367 | |
| 368 | mutex_lock(&ps->phy_mutex); |
| 369 | ret = __mv88e6352_phy_write(ds, port, 0x16, page); |
| 370 | if (ret < 0) |
| 371 | goto error; |
| 372 | |
| 373 | ret = __mv88e6352_phy_write(ds, port, reg, val); |
| 374 | error: |
| 375 | __mv88e6352_phy_write(ds, port, 0x16, 0x0); |
| 376 | mutex_unlock(&ps->phy_mutex); |
| 377 | return ret; |
| 378 | } |
| 379 | |
| 380 | static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp) |
| 381 | { |
| 382 | int ret; |
| 383 | |
| 384 | *temp = 0; |
| 385 | |
| 386 | ret = mv88e6352_phy_page_read(ds, 0, 6, 27); |
| 387 | if (ret < 0) |
| 388 | return ret; |
| 389 | |
| 390 | *temp = (ret & 0xff) - 25; |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp) |
| 396 | { |
| 397 | int ret; |
| 398 | |
| 399 | *temp = 0; |
| 400 | |
| 401 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); |
| 402 | if (ret < 0) |
| 403 | return ret; |
| 404 | |
| 405 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp) |
| 411 | { |
| 412 | int ret; |
| 413 | |
| 414 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); |
| 415 | if (ret < 0) |
| 416 | return ret; |
| 417 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
| 418 | return mv88e6352_phy_page_write(ds, 0, 6, 26, |
| 419 | (ret & 0xe0ff) | (temp << 8)); |
| 420 | } |
| 421 | |
| 422 | static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
| 423 | { |
| 424 | int ret; |
| 425 | |
| 426 | *alarm = false; |
| 427 | |
| 428 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); |
| 429 | if (ret < 0) |
| 430 | return ret; |
| 431 | |
| 432 | *alarm = !!(ret & 0x40); |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | #endif /* CONFIG_NET_DSA_HWMON */ |
| 437 | |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 438 | static int mv88e6352_setup(struct dsa_switch *ds) |
| 439 | { |
| 440 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 441 | int ret; |
| 442 | int i; |
| 443 | |
| 444 | mutex_init(&ps->smi_mutex); |
| 445 | mutex_init(&ps->stats_mutex); |
| 446 | mutex_init(&ps->phy_mutex); |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 447 | mutex_init(&ps->eeprom_mutex); |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 448 | |
| 449 | ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0; |
| 450 | |
| 451 | ret = mv88e6352_switch_reset(ds); |
| 452 | if (ret < 0) |
| 453 | return ret; |
| 454 | |
| 455 | /* @@@ initialise vtu and atu */ |
| 456 | |
| 457 | ret = mv88e6352_setup_global(ds); |
| 458 | if (ret < 0) |
| 459 | return ret; |
| 460 | |
| 461 | for (i = 0; i < 7; i++) { |
| 462 | ret = mv88e6352_setup_port(ds, i); |
| 463 | if (ret < 0) |
| 464 | return ret; |
| 465 | } |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | static int mv88e6352_port_to_phy_addr(int port) |
| 471 | { |
| 472 | if (port >= 0 && port <= 4) |
| 473 | return port; |
| 474 | return -EINVAL; |
| 475 | } |
| 476 | |
| 477 | static int |
| 478 | mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum) |
| 479 | { |
| 480 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 481 | int addr = mv88e6352_port_to_phy_addr(port); |
| 482 | int ret; |
| 483 | |
| 484 | if (addr < 0) |
| 485 | return addr; |
| 486 | |
| 487 | mutex_lock(&ps->phy_mutex); |
| 488 | ret = __mv88e6352_phy_read(ds, addr, regnum); |
| 489 | mutex_unlock(&ps->phy_mutex); |
| 490 | |
| 491 | return ret; |
| 492 | } |
| 493 | |
| 494 | static int |
| 495 | mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) |
| 496 | { |
| 497 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 498 | int addr = mv88e6352_port_to_phy_addr(port); |
| 499 | int ret; |
| 500 | |
| 501 | if (addr < 0) |
| 502 | return addr; |
| 503 | |
| 504 | mutex_lock(&ps->phy_mutex); |
| 505 | ret = __mv88e6352_phy_write(ds, addr, regnum, val); |
| 506 | mutex_unlock(&ps->phy_mutex); |
| 507 | |
| 508 | return ret; |
| 509 | } |
| 510 | |
| 511 | static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = { |
| 512 | { "in_good_octets", 8, 0x00, }, |
| 513 | { "in_bad_octets", 4, 0x02, }, |
| 514 | { "in_unicast", 4, 0x04, }, |
| 515 | { "in_broadcasts", 4, 0x06, }, |
| 516 | { "in_multicasts", 4, 0x07, }, |
| 517 | { "in_pause", 4, 0x16, }, |
| 518 | { "in_undersize", 4, 0x18, }, |
| 519 | { "in_fragments", 4, 0x19, }, |
| 520 | { "in_oversize", 4, 0x1a, }, |
| 521 | { "in_jabber", 4, 0x1b, }, |
| 522 | { "in_rx_error", 4, 0x1c, }, |
| 523 | { "in_fcs_error", 4, 0x1d, }, |
| 524 | { "out_octets", 8, 0x0e, }, |
| 525 | { "out_unicast", 4, 0x10, }, |
| 526 | { "out_broadcasts", 4, 0x13, }, |
| 527 | { "out_multicasts", 4, 0x12, }, |
| 528 | { "out_pause", 4, 0x15, }, |
| 529 | { "excessive", 4, 0x11, }, |
| 530 | { "collisions", 4, 0x1e, }, |
| 531 | { "deferred", 4, 0x05, }, |
| 532 | { "single", 4, 0x14, }, |
| 533 | { "multiple", 4, 0x17, }, |
| 534 | { "out_fcs_error", 4, 0x03, }, |
| 535 | { "late", 4, 0x1f, }, |
| 536 | { "hist_64bytes", 4, 0x08, }, |
| 537 | { "hist_65_127bytes", 4, 0x09, }, |
| 538 | { "hist_128_255bytes", 4, 0x0a, }, |
| 539 | { "hist_256_511bytes", 4, 0x0b, }, |
| 540 | { "hist_512_1023bytes", 4, 0x0c, }, |
| 541 | { "hist_1024_max_bytes", 4, 0x0d, }, |
| 542 | }; |
| 543 | |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 544 | static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr) |
| 545 | { |
| 546 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 547 | int ret; |
| 548 | |
| 549 | mutex_lock(&ps->eeprom_mutex); |
| 550 | |
| 551 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, |
| 552 | 0xc000 | (addr & 0xff)); |
| 553 | if (ret < 0) |
| 554 | goto error; |
| 555 | |
| 556 | ret = mv88e6352_eeprom_busy_wait(ds); |
| 557 | if (ret < 0) |
| 558 | goto error; |
| 559 | |
| 560 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15); |
| 561 | error: |
| 562 | mutex_unlock(&ps->eeprom_mutex); |
| 563 | return ret; |
| 564 | } |
| 565 | |
| 566 | static int mv88e6352_get_eeprom(struct dsa_switch *ds, |
| 567 | struct ethtool_eeprom *eeprom, u8 *data) |
| 568 | { |
| 569 | int offset; |
| 570 | int len; |
| 571 | int ret; |
| 572 | |
| 573 | offset = eeprom->offset; |
| 574 | len = eeprom->len; |
| 575 | eeprom->len = 0; |
| 576 | |
| 577 | eeprom->magic = 0xc3ec4951; |
| 578 | |
| 579 | ret = mv88e6352_eeprom_load_wait(ds); |
| 580 | if (ret < 0) |
| 581 | return ret; |
| 582 | |
| 583 | if (offset & 1) { |
| 584 | int word; |
| 585 | |
| 586 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); |
| 587 | if (word < 0) |
| 588 | return word; |
| 589 | |
| 590 | *data++ = (word >> 8) & 0xff; |
| 591 | |
| 592 | offset++; |
| 593 | len--; |
| 594 | eeprom->len++; |
| 595 | } |
| 596 | |
| 597 | while (len >= 2) { |
| 598 | int word; |
| 599 | |
| 600 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); |
| 601 | if (word < 0) |
| 602 | return word; |
| 603 | |
| 604 | *data++ = word & 0xff; |
| 605 | *data++ = (word >> 8) & 0xff; |
| 606 | |
| 607 | offset += 2; |
| 608 | len -= 2; |
| 609 | eeprom->len += 2; |
| 610 | } |
| 611 | |
| 612 | if (len) { |
| 613 | int word; |
| 614 | |
| 615 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); |
| 616 | if (word < 0) |
| 617 | return word; |
| 618 | |
| 619 | *data++ = word & 0xff; |
| 620 | |
| 621 | offset++; |
| 622 | len--; |
| 623 | eeprom->len++; |
| 624 | } |
| 625 | |
| 626 | return 0; |
| 627 | } |
| 628 | |
| 629 | static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds) |
| 630 | { |
| 631 | int ret; |
| 632 | |
| 633 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14); |
| 634 | if (ret < 0) |
| 635 | return ret; |
| 636 | |
| 637 | if (!(ret & 0x0400)) |
| 638 | return -EROFS; |
| 639 | |
| 640 | return 0; |
| 641 | } |
| 642 | |
| 643 | static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr, |
| 644 | u16 data) |
| 645 | { |
| 646 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 647 | int ret; |
| 648 | |
| 649 | mutex_lock(&ps->eeprom_mutex); |
| 650 | |
| 651 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data); |
| 652 | if (ret < 0) |
| 653 | goto error; |
| 654 | |
| 655 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, |
| 656 | 0xb000 | (addr & 0xff)); |
| 657 | if (ret < 0) |
| 658 | goto error; |
| 659 | |
| 660 | ret = mv88e6352_eeprom_busy_wait(ds); |
| 661 | error: |
| 662 | mutex_unlock(&ps->eeprom_mutex); |
| 663 | return ret; |
| 664 | } |
| 665 | |
| 666 | static int mv88e6352_set_eeprom(struct dsa_switch *ds, |
| 667 | struct ethtool_eeprom *eeprom, u8 *data) |
| 668 | { |
| 669 | int offset; |
| 670 | int ret; |
| 671 | int len; |
| 672 | |
| 673 | if (eeprom->magic != 0xc3ec4951) |
| 674 | return -EINVAL; |
| 675 | |
| 676 | ret = mv88e6352_eeprom_is_readonly(ds); |
| 677 | if (ret) |
| 678 | return ret; |
| 679 | |
| 680 | offset = eeprom->offset; |
| 681 | len = eeprom->len; |
| 682 | eeprom->len = 0; |
| 683 | |
| 684 | ret = mv88e6352_eeprom_load_wait(ds); |
| 685 | if (ret < 0) |
| 686 | return ret; |
| 687 | |
| 688 | if (offset & 1) { |
| 689 | int word; |
| 690 | |
| 691 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); |
| 692 | if (word < 0) |
| 693 | return word; |
| 694 | |
| 695 | word = (*data++ << 8) | (word & 0xff); |
| 696 | |
| 697 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); |
| 698 | if (ret < 0) |
| 699 | return ret; |
| 700 | |
| 701 | offset++; |
| 702 | len--; |
| 703 | eeprom->len++; |
| 704 | } |
| 705 | |
| 706 | while (len >= 2) { |
| 707 | int word; |
| 708 | |
| 709 | word = *data++; |
| 710 | word |= *data++ << 8; |
| 711 | |
| 712 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); |
| 713 | if (ret < 0) |
| 714 | return ret; |
| 715 | |
| 716 | offset += 2; |
| 717 | len -= 2; |
| 718 | eeprom->len += 2; |
| 719 | } |
| 720 | |
| 721 | if (len) { |
| 722 | int word; |
| 723 | |
| 724 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); |
| 725 | if (word < 0) |
| 726 | return word; |
| 727 | |
| 728 | word = (word & 0xff00) | *data++; |
| 729 | |
| 730 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); |
| 731 | if (ret < 0) |
| 732 | return ret; |
| 733 | |
| 734 | offset++; |
| 735 | len--; |
| 736 | eeprom->len++; |
| 737 | } |
| 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 742 | static void |
| 743 | mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data) |
| 744 | { |
| 745 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats), |
| 746 | mv88e6352_hw_stats, port, data); |
| 747 | } |
| 748 | |
| 749 | static void |
| 750 | mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) |
| 751 | { |
| 752 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats), |
| 753 | mv88e6352_hw_stats, port, data); |
| 754 | } |
| 755 | |
| 756 | static int mv88e6352_get_sset_count(struct dsa_switch *ds) |
| 757 | { |
| 758 | return ARRAY_SIZE(mv88e6352_hw_stats); |
| 759 | } |
| 760 | |
| 761 | struct dsa_switch_driver mv88e6352_switch_driver = { |
| 762 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
| 763 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
| 764 | .probe = mv88e6352_probe, |
| 765 | .setup = mv88e6352_setup, |
| 766 | .set_addr = mv88e6xxx_set_addr_indirect, |
| 767 | .phy_read = mv88e6352_phy_read, |
| 768 | .phy_write = mv88e6352_phy_write, |
| 769 | .poll_link = mv88e6xxx_poll_link, |
| 770 | .get_strings = mv88e6352_get_strings, |
| 771 | .get_ethtool_stats = mv88e6352_get_ethtool_stats, |
| 772 | .get_sset_count = mv88e6352_get_sset_count, |
Guenter Roeck | 276db3b | 2014-10-29 10:44:59 -0700 | [diff] [blame] | 773 | #ifdef CONFIG_NET_DSA_HWMON |
| 774 | .get_temp = mv88e6352_get_temp, |
| 775 | .get_temp_limit = mv88e6352_get_temp_limit, |
| 776 | .set_temp_limit = mv88e6352_set_temp_limit, |
| 777 | .get_temp_alarm = mv88e6352_get_temp_alarm, |
| 778 | #endif |
Guenter Roeck | 33b43df | 2014-10-29 10:45:03 -0700 | [diff] [blame^] | 779 | .get_eeprom = mv88e6352_get_eeprom, |
| 780 | .set_eeprom = mv88e6352_set_eeprom, |
Guenter Roeck | 3ad50cc | 2014-10-29 10:44:56 -0700 | [diff] [blame] | 781 | }; |
| 782 | |
| 783 | MODULE_ALIAS("platform:mv88e6352"); |