Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/memory.c |
| 3 | * |
| 4 | * Memory timing related functions for OMAP24XX |
| 5 | * |
| 6 | * Copyright (C) 2005 Texas Instruments Inc. |
| 7 | * Richard Woodruff <r-woodruff2@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2005 Nokia Corporation |
| 10 | * Tony Lindgren <tony@atomide.com> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 17 | #include <linux/module.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/list.h> |
| 21 | #include <linux/errno.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/clk.h> |
| 24 | |
| 25 | #include <asm/io.h> |
| 26 | |
| 27 | #include <asm/arch/clock.h> |
| 28 | #include <asm/arch/sram.h> |
| 29 | |
| 30 | #include "prcm-regs.h" |
| 31 | #include "memory.h" |
| 32 | |
Juha Yrjola | 33c9907 | 2006-12-06 17:13:46 -0800 | [diff] [blame^] | 33 | #define SMS_BASE 0x68008000 |
| 34 | #define SMS_SYSCONFIG 0x010 |
| 35 | |
| 36 | #define SDRC_BASE 0x68009000 |
| 37 | #define SDRC_SYSCONFIG 0x010 |
| 38 | #define SDRC_SYSSTATUS 0x014 |
| 39 | |
| 40 | static const u32 sms_base = IO_ADDRESS(SMS_BASE); |
| 41 | static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE); |
| 42 | |
| 43 | |
| 44 | static inline void sms_write_reg(int idx, u32 val) |
| 45 | { |
| 46 | __raw_writel(val, sms_base + idx); |
| 47 | } |
| 48 | |
| 49 | static inline u32 sms_read_reg(int idx) |
| 50 | { |
| 51 | return __raw_readl(sms_base + idx); |
| 52 | } |
| 53 | |
| 54 | static inline void sdrc_write_reg(int idx, u32 val) |
| 55 | { |
| 56 | __raw_writel(val, sdrc_base + idx); |
| 57 | } |
| 58 | |
| 59 | static inline u32 sdrc_read_reg(int idx) |
| 60 | { |
| 61 | return __raw_readl(sdrc_base + idx); |
| 62 | } |
| 63 | |
| 64 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 65 | static struct memory_timings mem_timings; |
| 66 | |
| 67 | u32 omap2_memory_get_slow_dll_ctrl(void) |
| 68 | { |
| 69 | return mem_timings.slow_dll_ctrl; |
| 70 | } |
| 71 | |
| 72 | u32 omap2_memory_get_fast_dll_ctrl(void) |
| 73 | { |
| 74 | return mem_timings.fast_dll_ctrl; |
| 75 | } |
| 76 | |
| 77 | u32 omap2_memory_get_type(void) |
| 78 | { |
| 79 | return mem_timings.m_type; |
| 80 | } |
| 81 | |
| 82 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) |
| 83 | { |
| 84 | unsigned long dll_cnt; |
| 85 | u32 fast_dll = 0; |
| 86 | |
| 87 | mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ |
| 88 | |
| 89 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. |
| 90 | * In the case of 2422, its ok to use CS1 instead of CS0. |
| 91 | */ |
| 92 | if (cpu_is_omap2422()) |
| 93 | mem_timings.base_cs = 1; |
| 94 | else |
| 95 | mem_timings.base_cs = 0; |
| 96 | |
| 97 | if (mem_timings.m_type != M_DDR) |
| 98 | return; |
| 99 | |
| 100 | /* With DDR we need to determine the low frequency DLL value */ |
| 101 | if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) |
| 102 | mem_timings.dll_mode = M_UNLOCK; |
| 103 | else |
| 104 | mem_timings.dll_mode = M_LOCK; |
| 105 | |
| 106 | if (mem_timings.base_cs == 0) { |
| 107 | fast_dll = SDRC_DLLA_CTRL; |
| 108 | dll_cnt = SDRC_DLLA_STATUS & 0xff00; |
| 109 | } else { |
| 110 | fast_dll = SDRC_DLLB_CTRL; |
| 111 | dll_cnt = SDRC_DLLB_STATUS & 0xff00; |
| 112 | } |
| 113 | if (force_lock_to_unlock_mode) { |
| 114 | fast_dll &= ~0xff00; |
| 115 | fast_dll |= dll_cnt; /* Current lock mode */ |
| 116 | } |
| 117 | /* set fast timings with DLL filter disabled */ |
| 118 | mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); |
| 119 | |
| 120 | /* No disruptions, DDR will be offline & C-ABI not followed */ |
| 121 | omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, |
| 122 | mem_timings.fast_dll_ctrl, |
| 123 | mem_timings.base_cs, |
| 124 | force_lock_to_unlock_mode); |
| 125 | mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ |
| 126 | |
| 127 | /* Turn status into unlock ctrl */ |
| 128 | mem_timings.slow_dll_ctrl |= |
| 129 | ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); |
| 130 | |
| 131 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ |
| 132 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
| 133 | } |
Juha Yrjola | 33c9907 | 2006-12-06 17:13:46 -0800 | [diff] [blame^] | 134 | |
| 135 | void __init omap2_init_memory(void) |
| 136 | { |
| 137 | u32 l; |
| 138 | |
| 139 | l = sms_read_reg(SMS_SYSCONFIG); |
| 140 | l &= ~(0x3 << 3); |
| 141 | l |= (0x2 << 3); |
| 142 | sms_write_reg(SMS_SYSCONFIG, l); |
| 143 | |
| 144 | l = sdrc_read_reg(SDRC_SYSCONFIG); |
| 145 | l &= ~(0x3 << 3); |
| 146 | l |= (0x2 << 3); |
| 147 | sdrc_write_reg(SDRC_SYSCONFIG, l); |
| 148 | |
| 149 | } |