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Wu Zhangjin363c55c2009-06-04 20:27:10 +08001/*
2 * Hibernation support specific for mips - temporary page tables
3 *
4 * Licensed under the GPLv2
5 *
Wu Zhangjinf7a904d2010-01-04 17:16:51 +08006 * Copyright (C) 2009 Lemote Inc.
Wu Zhangjin363c55c2009-06-04 20:27:10 +08007 * Author: Hu Hongbing <huhb@lemote.com>
Ralf Baechle70342282013-01-22 12:59:30 +01008 * Wu Zhangjin <wuzhangjin@gmail.com>
Wu Zhangjin363c55c2009-06-04 20:27:10 +08009 */
10#include <asm/asm-offsets.h>
11#include <asm/regdef.h>
12#include <asm/asm.h>
13
14.text
15LEAF(swsusp_arch_suspend)
16 PTR_LA t0, saved_regs
17 PTR_S ra, PT_R31(t0)
18 PTR_S sp, PT_R29(t0)
19 PTR_S fp, PT_R30(t0)
20 PTR_S gp, PT_R28(t0)
21 PTR_S s0, PT_R16(t0)
22 PTR_S s1, PT_R17(t0)
23 PTR_S s2, PT_R18(t0)
24 PTR_S s3, PT_R19(t0)
25 PTR_S s4, PT_R20(t0)
26 PTR_S s5, PT_R21(t0)
27 PTR_S s6, PT_R22(t0)
28 PTR_S s7, PT_R23(t0)
29 j swsusp_save
30END(swsusp_arch_suspend)
31
32LEAF(swsusp_arch_resume)
33 PTR_L t0, restore_pblist
340:
35 PTR_L t1, PBE_ADDRESS(t0) /* source */
36 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
Ralf Baechlebef9ae32012-12-28 15:15:25 +010037 PTR_ADDU t3, t1, _PAGE_SIZE
Wu Zhangjin363c55c2009-06-04 20:27:10 +0800381:
39 REG_L t8, (t1)
40 REG_S t8, (t2)
41 PTR_ADDIU t1, t1, SZREG
42 PTR_ADDIU t2, t2, SZREG
43 bne t1, t3, 1b
44 PTR_L t0, PBE_NEXT(t0)
45 bnez t0, 0b
Huacai Chenc14af232014-03-22 17:21:44 +080046 jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
Wu Zhangjin363c55c2009-06-04 20:27:10 +080047 PTR_LA t0, saved_regs
48 PTR_L ra, PT_R31(t0)
49 PTR_L sp, PT_R29(t0)
50 PTR_L fp, PT_R30(t0)
51 PTR_L gp, PT_R28(t0)
52 PTR_L s0, PT_R16(t0)
53 PTR_L s1, PT_R17(t0)
54 PTR_L s2, PT_R18(t0)
55 PTR_L s3, PT_R19(t0)
56 PTR_L s4, PT_R20(t0)
57 PTR_L s5, PT_R21(t0)
58 PTR_L s6, PT_R22(t0)
59 PTR_L s7, PT_R23(t0)
60 PTR_LI v0, 0x0
61 jr ra
62END(swsusp_arch_resume)