blob: 41b425602d8832ac0d71ea7a26abeef726ebac50 [file] [log] [blame]
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +09001/* linux/arch/arm/mach-s3c64xx/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S3C64XX setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <mach/map.h>
18#include <mach/regs-clock.h>
19#include <plat/gpio-cfg.h>
Mark Brown6b2cff92010-10-13 18:23:42 +090020#include <plat/ata.h>
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090021
22void s3c64xx_ide_setup_gpio(void)
23{
24 u32 reg;
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090025
26 reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
27
28 /* Independent CF interface, CF chip select configuration */
29 writel(reg | MEM_SYS_CFG_INDEP_CF |
30 MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
31
32 s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
33
34 /* Set XhiDATA[15:0] pins as CF Data[15:0] */
Kukjin Kimaef698a2010-10-01 20:47:21 +090035 s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090036
37 /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
Kukjin Kimaef698a2010-10-01 20:47:21 +090038 s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090039
40 /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
41 s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
Kukjin Kimaef698a2010-10-01 20:47:21 +090042 s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090043}