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Ben Dooks3501c9a2010-01-26 10:45:40 +09001/* linux/arch/arm/plat-s3c64xx/sleep.S
Ben Dooksbd117bd2009-03-10 18:19:35 +00002 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU sleep code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/linkage.h>
16#include <asm/assembler.h>
17#include <mach/map.h>
18
19#undef S3C64XX_VA_GPIO
20#define S3C64XX_VA_GPIO (0x0)
21
Ben Dooks3501c9a2010-01-26 10:45:40 +090022#include <mach/regs-gpio.h>
Ben Dooksbd117bd2009-03-10 18:19:35 +000023
24#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
25
26 .text
27
Ben Dooksbd117bd2009-03-10 18:19:35 +000028 /* Sleep magic, the word before the resume entry point so that the
29 * bootloader can check for a resumeable image. */
30
31 .word 0x2bedf00d
32
33 /* s3c_cpu_reusme
34 *
35 * This is the entry point, stored by whatever method the bootloader
36 * requires to get the kernel runnign again. This code expects to be
37 * entered with no caches live and the MMU disabled. It will then
38 * restore the MMU and other basic CP registers saved and restart
39 * the kernel C code to finish the resume code.
40 */
41
42ENTRY(s3c_cpu_resume)
43 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
44 ldr r2, =LL_UART /* for debug */
45
46#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
Joonyoung Shim31858472011-05-06 09:37:17 +090047
48#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
49#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
50
51#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
52#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
53
Ben Dooksbd117bd2009-03-10 18:19:35 +000054 /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
55 * as the uboot version supplied resets these to inputs during the
56 * resume checks.
57 */
58
59 ldr r3, =S3C64XX_PA_GPIO
60 ldr r0, [ r3, #S3C64XX_GPNCON ]
61 bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
62 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
63 orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
64 S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
65 str r0, [ r3, #S3C64XX_GPNCON ]
66
67 ldr r0, [ r3, #S3C64XX_GPNDAT ]
68 bic r0, r0, #0xf << 12 @ GPN12..15
69 orr r0, r0, #1 << 15 @ GPN15
70 str r0, [ r3, #S3C64XX_GPNDAT ]
71#endif
Russell King2e2f3d32011-02-06 17:39:31 +000072 b cpu_resume