Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include "drmP.h" |
| 25 | #include "radeon.h" |
| 26 | #include "sumod.h" |
| 27 | #include "r600_dpm.h" |
| 28 | #include "cypress_dpm.h" |
| 29 | #include "sumo_dpm.h" |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 30 | |
| 31 | #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 |
| 32 | #define SUMO_MINIMUM_ENGINE_CLOCK 800 |
| 33 | #define BOOST_DPM_LEVEL 7 |
| 34 | |
| 35 | static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = |
| 36 | { |
| 37 | SUMO_UTC_DFLT_00, |
| 38 | SUMO_UTC_DFLT_01, |
| 39 | SUMO_UTC_DFLT_02, |
| 40 | SUMO_UTC_DFLT_03, |
| 41 | SUMO_UTC_DFLT_04, |
| 42 | SUMO_UTC_DFLT_05, |
| 43 | SUMO_UTC_DFLT_06, |
| 44 | SUMO_UTC_DFLT_07, |
| 45 | SUMO_UTC_DFLT_08, |
| 46 | SUMO_UTC_DFLT_09, |
| 47 | SUMO_UTC_DFLT_10, |
| 48 | SUMO_UTC_DFLT_11, |
| 49 | SUMO_UTC_DFLT_12, |
| 50 | SUMO_UTC_DFLT_13, |
| 51 | SUMO_UTC_DFLT_14, |
| 52 | }; |
| 53 | |
| 54 | static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = |
| 55 | { |
| 56 | SUMO_DTC_DFLT_00, |
| 57 | SUMO_DTC_DFLT_01, |
| 58 | SUMO_DTC_DFLT_02, |
| 59 | SUMO_DTC_DFLT_03, |
| 60 | SUMO_DTC_DFLT_04, |
| 61 | SUMO_DTC_DFLT_05, |
| 62 | SUMO_DTC_DFLT_06, |
| 63 | SUMO_DTC_DFLT_07, |
| 64 | SUMO_DTC_DFLT_08, |
| 65 | SUMO_DTC_DFLT_09, |
| 66 | SUMO_DTC_DFLT_10, |
| 67 | SUMO_DTC_DFLT_11, |
| 68 | SUMO_DTC_DFLT_12, |
| 69 | SUMO_DTC_DFLT_13, |
| 70 | SUMO_DTC_DFLT_14, |
| 71 | }; |
| 72 | |
| 73 | struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) |
| 74 | { |
| 75 | struct sumo_ps *ps = rps->ps_priv; |
| 76 | |
| 77 | return ps; |
| 78 | } |
| 79 | |
| 80 | struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) |
| 81 | { |
| 82 | struct sumo_power_info *pi = rdev->pm.dpm.priv; |
| 83 | |
| 84 | return pi; |
| 85 | } |
| 86 | |
| 87 | u32 sumo_get_xclk(struct radeon_device *rdev) |
| 88 | { |
| 89 | return rdev->clock.spll.reference_freq; |
| 90 | } |
| 91 | |
| 92 | static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) |
| 93 | { |
| 94 | if (enable) |
| 95 | WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); |
| 96 | else { |
| 97 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); |
| 98 | WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); |
| 99 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); |
| 100 | RREG32(GB_ADDR_CONFIG); |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF |
| 105 | #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF |
| 106 | |
| 107 | static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) |
| 108 | { |
| 109 | u32 local0; |
| 110 | u32 local1; |
| 111 | |
| 112 | local0 = RREG32(CG_CGTT_LOCAL_0); |
| 113 | local1 = RREG32(CG_CGTT_LOCAL_1); |
| 114 | |
| 115 | if (enable) { |
| 116 | WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); |
| 117 | WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); |
| 118 | } else { |
| 119 | WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); |
| 120 | WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static void sumo_program_git(struct radeon_device *rdev) |
| 125 | { |
| 126 | u32 p, u; |
| 127 | u32 xclk = sumo_get_xclk(rdev); |
| 128 | |
| 129 | r600_calculate_u_and_p(SUMO_GICST_DFLT, |
| 130 | xclk, 16, &p, &u); |
| 131 | |
| 132 | WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); |
| 133 | } |
| 134 | |
| 135 | static void sumo_program_grsd(struct radeon_device *rdev) |
| 136 | { |
| 137 | u32 p, u; |
| 138 | u32 xclk = sumo_get_xclk(rdev); |
| 139 | u32 grs = 256 * 25 / 100; |
| 140 | |
| 141 | r600_calculate_u_and_p(1, xclk, 14, &p, &u); |
| 142 | |
| 143 | WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); |
| 144 | } |
| 145 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 146 | void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 147 | { |
| 148 | sumo_program_git(rdev); |
| 149 | sumo_program_grsd(rdev); |
| 150 | } |
| 151 | |
| 152 | static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) |
| 153 | { |
| 154 | u32 rcu_pwr_gating_cntl; |
| 155 | u32 p, u; |
| 156 | u32 p_c, p_p, d_p; |
| 157 | u32 r_t, i_t; |
| 158 | u32 xclk = sumo_get_xclk(rdev); |
| 159 | |
| 160 | if (rdev->family == CHIP_PALM) { |
| 161 | p_c = 4; |
| 162 | d_p = 10; |
| 163 | r_t = 10; |
| 164 | i_t = 4; |
| 165 | p_p = 50 + 1000/200 + 6 * 32; |
| 166 | } else { |
| 167 | p_c = 16; |
| 168 | d_p = 50; |
| 169 | r_t = 50; |
| 170 | i_t = 50; |
| 171 | p_p = 113; |
| 172 | } |
| 173 | |
| 174 | WREG32(CG_SCRATCH2, 0x01B60A17); |
| 175 | |
| 176 | r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT, |
| 177 | xclk, 16, &p, &u); |
| 178 | |
| 179 | WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), |
| 180 | ~(PGP_MASK | PGU_MASK)); |
| 181 | |
| 182 | r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT, |
| 183 | xclk, 16, &p, &u); |
| 184 | |
| 185 | WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), |
| 186 | ~(PGP_MASK | PGU_MASK)); |
| 187 | |
| 188 | if (rdev->family == CHIP_PALM) { |
| 189 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210); |
| 190 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010); |
| 191 | } else { |
| 192 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210); |
| 193 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98); |
| 194 | } |
| 195 | |
| 196 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); |
| 197 | rcu_pwr_gating_cntl &= |
| 198 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); |
| 199 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN; |
| 200 | if (rdev->family == CHIP_PALM) { |
| 201 | rcu_pwr_gating_cntl &= ~PCP_MASK; |
| 202 | rcu_pwr_gating_cntl |= PCP(0x77); |
| 203 | } |
| 204 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); |
| 205 | |
| 206 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); |
| 207 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); |
| 208 | rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50); |
| 209 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); |
| 210 | |
| 211 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); |
| 212 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); |
| 213 | rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50); |
| 214 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); |
| 215 | |
| 216 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4); |
| 217 | rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK); |
| 218 | rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); |
| 219 | WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl); |
| 220 | |
| 221 | if (rdev->family == CHIP_PALM) |
| 222 | WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02); |
| 223 | |
| 224 | sumo_smu_pg_init(rdev); |
| 225 | |
| 226 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); |
| 227 | rcu_pwr_gating_cntl &= |
| 228 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); |
| 229 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN; |
| 230 | if (rdev->family == CHIP_PALM) { |
| 231 | rcu_pwr_gating_cntl &= ~PCP_MASK; |
| 232 | rcu_pwr_gating_cntl |= PCP(0x77); |
| 233 | } |
| 234 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); |
| 235 | |
| 236 | if (rdev->family == CHIP_PALM) { |
| 237 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); |
| 238 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); |
| 239 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); |
| 240 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); |
| 241 | |
| 242 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); |
| 243 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); |
| 244 | rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50); |
| 245 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); |
| 246 | } |
| 247 | |
| 248 | sumo_smu_pg_init(rdev); |
| 249 | |
| 250 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); |
| 251 | rcu_pwr_gating_cntl &= |
| 252 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); |
| 253 | rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN; |
| 254 | |
| 255 | if (rdev->family == CHIP_PALM) { |
| 256 | rcu_pwr_gating_cntl |= PCV(4); |
| 257 | rcu_pwr_gating_cntl &= ~PCP_MASK; |
| 258 | rcu_pwr_gating_cntl |= PCP(0x77); |
| 259 | } else |
| 260 | rcu_pwr_gating_cntl |= PCV(11); |
| 261 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); |
| 262 | |
| 263 | if (rdev->family == CHIP_PALM) { |
| 264 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); |
| 265 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); |
| 266 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); |
| 267 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); |
| 268 | |
| 269 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); |
| 270 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); |
| 271 | rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50); |
| 272 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); |
| 273 | } |
| 274 | |
| 275 | sumo_smu_pg_init(rdev); |
| 276 | } |
| 277 | |
| 278 | static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable) |
| 279 | { |
| 280 | if (enable) |
| 281 | WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); |
| 282 | else { |
| 283 | WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); |
| 284 | RREG32(GB_ADDR_CONFIG); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | static int sumo_enable_clock_power_gating(struct radeon_device *rdev) |
| 289 | { |
| 290 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 291 | |
| 292 | if (pi->enable_gfx_clock_gating) |
| 293 | sumo_gfx_clockgating_initialize(rdev); |
| 294 | if (pi->enable_gfx_power_gating) |
| 295 | sumo_gfx_powergating_initialize(rdev); |
| 296 | if (pi->enable_mg_clock_gating) |
| 297 | sumo_mg_clockgating_enable(rdev, true); |
| 298 | if (pi->enable_gfx_clock_gating) |
| 299 | sumo_gfx_clockgating_enable(rdev, true); |
| 300 | if (pi->enable_gfx_power_gating) |
| 301 | sumo_gfx_powergating_enable(rdev, true); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static void sumo_disable_clock_power_gating(struct radeon_device *rdev) |
| 307 | { |
| 308 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 309 | |
| 310 | if (pi->enable_gfx_clock_gating) |
| 311 | sumo_gfx_clockgating_enable(rdev, false); |
| 312 | if (pi->enable_gfx_power_gating) |
| 313 | sumo_gfx_powergating_enable(rdev, false); |
| 314 | if (pi->enable_mg_clock_gating) |
| 315 | sumo_mg_clockgating_enable(rdev, false); |
| 316 | } |
| 317 | |
| 318 | static void sumo_calculate_bsp(struct radeon_device *rdev, |
| 319 | u32 high_clk) |
| 320 | { |
| 321 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 322 | u32 xclk = sumo_get_xclk(rdev); |
| 323 | |
| 324 | pi->pasi = 65535 * 100 / high_clk; |
| 325 | pi->asi = 65535 * 100 / high_clk; |
| 326 | |
| 327 | r600_calculate_u_and_p(pi->asi, |
| 328 | xclk, 16, &pi->bsp, &pi->bsu); |
| 329 | |
| 330 | r600_calculate_u_and_p(pi->pasi, |
| 331 | xclk, 16, &pi->pbsp, &pi->pbsu); |
| 332 | |
| 333 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); |
| 334 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); |
| 335 | } |
| 336 | |
| 337 | static void sumo_init_bsp(struct radeon_device *rdev) |
| 338 | { |
| 339 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 340 | |
| 341 | WREG32(CG_BSP_0, pi->psp); |
| 342 | } |
| 343 | |
| 344 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 345 | static void sumo_program_bsp(struct radeon_device *rdev, |
| 346 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 347 | { |
| 348 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 349 | struct sumo_ps *ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 350 | u32 i; |
| 351 | u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; |
| 352 | |
| 353 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) |
| 354 | highest_engine_clock = pi->boost_pl.sclk; |
| 355 | |
| 356 | sumo_calculate_bsp(rdev, highest_engine_clock); |
| 357 | |
| 358 | for (i = 0; i < ps->num_levels - 1; i++) |
| 359 | WREG32(CG_BSP_0 + (i * 4), pi->dsp); |
| 360 | |
| 361 | WREG32(CG_BSP_0 + (i * 4), pi->psp); |
| 362 | |
| 363 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) |
| 364 | WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); |
| 365 | } |
| 366 | |
| 367 | static void sumo_write_at(struct radeon_device *rdev, |
| 368 | u32 index, u32 value) |
| 369 | { |
| 370 | if (index == 0) |
| 371 | WREG32(CG_AT_0, value); |
| 372 | else if (index == 1) |
| 373 | WREG32(CG_AT_1, value); |
| 374 | else if (index == 2) |
| 375 | WREG32(CG_AT_2, value); |
| 376 | else if (index == 3) |
| 377 | WREG32(CG_AT_3, value); |
| 378 | else if (index == 4) |
| 379 | WREG32(CG_AT_4, value); |
| 380 | else if (index == 5) |
| 381 | WREG32(CG_AT_5, value); |
| 382 | else if (index == 6) |
| 383 | WREG32(CG_AT_6, value); |
| 384 | else if (index == 7) |
| 385 | WREG32(CG_AT_7, value); |
| 386 | } |
| 387 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 388 | static void sumo_program_at(struct radeon_device *rdev, |
| 389 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 390 | { |
| 391 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 392 | struct sumo_ps *ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 393 | u32 asi; |
| 394 | u32 i; |
| 395 | u32 m_a; |
| 396 | u32 a_t; |
| 397 | u32 r[SUMO_MAX_HARDWARE_POWERLEVELS]; |
| 398 | u32 l[SUMO_MAX_HARDWARE_POWERLEVELS]; |
| 399 | |
| 400 | r[0] = SUMO_R_DFLT0; |
| 401 | r[1] = SUMO_R_DFLT1; |
| 402 | r[2] = SUMO_R_DFLT2; |
| 403 | r[3] = SUMO_R_DFLT3; |
| 404 | r[4] = SUMO_R_DFLT4; |
| 405 | |
| 406 | l[0] = SUMO_L_DFLT0; |
| 407 | l[1] = SUMO_L_DFLT1; |
| 408 | l[2] = SUMO_L_DFLT2; |
| 409 | l[3] = SUMO_L_DFLT3; |
| 410 | l[4] = SUMO_L_DFLT4; |
| 411 | |
| 412 | for (i = 0; i < ps->num_levels; i++) { |
| 413 | asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; |
| 414 | |
| 415 | m_a = asi * ps->levels[i].sclk / 100; |
| 416 | |
| 417 | a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100); |
| 418 | |
| 419 | sumo_write_at(rdev, i, a_t); |
| 420 | } |
| 421 | |
| 422 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { |
| 423 | asi = pi->pasi; |
| 424 | |
| 425 | m_a = asi * pi->boost_pl.sclk / 100; |
| 426 | |
| 427 | a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | |
| 428 | CG_L(m_a * l[ps->num_levels - 1] / 100); |
| 429 | |
| 430 | sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t); |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | static void sumo_program_tp(struct radeon_device *rdev) |
| 435 | { |
| 436 | int i; |
| 437 | enum r600_td td = R600_TD_DFLT; |
| 438 | |
| 439 | for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) { |
| 440 | WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); |
| 441 | WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); |
| 442 | } |
| 443 | |
| 444 | if (td == R600_TD_AUTO) |
| 445 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); |
| 446 | else |
| 447 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); |
| 448 | |
| 449 | if (td == R600_TD_UP) |
| 450 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); |
| 451 | |
| 452 | if (td == R600_TD_DOWN) |
| 453 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); |
| 454 | } |
| 455 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 456 | void sumo_program_vc(struct radeon_device *rdev, u32 vrc) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 457 | { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 458 | WREG32(CG_FTV, vrc); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 459 | } |
| 460 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 461 | void sumo_clear_vc(struct radeon_device *rdev) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 462 | { |
| 463 | WREG32(CG_FTV, 0); |
| 464 | } |
| 465 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 466 | void sumo_program_sstp(struct radeon_device *rdev) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 467 | { |
| 468 | u32 p, u; |
| 469 | u32 xclk = sumo_get_xclk(rdev); |
| 470 | |
| 471 | r600_calculate_u_and_p(SUMO_SST_DFLT, |
| 472 | xclk, 16, &p, &u); |
| 473 | |
| 474 | WREG32(CG_SSP, SSTU(u) | SST(p)); |
| 475 | } |
| 476 | |
| 477 | static void sumo_set_divider_value(struct radeon_device *rdev, |
| 478 | u32 index, u32 divider) |
| 479 | { |
| 480 | u32 reg_index = index / 4; |
| 481 | u32 field_index = index % 4; |
| 482 | |
| 483 | if (field_index == 0) |
| 484 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 485 | SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); |
| 486 | else if (field_index == 1) |
| 487 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 488 | SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); |
| 489 | else if (field_index == 2) |
| 490 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 491 | SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); |
| 492 | else if (field_index == 3) |
| 493 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 494 | SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); |
| 495 | } |
| 496 | |
| 497 | static void sumo_set_ds_dividers(struct radeon_device *rdev, |
| 498 | u32 index, u32 divider) |
| 499 | { |
| 500 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 501 | |
| 502 | if (pi->enable_sclk_ds) { |
| 503 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); |
| 504 | |
| 505 | dpm_ctrl &= ~(0x7 << (index * 3)); |
| 506 | dpm_ctrl |= (divider << (index * 3)); |
| 507 | WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | static void sumo_set_ss_dividers(struct radeon_device *rdev, |
| 512 | u32 index, u32 divider) |
| 513 | { |
| 514 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 515 | |
| 516 | if (pi->enable_sclk_ds) { |
| 517 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); |
| 518 | |
| 519 | dpm_ctrl &= ~(0x7 << (index * 3)); |
| 520 | dpm_ctrl |= (divider << (index * 3)); |
| 521 | WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid) |
| 526 | { |
| 527 | u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); |
| 528 | |
| 529 | voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2)); |
| 530 | voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2)); |
| 531 | WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl); |
| 532 | } |
| 533 | |
| 534 | static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow) |
| 535 | { |
| 536 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 537 | u32 temp = gnb_slow; |
| 538 | u32 cg_sclk_dpm_ctrl_3; |
| 539 | |
| 540 | if (pi->driver_nbps_policy_disable) |
| 541 | temp = 1; |
| 542 | |
| 543 | cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); |
| 544 | cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index); |
| 545 | cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index)); |
| 546 | |
| 547 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); |
| 548 | } |
| 549 | |
| 550 | static void sumo_program_power_level(struct radeon_device *rdev, |
| 551 | struct sumo_pl *pl, u32 index) |
| 552 | { |
| 553 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 554 | int ret; |
| 555 | struct atom_clock_dividers dividers; |
| 556 | u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; |
| 557 | |
| 558 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 559 | pl->sclk, false, ÷rs); |
| 560 | if (ret) |
| 561 | return; |
| 562 | |
| 563 | sumo_set_divider_value(rdev, index, dividers.post_div); |
| 564 | |
| 565 | sumo_set_vid(rdev, index, pl->vddc_index); |
| 566 | |
| 567 | if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) { |
| 568 | if (ds_en) |
| 569 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); |
| 570 | } else { |
| 571 | sumo_set_ss_dividers(rdev, index, pl->ss_divider_index); |
| 572 | sumo_set_ds_dividers(rdev, index, pl->ds_divider_index); |
| 573 | |
| 574 | if (!ds_en) |
| 575 | WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS); |
| 576 | } |
| 577 | |
| 578 | sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); |
| 579 | |
| 580 | if (pi->enable_boost) |
| 581 | sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit); |
| 582 | } |
| 583 | |
| 584 | static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable) |
| 585 | { |
| 586 | u32 reg_index = index / 4; |
| 587 | u32 field_index = index % 4; |
| 588 | |
| 589 | if (field_index == 0) |
| 590 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 591 | enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD); |
| 592 | else if (field_index == 1) |
| 593 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 594 | enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD); |
| 595 | else if (field_index == 2) |
| 596 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 597 | enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD); |
| 598 | else if (field_index == 3) |
| 599 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), |
| 600 | enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD); |
| 601 | } |
| 602 | |
| 603 | static bool sumo_dpm_enabled(struct radeon_device *rdev) |
| 604 | { |
| 605 | if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) |
| 606 | return true; |
| 607 | else |
| 608 | return false; |
| 609 | } |
| 610 | |
| 611 | static void sumo_start_dpm(struct radeon_device *rdev) |
| 612 | { |
| 613 | WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); |
| 614 | } |
| 615 | |
| 616 | static void sumo_stop_dpm(struct radeon_device *rdev) |
| 617 | { |
| 618 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); |
| 619 | } |
| 620 | |
| 621 | static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable) |
| 622 | { |
| 623 | if (enable) |
| 624 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); |
| 625 | else |
| 626 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); |
| 627 | } |
| 628 | |
| 629 | static void sumo_set_forced_mode_enabled(struct radeon_device *rdev) |
| 630 | { |
| 631 | int i; |
| 632 | |
| 633 | sumo_set_forced_mode(rdev, true); |
| 634 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 635 | if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT) |
| 636 | break; |
| 637 | udelay(1); |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | static void sumo_wait_for_level_0(struct radeon_device *rdev) |
| 642 | { |
| 643 | int i; |
| 644 | |
| 645 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 646 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0) |
| 647 | break; |
| 648 | udelay(1); |
| 649 | } |
| 650 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 651 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0) |
| 652 | break; |
| 653 | udelay(1); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | static void sumo_set_forced_mode_disabled(struct radeon_device *rdev) |
| 658 | { |
| 659 | sumo_set_forced_mode(rdev, false); |
| 660 | } |
| 661 | |
| 662 | static void sumo_enable_power_level_0(struct radeon_device *rdev) |
| 663 | { |
| 664 | sumo_power_level_enable(rdev, 0, true); |
| 665 | } |
| 666 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 667 | static void sumo_patch_boost_state(struct radeon_device *rdev, |
| 668 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 669 | { |
| 670 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 671 | struct sumo_ps *new_ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 672 | |
| 673 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { |
| 674 | pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; |
| 675 | pi->boost_pl.sclk = pi->sys_info.boost_sclk; |
| 676 | pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit; |
| 677 | pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost; |
| 678 | } |
| 679 | } |
| 680 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 681 | static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev, |
| 682 | struct radeon_ps *new_rps, |
| 683 | struct radeon_ps *old_rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 684 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 685 | struct sumo_ps *new_ps = sumo_get_ps(new_rps); |
| 686 | struct sumo_ps *old_ps = sumo_get_ps(old_rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 687 | u32 nbps1_old = 0; |
| 688 | u32 nbps1_new = 0; |
| 689 | |
| 690 | if (old_ps != NULL) |
| 691 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; |
| 692 | |
| 693 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; |
| 694 | |
| 695 | if (nbps1_old == 1 && nbps1_new == 0) |
| 696 | sumo_smu_notify_alt_vddnb_change(rdev, 0, 0); |
| 697 | } |
| 698 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 699 | static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev, |
| 700 | struct radeon_ps *new_rps, |
| 701 | struct radeon_ps *old_rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 702 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 703 | struct sumo_ps *new_ps = sumo_get_ps(new_rps); |
| 704 | struct sumo_ps *old_ps = sumo_get_ps(old_rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 705 | u32 nbps1_old = 0; |
| 706 | u32 nbps1_new = 0; |
| 707 | |
| 708 | if (old_ps != NULL) |
| 709 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; |
| 710 | |
| 711 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; |
| 712 | |
| 713 | if (nbps1_old == 0 && nbps1_new == 1) |
| 714 | sumo_smu_notify_alt_vddnb_change(rdev, 1, 1); |
| 715 | } |
| 716 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 717 | static void sumo_enable_boost(struct radeon_device *rdev, |
| 718 | struct radeon_ps *rps, |
| 719 | bool enable) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 720 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 721 | struct sumo_ps *new_ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 722 | |
| 723 | if (enable) { |
| 724 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) |
| 725 | sumo_boost_state_enable(rdev, true); |
| 726 | } else |
| 727 | sumo_boost_state_enable(rdev, false); |
| 728 | } |
| 729 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 730 | static void sumo_update_current_power_levels(struct radeon_device *rdev, |
| 731 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 732 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 733 | struct sumo_ps *new_ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 734 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 735 | |
| 736 | pi->current_ps = *new_ps; |
| 737 | } |
| 738 | |
| 739 | static void sumo_set_forced_level(struct radeon_device *rdev, u32 index) |
| 740 | { |
| 741 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); |
| 742 | } |
| 743 | |
| 744 | static void sumo_set_forced_level_0(struct radeon_device *rdev) |
| 745 | { |
| 746 | sumo_set_forced_level(rdev, 0); |
| 747 | } |
| 748 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 749 | static void sumo_program_wl(struct radeon_device *rdev, |
| 750 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 751 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 752 | struct sumo_ps *new_ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 753 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); |
| 754 | |
| 755 | dpm_ctrl4 &= 0xFFFFFF00; |
| 756 | dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); |
| 757 | |
| 758 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) |
| 759 | dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL); |
| 760 | |
| 761 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); |
| 762 | } |
| 763 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 764 | static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev, |
| 765 | struct radeon_ps *new_rps, |
| 766 | struct radeon_ps *old_rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 767 | { |
| 768 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 769 | struct sumo_ps *new_ps = sumo_get_ps(new_rps); |
| 770 | struct sumo_ps *old_ps = sumo_get_ps(old_rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 771 | u32 i; |
| 772 | u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; |
| 773 | |
| 774 | for (i = 0; i < new_ps->num_levels; i++) { |
| 775 | sumo_program_power_level(rdev, &new_ps->levels[i], i); |
| 776 | sumo_power_level_enable(rdev, i, true); |
| 777 | } |
| 778 | |
| 779 | for (i = new_ps->num_levels; i < n_current_state_levels; i++) |
| 780 | sumo_power_level_enable(rdev, i, false); |
| 781 | |
| 782 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) |
| 783 | sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL); |
| 784 | } |
| 785 | |
| 786 | static void sumo_enable_acpi_pm(struct radeon_device *rdev) |
| 787 | { |
| 788 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); |
| 789 | } |
| 790 | |
| 791 | static void sumo_program_power_level_enter_state(struct radeon_device *rdev) |
| 792 | { |
| 793 | WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); |
| 794 | } |
| 795 | |
| 796 | static void sumo_program_acpi_power_level(struct radeon_device *rdev) |
| 797 | { |
| 798 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 799 | struct atom_clock_dividers dividers; |
| 800 | int ret; |
| 801 | |
| 802 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 803 | pi->acpi_pl.sclk, |
| 804 | false, ÷rs); |
| 805 | if (ret) |
| 806 | return; |
| 807 | |
| 808 | WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); |
| 809 | WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN); |
| 810 | } |
| 811 | |
| 812 | static void sumo_program_bootup_state(struct radeon_device *rdev) |
| 813 | { |
| 814 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 815 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); |
| 816 | u32 i; |
| 817 | |
| 818 | sumo_program_power_level(rdev, &pi->boot_pl, 0); |
| 819 | |
| 820 | dpm_ctrl4 &= 0xFFFFFF00; |
| 821 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); |
| 822 | |
| 823 | for (i = 1; i < 8; i++) |
| 824 | sumo_power_level_enable(rdev, i, false); |
| 825 | } |
| 826 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 827 | static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, |
| 828 | struct radeon_ps *new_rps, |
| 829 | struct radeon_ps *old_rps) |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 830 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 831 | struct sumo_ps *new_ps = sumo_get_ps(new_rps); |
| 832 | struct sumo_ps *current_ps = sumo_get_ps(old_rps); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 833 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 834 | if ((new_rps->vclk == old_rps->vclk) && |
| 835 | (new_rps->dclk == old_rps->dclk)) |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 836 | return; |
| 837 | |
| 838 | if (new_ps->levels[new_ps->num_levels - 1].sclk >= |
| 839 | current_ps->levels[current_ps->num_levels - 1].sclk) |
| 840 | return; |
| 841 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 842 | radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 843 | } |
| 844 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 845 | static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, |
| 846 | struct radeon_ps *new_rps, |
| 847 | struct radeon_ps *old_rps) |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 848 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 849 | struct sumo_ps *new_ps = sumo_get_ps(new_rps); |
| 850 | struct sumo_ps *current_ps = sumo_get_ps(old_rps); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 851 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 852 | if ((new_rps->vclk == old_rps->vclk) && |
| 853 | (new_rps->dclk == old_rps->dclk)) |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 854 | return; |
| 855 | |
| 856 | if (new_ps->levels[new_ps->num_levels - 1].sclk < |
| 857 | current_ps->levels[current_ps->num_levels - 1].sclk) |
| 858 | return; |
| 859 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 860 | radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 861 | } |
| 862 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 863 | void sumo_take_smu_control(struct radeon_device *rdev, bool enable) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 864 | { |
Alex Deucher | 65676d0 | 2012-11-27 12:10:35 -0500 | [diff] [blame] | 865 | /* This bit selects who handles display phy powergating. |
| 866 | * Clear the bit to let atom handle it. |
| 867 | * Set it to let the driver handle it. |
| 868 | * For now we just let atom handle it. |
| 869 | */ |
| 870 | #if 0 |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 871 | u32 v = RREG32(DOUT_SCRATCH3); |
| 872 | |
| 873 | if (enable) |
| 874 | v |= 0x4; |
| 875 | else |
| 876 | v &= 0xFFFFFFFB; |
| 877 | |
| 878 | WREG32(DOUT_SCRATCH3, v); |
Alex Deucher | 65676d0 | 2012-11-27 12:10:35 -0500 | [diff] [blame] | 879 | #endif |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable) |
| 883 | { |
| 884 | if (enable) { |
| 885 | u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL); |
| 886 | u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2); |
| 887 | u32 t = 1; |
| 888 | |
| 889 | deep_sleep_cntl &= ~R_DIS; |
| 890 | deep_sleep_cntl &= ~HS_MASK; |
| 891 | deep_sleep_cntl |= HS(t > 4095 ? 4095 : t); |
| 892 | |
| 893 | deep_sleep_cntl2 |= LB_UFP_EN; |
| 894 | deep_sleep_cntl2 &= INOUT_C_MASK; |
| 895 | deep_sleep_cntl2 |= INOUT_C(0xf); |
| 896 | |
| 897 | WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2); |
| 898 | WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl); |
| 899 | } else |
| 900 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); |
| 901 | } |
| 902 | |
| 903 | static void sumo_program_bootup_at(struct radeon_device *rdev) |
| 904 | { |
| 905 | WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK); |
| 906 | WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); |
| 907 | } |
| 908 | |
| 909 | static void sumo_reset_am(struct radeon_device *rdev) |
| 910 | { |
| 911 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); |
| 912 | } |
| 913 | |
| 914 | static void sumo_start_am(struct radeon_device *rdev) |
| 915 | { |
| 916 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); |
| 917 | } |
| 918 | |
| 919 | static void sumo_program_ttp(struct radeon_device *rdev) |
| 920 | { |
| 921 | u32 xclk = sumo_get_xclk(rdev); |
| 922 | u32 p, u; |
| 923 | u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); |
| 924 | |
| 925 | r600_calculate_u_and_p(1000, |
| 926 | xclk, 16, &p, &u); |
| 927 | |
| 928 | cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK); |
| 929 | cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u); |
| 930 | |
| 931 | WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5); |
| 932 | } |
| 933 | |
| 934 | static void sumo_program_ttt(struct radeon_device *rdev) |
| 935 | { |
| 936 | u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); |
| 937 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 938 | |
| 939 | cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK); |
| 940 | cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49); |
| 941 | |
| 942 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); |
| 943 | } |
| 944 | |
| 945 | |
| 946 | static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable) |
| 947 | { |
| 948 | if (enable) { |
| 949 | WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN); |
| 950 | WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN); |
| 951 | } else { |
| 952 | WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN); |
| 953 | WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN); |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | static void sumo_override_cnb_thermal_events(struct radeon_device *rdev) |
| 958 | { |
| 959 | WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK, |
| 960 | ~CNB_THERMTHRO_MASK_SCLK); |
| 961 | } |
| 962 | |
| 963 | static void sumo_program_dc_hto(struct radeon_device *rdev) |
| 964 | { |
| 965 | u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); |
| 966 | u32 p, u; |
| 967 | u32 xclk = sumo_get_xclk(rdev); |
| 968 | |
| 969 | r600_calculate_u_and_p(100000, |
| 970 | xclk, 14, &p, &u); |
| 971 | |
| 972 | cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK); |
| 973 | cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u); |
| 974 | |
| 975 | WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4); |
| 976 | } |
| 977 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 978 | static void sumo_force_nbp_state(struct radeon_device *rdev, |
| 979 | struct radeon_ps *rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 980 | { |
| 981 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 982 | struct sumo_ps *new_ps = sumo_get_ps(rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 983 | |
| 984 | if (!pi->driver_nbps_policy_disable) { |
| 985 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) |
| 986 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1); |
| 987 | else |
| 988 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1); |
| 989 | } |
| 990 | } |
| 991 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 992 | u32 sumo_get_sleep_divider_from_id(u32 id) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 993 | { |
| 994 | return 1 << id; |
| 995 | } |
| 996 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 997 | u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, |
| 998 | u32 sclk, |
| 999 | u32 min_sclk_in_sr) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1000 | { |
| 1001 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1002 | u32 i; |
| 1003 | u32 temp; |
| 1004 | u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ? |
| 1005 | min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK; |
| 1006 | |
| 1007 | if (sclk < min) |
| 1008 | return 0; |
| 1009 | |
| 1010 | if (!pi->enable_sclk_ds) |
| 1011 | return 0; |
| 1012 | |
| 1013 | for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { |
| 1014 | temp = sclk / sumo_get_sleep_divider_from_id(i); |
| 1015 | |
| 1016 | if (temp >= min || i == 0) |
| 1017 | break; |
| 1018 | } |
| 1019 | return i; |
| 1020 | } |
| 1021 | |
| 1022 | static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev, |
| 1023 | u32 lower_limit) |
| 1024 | { |
| 1025 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1026 | u32 i; |
| 1027 | |
| 1028 | for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { |
| 1029 | if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) |
| 1030 | return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; |
| 1031 | } |
| 1032 | |
| 1033 | return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency; |
| 1034 | } |
| 1035 | |
| 1036 | static void sumo_patch_thermal_state(struct radeon_device *rdev, |
| 1037 | struct sumo_ps *ps, |
| 1038 | struct sumo_ps *current_ps) |
| 1039 | { |
| 1040 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1041 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ |
| 1042 | u32 current_vddc; |
| 1043 | u32 current_sclk; |
| 1044 | u32 current_index = 0; |
| 1045 | |
| 1046 | if (current_ps) { |
| 1047 | current_vddc = current_ps->levels[current_index].vddc_index; |
| 1048 | current_sclk = current_ps->levels[current_index].sclk; |
| 1049 | } else { |
| 1050 | current_vddc = pi->boot_pl.vddc_index; |
| 1051 | current_sclk = pi->boot_pl.sclk; |
| 1052 | } |
| 1053 | |
| 1054 | ps->levels[0].vddc_index = current_vddc; |
| 1055 | |
| 1056 | if (ps->levels[0].sclk > current_sclk) |
| 1057 | ps->levels[0].sclk = current_sclk; |
| 1058 | |
| 1059 | ps->levels[0].ss_divider_index = |
| 1060 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); |
| 1061 | |
| 1062 | ps->levels[0].ds_divider_index = |
| 1063 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK); |
| 1064 | |
| 1065 | if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1) |
| 1066 | ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1; |
| 1067 | |
| 1068 | if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) { |
| 1069 | if (ps->levels[0].ss_divider_index > 1) |
| 1070 | ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1; |
| 1071 | } |
| 1072 | |
| 1073 | if (ps->levels[0].ss_divider_index == 0) |
| 1074 | ps->levels[0].ds_divider_index = 0; |
| 1075 | |
| 1076 | if (ps->levels[0].ds_divider_index == 0) |
| 1077 | ps->levels[0].ss_divider_index = 0; |
| 1078 | } |
| 1079 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1080 | static void sumo_apply_state_adjust_rules(struct radeon_device *rdev, |
| 1081 | struct radeon_ps *new_rps, |
| 1082 | struct radeon_ps *old_rps) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1083 | { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1084 | struct sumo_ps *ps = sumo_get_ps(new_rps); |
| 1085 | struct sumo_ps *current_ps = sumo_get_ps(old_rps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1086 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1087 | u32 min_voltage = 0; /* ??? */ |
| 1088 | u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ |
| 1089 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ |
| 1090 | u32 i; |
| 1091 | |
Alex Deucher | 7cf36de | 2012-11-29 20:27:50 -0500 | [diff] [blame] | 1092 | /* point to the hw copy since this function will modify the ps */ |
| 1093 | pi->hw_ps = *ps; |
| 1094 | rdev->pm.dpm.hw_ps.ps_priv = &pi->hw_ps; |
| 1095 | ps = &pi->hw_ps; |
| 1096 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1097 | if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1098 | return sumo_patch_thermal_state(rdev, ps, current_ps); |
| 1099 | |
| 1100 | if (pi->enable_boost) { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1101 | if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1102 | ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE; |
| 1103 | } |
| 1104 | |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1105 | if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || |
| 1106 | (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) || |
| 1107 | (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1108 | ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE; |
| 1109 | |
| 1110 | for (i = 0; i < ps->num_levels; i++) { |
| 1111 | if (ps->levels[i].vddc_index < min_voltage) |
| 1112 | ps->levels[i].vddc_index = min_voltage; |
| 1113 | |
| 1114 | if (ps->levels[i].sclk < min_sclk) |
| 1115 | ps->levels[i].sclk = |
| 1116 | sumo_get_valid_engine_clock(rdev, min_sclk); |
| 1117 | |
| 1118 | ps->levels[i].ss_divider_index = |
| 1119 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); |
| 1120 | |
| 1121 | ps->levels[i].ds_divider_index = |
| 1122 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK); |
| 1123 | |
| 1124 | if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1) |
| 1125 | ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1; |
| 1126 | |
| 1127 | if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) { |
| 1128 | if (ps->levels[i].ss_divider_index > 1) |
| 1129 | ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1; |
| 1130 | } |
| 1131 | |
| 1132 | if (ps->levels[i].ss_divider_index == 0) |
| 1133 | ps->levels[i].ds_divider_index = 0; |
| 1134 | |
| 1135 | if (ps->levels[i].ds_divider_index == 0) |
| 1136 | ps->levels[i].ss_divider_index = 0; |
| 1137 | |
| 1138 | if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) |
| 1139 | ps->levels[i].allow_gnb_slow = 1; |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1140 | else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) || |
| 1141 | (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1142 | ps->levels[i].allow_gnb_slow = 0; |
| 1143 | else if (i == ps->num_levels - 1) |
| 1144 | ps->levels[i].allow_gnb_slow = 0; |
| 1145 | else |
| 1146 | ps->levels[i].allow_gnb_slow = 1; |
| 1147 | } |
| 1148 | } |
| 1149 | |
| 1150 | static void sumo_cleanup_asic(struct radeon_device *rdev) |
| 1151 | { |
| 1152 | sumo_take_smu_control(rdev, false); |
| 1153 | } |
| 1154 | |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 1155 | static void sumo_uvd_init(struct radeon_device *rdev) |
| 1156 | { |
| 1157 | u32 tmp; |
| 1158 | |
| 1159 | tmp = RREG32(CG_VCLK_CNTL); |
| 1160 | tmp &= ~VCLK_DIR_CNTL_EN; |
| 1161 | WREG32(CG_VCLK_CNTL, tmp); |
| 1162 | |
| 1163 | tmp = RREG32(CG_DCLK_CNTL); |
| 1164 | tmp &= ~DCLK_DIR_CNTL_EN; |
| 1165 | WREG32(CG_DCLK_CNTL, tmp); |
| 1166 | |
| 1167 | /* 100 Mhz */ |
| 1168 | radeon_set_uvd_clocks(rdev, 10000, 10000); |
| 1169 | } |
| 1170 | |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1171 | static int sumo_set_thermal_temperature_range(struct radeon_device *rdev, |
| 1172 | int min_temp, int max_temp) |
| 1173 | { |
| 1174 | int low_temp = 0 * 1000; |
| 1175 | int high_temp = 255 * 1000; |
| 1176 | |
| 1177 | if (low_temp < min_temp) |
| 1178 | low_temp = min_temp; |
| 1179 | if (high_temp > max_temp) |
| 1180 | high_temp = max_temp; |
| 1181 | if (high_temp < low_temp) { |
| 1182 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); |
| 1183 | return -EINVAL; |
| 1184 | } |
| 1185 | |
| 1186 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); |
| 1187 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); |
| 1188 | |
| 1189 | rdev->pm.dpm.thermal.min_temp = low_temp; |
| 1190 | rdev->pm.dpm.thermal.max_temp = high_temp; |
| 1191 | |
| 1192 | return 0; |
| 1193 | } |
| 1194 | |
| 1195 | int sumo_dpm_enable(struct radeon_device *rdev) |
| 1196 | { |
| 1197 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1198 | |
| 1199 | if (sumo_dpm_enabled(rdev)) |
| 1200 | return -EINVAL; |
| 1201 | |
| 1202 | sumo_enable_clock_power_gating(rdev); |
| 1203 | sumo_program_bootup_state(rdev); |
| 1204 | sumo_init_bsp(rdev); |
| 1205 | sumo_reset_am(rdev); |
| 1206 | sumo_program_tp(rdev); |
| 1207 | sumo_program_bootup_at(rdev); |
| 1208 | sumo_start_am(rdev); |
| 1209 | if (pi->enable_auto_thermal_throttling) { |
| 1210 | sumo_program_ttp(rdev); |
| 1211 | sumo_program_ttt(rdev); |
| 1212 | } |
| 1213 | sumo_program_dc_hto(rdev); |
| 1214 | sumo_program_power_level_enter_state(rdev); |
| 1215 | sumo_enable_voltage_scaling(rdev, true); |
| 1216 | sumo_program_sstp(rdev); |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1217 | sumo_program_vc(rdev, SUMO_VRC_DFLT); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1218 | sumo_override_cnb_thermal_events(rdev); |
| 1219 | sumo_start_dpm(rdev); |
| 1220 | sumo_wait_for_level_0(rdev); |
| 1221 | if (pi->enable_sclk_ds) |
| 1222 | sumo_enable_sclk_ds(rdev, true); |
| 1223 | if (pi->enable_boost) |
| 1224 | sumo_enable_boost_timer(rdev); |
| 1225 | |
| 1226 | if (rdev->irq.installed && |
| 1227 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { |
| 1228 | sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
| 1229 | rdev->irq.dpm_thermal = true; |
| 1230 | radeon_irq_set(rdev); |
| 1231 | } |
| 1232 | |
| 1233 | return 0; |
| 1234 | } |
| 1235 | |
| 1236 | void sumo_dpm_disable(struct radeon_device *rdev) |
| 1237 | { |
| 1238 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1239 | |
| 1240 | if (!sumo_dpm_enabled(rdev)) |
| 1241 | return; |
| 1242 | sumo_disable_clock_power_gating(rdev); |
| 1243 | if (pi->enable_sclk_ds) |
| 1244 | sumo_enable_sclk_ds(rdev, false); |
| 1245 | sumo_clear_vc(rdev); |
| 1246 | sumo_wait_for_level_0(rdev); |
| 1247 | sumo_stop_dpm(rdev); |
| 1248 | sumo_enable_voltage_scaling(rdev, false); |
| 1249 | |
| 1250 | if (rdev->irq.installed && |
| 1251 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { |
| 1252 | rdev->irq.dpm_thermal = false; |
| 1253 | radeon_irq_set(rdev); |
| 1254 | } |
| 1255 | } |
| 1256 | |
| 1257 | int sumo_dpm_set_power_state(struct radeon_device *rdev) |
| 1258 | { |
| 1259 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1260 | struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; |
| 1261 | struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1262 | |
| 1263 | if (pi->enable_dynamic_patch_ps) |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1264 | sumo_apply_state_adjust_rules(rdev, new_ps, old_ps); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 1265 | if (pi->enable_dpm) |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1266 | sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); |
| 1267 | sumo_update_current_power_levels(rdev, new_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1268 | if (pi->enable_boost) { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1269 | sumo_enable_boost(rdev, new_ps, false); |
| 1270 | sumo_patch_boost_state(rdev, new_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1271 | } |
| 1272 | if (pi->enable_dpm) { |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1273 | sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1274 | sumo_enable_power_level_0(rdev); |
| 1275 | sumo_set_forced_level_0(rdev); |
| 1276 | sumo_set_forced_mode_enabled(rdev); |
| 1277 | sumo_wait_for_level_0(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1278 | sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps); |
| 1279 | sumo_program_wl(rdev, new_ps); |
| 1280 | sumo_program_bsp(rdev, new_ps); |
| 1281 | sumo_program_at(rdev, new_ps); |
| 1282 | sumo_force_nbp_state(rdev, new_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1283 | sumo_set_forced_mode_disabled(rdev); |
| 1284 | sumo_set_forced_mode_enabled(rdev); |
| 1285 | sumo_set_forced_mode_disabled(rdev); |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1286 | sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1287 | } |
| 1288 | if (pi->enable_boost) |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1289 | sumo_enable_boost(rdev, new_ps, true); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 1290 | if (pi->enable_dpm) |
Alex Deucher | 34936f5 | 2013-06-25 15:31:49 -0400 | [diff] [blame^] | 1291 | sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1292 | |
| 1293 | return 0; |
| 1294 | } |
| 1295 | |
| 1296 | void sumo_dpm_reset_asic(struct radeon_device *rdev) |
| 1297 | { |
| 1298 | sumo_program_bootup_state(rdev); |
| 1299 | sumo_enable_power_level_0(rdev); |
| 1300 | sumo_set_forced_level_0(rdev); |
| 1301 | sumo_set_forced_mode_enabled(rdev); |
| 1302 | sumo_wait_for_level_0(rdev); |
| 1303 | sumo_set_forced_mode_disabled(rdev); |
| 1304 | sumo_set_forced_mode_enabled(rdev); |
| 1305 | sumo_set_forced_mode_disabled(rdev); |
| 1306 | } |
| 1307 | |
| 1308 | void sumo_dpm_setup_asic(struct radeon_device *rdev) |
| 1309 | { |
| 1310 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1311 | |
| 1312 | sumo_initialize_m3_arb(rdev); |
| 1313 | pi->fw_version = sumo_get_running_fw_version(rdev); |
| 1314 | DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version); |
| 1315 | sumo_program_acpi_power_level(rdev); |
| 1316 | sumo_enable_acpi_pm(rdev); |
| 1317 | sumo_take_smu_control(rdev, true); |
Alex Deucher | 06793df | 2012-12-05 15:59:11 -0500 | [diff] [blame] | 1318 | sumo_uvd_init(rdev); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1319 | } |
| 1320 | |
| 1321 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev) |
| 1322 | { |
| 1323 | |
| 1324 | } |
| 1325 | |
| 1326 | union power_info { |
| 1327 | struct _ATOM_POWERPLAY_INFO info; |
| 1328 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
| 1329 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
| 1330 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
| 1331 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
| 1332 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
| 1333 | }; |
| 1334 | |
| 1335 | union pplib_clock_info { |
| 1336 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
| 1337 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
| 1338 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
| 1339 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
| 1340 | }; |
| 1341 | |
| 1342 | union pplib_power_state { |
| 1343 | struct _ATOM_PPLIB_STATE v1; |
| 1344 | struct _ATOM_PPLIB_STATE_V2 v2; |
| 1345 | }; |
| 1346 | |
| 1347 | static void sumo_patch_boot_state(struct radeon_device *rdev, |
| 1348 | struct sumo_ps *ps) |
| 1349 | { |
| 1350 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1351 | |
| 1352 | ps->num_levels = 1; |
| 1353 | ps->flags = 0; |
| 1354 | ps->levels[0] = pi->boot_pl; |
| 1355 | } |
| 1356 | |
| 1357 | static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev, |
| 1358 | struct radeon_ps *rps, |
| 1359 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, |
| 1360 | u8 table_rev) |
| 1361 | { |
| 1362 | struct sumo_ps *ps = sumo_get_ps(rps); |
| 1363 | |
| 1364 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
| 1365 | rps->class = le16_to_cpu(non_clock_info->usClassification); |
| 1366 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); |
| 1367 | |
| 1368 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
| 1369 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
| 1370 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
| 1371 | } else { |
| 1372 | rps->vclk = 0; |
| 1373 | rps->dclk = 0; |
| 1374 | } |
| 1375 | |
| 1376 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
| 1377 | rdev->pm.dpm.boot_ps = rps; |
| 1378 | sumo_patch_boot_state(rdev, ps); |
| 1379 | } |
| 1380 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
| 1381 | rdev->pm.dpm.uvd_ps = rps; |
| 1382 | } |
| 1383 | |
| 1384 | static void sumo_parse_pplib_clock_info(struct radeon_device *rdev, |
| 1385 | struct radeon_ps *rps, int index, |
| 1386 | union pplib_clock_info *clock_info) |
| 1387 | { |
| 1388 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1389 | struct sumo_ps *ps = sumo_get_ps(rps); |
| 1390 | struct sumo_pl *pl = &ps->levels[index]; |
| 1391 | u32 sclk; |
| 1392 | |
| 1393 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); |
| 1394 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; |
| 1395 | pl->sclk = sclk; |
| 1396 | pl->vddc_index = clock_info->sumo.vddcIndex; |
| 1397 | pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit; |
| 1398 | |
| 1399 | ps->num_levels = index + 1; |
| 1400 | |
| 1401 | if (pi->enable_sclk_ds) { |
| 1402 | pl->ds_divider_index = 5; |
| 1403 | pl->ss_divider_index = 4; |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | static int sumo_parse_power_table(struct radeon_device *rdev) |
| 1408 | { |
| 1409 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1410 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
| 1411 | union pplib_power_state *power_state; |
| 1412 | int i, j, k, non_clock_array_index, clock_array_index; |
| 1413 | union pplib_clock_info *clock_info; |
| 1414 | struct _StateArray *state_array; |
| 1415 | struct _ClockInfoArray *clock_info_array; |
| 1416 | struct _NonClockInfoArray *non_clock_info_array; |
| 1417 | union power_info *power_info; |
| 1418 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 1419 | u16 data_offset; |
| 1420 | u8 frev, crev; |
| 1421 | u8 *power_state_offset; |
| 1422 | struct sumo_ps *ps; |
| 1423 | |
| 1424 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1425 | &frev, &crev, &data_offset)) |
| 1426 | return -EINVAL; |
| 1427 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 1428 | |
| 1429 | state_array = (struct _StateArray *) |
| 1430 | (mode_info->atom_context->bios + data_offset + |
| 1431 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
| 1432 | clock_info_array = (struct _ClockInfoArray *) |
| 1433 | (mode_info->atom_context->bios + data_offset + |
| 1434 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
| 1435 | non_clock_info_array = (struct _NonClockInfoArray *) |
| 1436 | (mode_info->atom_context->bios + data_offset + |
| 1437 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
| 1438 | |
| 1439 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * |
| 1440 | state_array->ucNumEntries, GFP_KERNEL); |
| 1441 | if (!rdev->pm.dpm.ps) |
| 1442 | return -ENOMEM; |
| 1443 | power_state_offset = (u8 *)state_array->states; |
| 1444 | rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); |
| 1445 | rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); |
| 1446 | rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); |
| 1447 | for (i = 0; i < state_array->ucNumEntries; i++) { |
| 1448 | power_state = (union pplib_power_state *)power_state_offset; |
| 1449 | non_clock_array_index = power_state->v2.nonClockInfoIndex; |
| 1450 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
| 1451 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
| 1452 | if (!rdev->pm.power_state[i].clock_info) |
| 1453 | return -EINVAL; |
| 1454 | ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); |
| 1455 | if (ps == NULL) { |
| 1456 | kfree(rdev->pm.dpm.ps); |
| 1457 | return -ENOMEM; |
| 1458 | } |
| 1459 | rdev->pm.dpm.ps[i].ps_priv = ps; |
| 1460 | k = 0; |
| 1461 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
| 1462 | clock_array_index = power_state->v2.clockInfoIndex[j]; |
| 1463 | if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) |
| 1464 | break; |
| 1465 | clock_info = (union pplib_clock_info *) |
| 1466 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
| 1467 | sumo_parse_pplib_clock_info(rdev, |
| 1468 | &rdev->pm.dpm.ps[i], k, |
| 1469 | clock_info); |
| 1470 | k++; |
| 1471 | } |
| 1472 | sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], |
| 1473 | non_clock_info, |
| 1474 | non_clock_info_array->ucEntrySize); |
| 1475 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
| 1476 | } |
| 1477 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1481 | u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, |
| 1482 | struct sumo_vid_mapping_table *vid_mapping_table, |
| 1483 | u32 vid_2bit) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1484 | { |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1485 | u32 i; |
| 1486 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1487 | for (i = 0; i < vid_mapping_table->num_entries; i++) { |
| 1488 | if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) |
| 1489 | return vid_mapping_table->entries[i].vid_7bit; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1490 | } |
| 1491 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1492 | return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1493 | } |
| 1494 | |
| 1495 | static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, |
| 1496 | u32 vid_2bit) |
| 1497 | { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1498 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1499 | u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1500 | |
| 1501 | if (vid_7bit > 0x7C) |
| 1502 | return 0; |
| 1503 | |
| 1504 | return (15500 - vid_7bit * 125 + 5) / 10; |
| 1505 | } |
| 1506 | |
| 1507 | static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev, |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1508 | struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table, |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1509 | ATOM_CLK_VOLT_CAPABILITY *table) |
| 1510 | { |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1511 | u32 i; |
| 1512 | |
| 1513 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { |
| 1514 | if (table[i].ulMaximumSupportedCLK == 0) |
| 1515 | break; |
| 1516 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1517 | disp_clk_voltage_mapping_table->display_clock_frequency[i] = |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1518 | table[i].ulMaximumSupportedCLK; |
| 1519 | } |
| 1520 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1521 | disp_clk_voltage_mapping_table->num_max_voltage_levels = i; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1522 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1523 | if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) { |
| 1524 | disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000; |
| 1525 | disp_clk_voltage_mapping_table->num_max_voltage_levels = 1; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1526 | } |
| 1527 | } |
| 1528 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1529 | void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, |
| 1530 | struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, |
| 1531 | ATOM_AVAILABLE_SCLK_LIST *table) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1532 | { |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1533 | u32 i; |
| 1534 | u32 n = 0; |
| 1535 | u32 prev_sclk = 0; |
| 1536 | |
| 1537 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { |
| 1538 | if (table[i].ulSupportedSCLK > prev_sclk) { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1539 | sclk_voltage_mapping_table->entries[n].sclk_frequency = |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1540 | table[i].ulSupportedSCLK; |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1541 | sclk_voltage_mapping_table->entries[n].vid_2bit = |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1542 | table[i].usVoltageIndex; |
| 1543 | prev_sclk = table[i].ulSupportedSCLK; |
| 1544 | n++; |
| 1545 | } |
| 1546 | } |
| 1547 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1548 | sclk_voltage_mapping_table->num_max_dpm_entries = n; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1549 | } |
| 1550 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1551 | void sumo_construct_vid_mapping_table(struct radeon_device *rdev, |
| 1552 | struct sumo_vid_mapping_table *vid_mapping_table, |
| 1553 | ATOM_AVAILABLE_SCLK_LIST *table) |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1554 | { |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1555 | u32 i, j; |
| 1556 | |
| 1557 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { |
| 1558 | if (table[i].ulSupportedSCLK != 0) { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1559 | vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1560 | table[i].usVoltageID; |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1561 | vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1562 | table[i].usVoltageIndex; |
| 1563 | } |
| 1564 | } |
| 1565 | |
| 1566 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1567 | if (vid_mapping_table->entries[i].vid_7bit == 0) { |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1568 | for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1569 | if (vid_mapping_table->entries[j].vid_7bit != 0) { |
| 1570 | vid_mapping_table->entries[i] = |
| 1571 | vid_mapping_table->entries[j]; |
| 1572 | vid_mapping_table->entries[j].vid_7bit = 0; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1573 | break; |
| 1574 | } |
| 1575 | } |
| 1576 | |
| 1577 | if (j == SUMO_MAX_NUMBER_VOLTAGES) |
| 1578 | break; |
| 1579 | } |
| 1580 | } |
| 1581 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1582 | vid_mapping_table->num_entries = i; |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1583 | } |
| 1584 | |
| 1585 | union igp_info { |
| 1586 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
| 1587 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; |
| 1588 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; |
| 1589 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; |
| 1590 | }; |
| 1591 | |
| 1592 | static int sumo_parse_sys_info_table(struct radeon_device *rdev) |
| 1593 | { |
| 1594 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1595 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1596 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
| 1597 | union igp_info *igp_info; |
| 1598 | u8 frev, crev; |
| 1599 | u16 data_offset; |
| 1600 | int i; |
| 1601 | |
| 1602 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1603 | &frev, &crev, &data_offset)) { |
| 1604 | igp_info = (union igp_info *)(mode_info->atom_context->bios + |
| 1605 | data_offset); |
| 1606 | |
| 1607 | if (crev != 6) { |
| 1608 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); |
| 1609 | return -EINVAL; |
| 1610 | } |
| 1611 | pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock); |
| 1612 | pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock); |
| 1613 | pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock); |
| 1614 | pi->sys_info.bootup_nb_voltage_index = |
| 1615 | le16_to_cpu(igp_info->info_6.usBootUpNBVoltage); |
| 1616 | if (igp_info->info_6.ucHtcTmpLmt == 0) |
| 1617 | pi->sys_info.htc_tmp_lmt = 203; |
| 1618 | else |
| 1619 | pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt; |
| 1620 | if (igp_info->info_6.ucHtcHystLmt == 0) |
| 1621 | pi->sys_info.htc_hyst_lmt = 5; |
| 1622 | else |
| 1623 | pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt; |
| 1624 | if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { |
| 1625 | DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); |
| 1626 | } |
| 1627 | for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) { |
| 1628 | pi->sys_info.csr_m3_arb_cntl_default[i] = |
| 1629 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]); |
| 1630 | pi->sys_info.csr_m3_arb_cntl_uvd[i] = |
| 1631 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]); |
| 1632 | pi->sys_info.csr_m3_arb_cntl_fs3d[i] = |
| 1633 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]); |
| 1634 | } |
| 1635 | pi->sys_info.sclk_dpm_boost_margin = |
| 1636 | le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin); |
| 1637 | pi->sys_info.sclk_dpm_throttle_margin = |
| 1638 | le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin); |
| 1639 | pi->sys_info.sclk_dpm_tdp_limit_pg = |
| 1640 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG); |
| 1641 | pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit); |
| 1642 | pi->sys_info.sclk_dpm_tdp_limit_boost = |
| 1643 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost); |
| 1644 | pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock); |
| 1645 | pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit; |
| 1646 | if (igp_info->info_6.EnableBoost) |
| 1647 | pi->sys_info.enable_boost = true; |
| 1648 | else |
| 1649 | pi->sys_info.enable_boost = false; |
| 1650 | sumo_construct_display_voltage_mapping_table(rdev, |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1651 | &pi->sys_info.disp_clk_voltage_mapping_table, |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1652 | igp_info->info_6.sDISPCLK_Voltage); |
| 1653 | sumo_construct_sclk_voltage_mapping_table(rdev, |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1654 | &pi->sys_info.sclk_voltage_mapping_table, |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1655 | igp_info->info_6.sAvail_SCLK); |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 1656 | sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, |
| 1657 | igp_info->info_6.sAvail_SCLK); |
Alex Deucher | 80ea2c1 | 2013-04-12 14:56:21 -0400 | [diff] [blame] | 1658 | |
| 1659 | } |
| 1660 | return 0; |
| 1661 | } |
| 1662 | |
| 1663 | static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev) |
| 1664 | { |
| 1665 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1666 | |
| 1667 | pi->boot_pl.sclk = pi->sys_info.bootup_sclk; |
| 1668 | pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; |
| 1669 | pi->boot_pl.ds_divider_index = 0; |
| 1670 | pi->boot_pl.ss_divider_index = 0; |
| 1671 | pi->boot_pl.allow_gnb_slow = 1; |
| 1672 | pi->acpi_pl = pi->boot_pl; |
| 1673 | pi->current_ps.num_levels = 1; |
| 1674 | pi->current_ps.levels[0] = pi->boot_pl; |
| 1675 | } |
| 1676 | |
| 1677 | int sumo_dpm_init(struct radeon_device *rdev) |
| 1678 | { |
| 1679 | struct sumo_power_info *pi; |
| 1680 | u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; |
| 1681 | int ret; |
| 1682 | |
| 1683 | pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL); |
| 1684 | if (pi == NULL) |
| 1685 | return -ENOMEM; |
| 1686 | rdev->pm.dpm.priv = pi; |
| 1687 | |
| 1688 | pi->driver_nbps_policy_disable = false; |
| 1689 | if ((rdev->family == CHIP_PALM) && (hw_rev < 3)) |
| 1690 | pi->disable_gfx_power_gating_in_uvd = true; |
| 1691 | else |
| 1692 | pi->disable_gfx_power_gating_in_uvd = false; |
| 1693 | pi->enable_alt_vddnb = true; |
| 1694 | pi->enable_sclk_ds = true; |
| 1695 | pi->enable_dynamic_m3_arbiter = false; |
| 1696 | pi->enable_dynamic_patch_ps = true; |
| 1697 | pi->enable_gfx_power_gating = true; |
| 1698 | pi->enable_gfx_clock_gating = true; |
| 1699 | pi->enable_mg_clock_gating = true; |
| 1700 | pi->enable_auto_thermal_throttling = true; |
| 1701 | |
| 1702 | ret = sumo_parse_sys_info_table(rdev); |
| 1703 | if (ret) |
| 1704 | return ret; |
| 1705 | |
| 1706 | sumo_construct_boot_and_acpi_state(rdev); |
| 1707 | |
| 1708 | ret = sumo_parse_power_table(rdev); |
| 1709 | if (ret) |
| 1710 | return ret; |
| 1711 | |
| 1712 | pi->pasi = CYPRESS_HASI_DFLT; |
| 1713 | pi->asi = RV770_ASI_DFLT; |
| 1714 | pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; |
| 1715 | pi->enable_boost = pi->sys_info.enable_boost; |
| 1716 | pi->enable_dpm = true; |
| 1717 | |
| 1718 | return 0; |
| 1719 | } |
| 1720 | |
| 1721 | void sumo_dpm_print_power_state(struct radeon_device *rdev, |
| 1722 | struct radeon_ps *rps) |
| 1723 | { |
| 1724 | int i; |
| 1725 | struct sumo_ps *ps = sumo_get_ps(rps); |
| 1726 | |
| 1727 | r600_dpm_print_class_info(rps->class, rps->class2); |
| 1728 | r600_dpm_print_cap_info(rps->caps); |
| 1729 | printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); |
| 1730 | for (i = 0; i < ps->num_levels; i++) { |
| 1731 | struct sumo_pl *pl = &ps->levels[i]; |
| 1732 | printk("\t\tpower level %d sclk: %u vddc: %u\n", |
| 1733 | i, pl->sclk, |
| 1734 | sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); |
| 1735 | } |
| 1736 | r600_dpm_print_ps_status(rdev, rps); |
| 1737 | } |
| 1738 | |
| 1739 | void sumo_dpm_fini(struct radeon_device *rdev) |
| 1740 | { |
| 1741 | int i; |
| 1742 | |
| 1743 | sumo_cleanup_asic(rdev); /* ??? */ |
| 1744 | |
| 1745 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
| 1746 | kfree(rdev->pm.dpm.ps[i].ps_priv); |
| 1747 | } |
| 1748 | kfree(rdev->pm.dpm.ps); |
| 1749 | kfree(rdev->pm.dpm.priv); |
| 1750 | } |
| 1751 | |
| 1752 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low) |
| 1753 | { |
| 1754 | struct sumo_ps *requested_state = sumo_get_ps(rdev->pm.dpm.requested_ps); |
| 1755 | |
| 1756 | if (low) |
| 1757 | return requested_state->levels[0].sclk; |
| 1758 | else |
| 1759 | return requested_state->levels[requested_state->num_levels - 1].sclk; |
| 1760 | } |
| 1761 | |
| 1762 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low) |
| 1763 | { |
| 1764 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
| 1765 | |
| 1766 | return pi->sys_info.bootup_uma_clk; |
| 1767 | } |