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Dhaval Patel6a5bd8b2016-10-10 14:12:10 -07001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -080013#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dualmipi-video.dtsi"
16#include "dsi-panel-sim-dualmipi-cmd.dtsi"
17#include "dsi-panel-sharp-dsc-4k-video.dtsi"
18#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
23#include "dsi-panel-sharp-1080p-cmd.dtsi"
24#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
25#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi"
Shashank Babu Chinta Venkata59e305f2017-04-05 12:14:18 -070026#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -080027
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -070028&soc {
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -080029 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 qcom,panel-supply-entry@0 {
34 reg = <0>;
35 qcom,supply-name = "vddio";
36 qcom,supply-min-voltage = <1800000>;
37 qcom,supply-max-voltage = <1800000>;
38 qcom,supply-enable-load = <62000>;
39 qcom,supply-disable-load = <80>;
40 qcom,supply-post-on-sleep = <20>;
41 };
42
43 qcom,panel-supply-entry@1 {
44 reg = <1>;
45 qcom,supply-name = "lab";
46 qcom,supply-min-voltage = <4600000>;
47 qcom,supply-max-voltage = <6000000>;
48 qcom,supply-enable-load = <100000>;
49 qcom,supply-disable-load = <100>;
50 };
51
52 qcom,panel-supply-entry@2 {
53 reg = <2>;
54 qcom,supply-name = "ibb";
55 qcom,supply-min-voltage = <4600000>;
56 qcom,supply-max-voltage = <6000000>;
57 qcom,supply-enable-load = <100000>;
58 qcom,supply-disable-load = <100>;
59 qcom,supply-post-on-sleep = <20>;
60 };
61 };
62
63 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 qcom,panel-supply-entry@0 {
68 reg = <0>;
69 qcom,supply-name = "vddio";
70 qcom,supply-min-voltage = <1800000>;
71 qcom,supply-max-voltage = <1800000>;
72 qcom,supply-enable-load = <62000>;
73 qcom,supply-disable-load = <80>;
74 qcom,supply-post-on-sleep = <20>;
75 };
76 };
77
78 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 qcom,panel-supply-entry@0 {
83 reg = <0>;
84 qcom,supply-name = "vddio";
85 qcom,supply-min-voltage = <1800000>;
86 qcom,supply-max-voltage = <1800000>;
87 qcom,supply-enable-load = <62000>;
88 qcom,supply-disable-load = <80>;
89 qcom,supply-post-on-sleep = <20>;
90 };
91
92 qcom,panel-supply-entry@1 {
93 reg = <1>;
94 qcom,supply-name = "vdd";
95 qcom,supply-min-voltage = <3000000>;
96 qcom,supply-max-voltage = <3000000>;
97 qcom,supply-enable-load = <857000>;
98 qcom,supply-disable-load = <0>;
99 qcom,supply-post-on-sleep = <0>;
100 };
101 };
102
103 dsi_sharp_4k_dsc_video_display: qcom,dsi-display@0 {
104 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700105 label = "dsi_sharp_4k_dsc_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800106 qcom,display-type = "primary";
107
108 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
109 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkatadb329392017-04-28 15:45:44 -0700110 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
111 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800112 clock-names = "src_byte_clk", "src_pixel_clk";
113
114 pinctrl-names = "panel_active", "panel_suspend";
115 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
116 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
117 qcom,platform-te-gpio = <&tlmm 10 0>;
118 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700119 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800120
121 qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>;
122 vddio-supply = <&pm8998_l14>;
123 lab-supply = <&lab_regulator>;
124 ibb-supply = <&ibb_regulator>;
125 };
126
127 dsi_sharp_4k_dsc_cmd_display: qcom,dsi-display@1 {
128 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700129 label = "dsi_sharp_4k_dsc_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800130 qcom,display-type = "primary";
131
132 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
133 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkatadb329392017-04-28 15:45:44 -0700134 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
135 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800136 clock-names = "src_byte_clk", "src_pixel_clk";
137
138 pinctrl-names = "panel_active", "panel_suspend";
139 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
140 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
141 qcom,platform-te-gpio = <&tlmm 10 0>;
142 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700143 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800144
145 qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>;
146 vddio-supply = <&pm8998_l14>;
147 lab-supply = <&lab_regulator>;
148 ibb-supply = <&ibb_regulator>;
149 };
150
151 dsi_sharp_1080_cmd_display: qcom,dsi-display@2 {
152 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700153 label = "dsi_sharp_1080_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800154 qcom,display-type = "primary";
155
156 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
157 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkatadb329392017-04-28 15:45:44 -0700158 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
159 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800160 clock-names = "src_byte_clk", "src_pixel_clk";
161
162 pinctrl-names = "panel_active", "panel_suspend";
163 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
164 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
165 qcom,platform-te-gpio = <&tlmm 10 0>;
166 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700167 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800168
169 qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
170 vddio-supply = <&pm8998_l14>;
171 lab-supply = <&lab_regulator>;
172 ibb-supply = <&ibb_regulator>;
173 };
174
175 dsi_dual_sharp_1080_120hz_cmd_display: qcom,dsi-display@3 {
176 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700177 label = "dsi_dual_sharp_1080_120hz_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800178 qcom,display-type = "primary";
179
180 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
181 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkatadb329392017-04-28 15:45:44 -0700182 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
183 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800184 clock-names = "src_byte_clk", "src_pixel_clk";
185
186 pinctrl-names = "panel_active", "panel_suspend";
187 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
188 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
189 qcom,platform-te-gpio = <&tlmm 10 0>;
190 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700191 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800192
193 qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>;
194 vddio-supply = <&pm8998_l14>;
195 lab-supply = <&lab_regulator>;
196 ibb-supply = <&ibb_regulator>;
197 };
198
199 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 {
200 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700201 label = "dsi_dual_nt35597_truly_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800202 qcom,display-type = "primary";
203
204 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
205 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkata59e305f2017-04-05 12:14:18 -0700206 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
207 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800208 clock-names = "src_byte_clk", "src_pixel_clk";
209
210 pinctrl-names = "panel_active", "panel_suspend";
211 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
212 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800213 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata59e305f2017-04-05 12:14:18 -0700214 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800215
216 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
217 vddio-supply = <&pm8998_l14>;
218 lab-supply = <&lab_regulator>;
219 ibb-supply = <&ibb_regulator>;
220 };
221
222 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 {
223 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700224 label = "dsi_dual_nt35597_truly_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800225 qcom,display-type = "primary";
226
227 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
228 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
Shashank Babu Chinta Venkatadb329392017-04-28 15:45:44 -0700229 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
230 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800231 clock-names = "src_byte_clk", "src_pixel_clk";
232
233 pinctrl-names = "panel_active", "panel_suspend";
234 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
235 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
236 qcom,platform-te-gpio = <&tlmm 10 0>;
237 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700238 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800239
240 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
241 vddio-supply = <&pm8998_l14>;
242 lab-supply = <&lab_regulator>;
243 ibb-supply = <&ibb_regulator>;
244 };
245
246 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@6 {
247 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700248 label = "dsi_nt35597_truly_dsc_cmd_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800249 qcom,display-type = "primary";
250
Vara Reddy199c2822017-05-19 10:14:44 -0700251 qcom,dsi-ctrl = <&mdss_dsi1>;
252 qcom,dsi-phy = <&mdss_dsi_phy1>;
253 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
254 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800255 clock-names = "src_byte_clk", "src_pixel_clk";
256
257 pinctrl-names = "panel_active", "panel_suspend";
258 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
259 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
260 qcom,platform-te-gpio = <&tlmm 10 0>;
261 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700262 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800263
264 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
265 vddio-supply = <&pm8998_l14>;
266 lab-supply = <&lab_regulator>;
267 ibb-supply = <&ibb_regulator>;
268 };
269
270 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@7 {
271 compatible = "qcom,dsi-display";
Shashank Babu Chinta Venkata5f3ddcd22017-03-29 14:27:21 -0700272 label = "dsi_nt35597_truly_dsc_video_display";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800273 qcom,display-type = "primary";
274
Vara Reddy199c2822017-05-19 10:14:44 -0700275 qcom,dsi-ctrl = <&mdss_dsi1>;
276 qcom,dsi-phy = <&mdss_dsi_phy1>;
277 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
278 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800279 clock-names = "src_byte_clk", "src_pixel_clk";
280
281 pinctrl-names = "panel_active", "panel_suspend";
282 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
283 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
284 qcom,platform-te-gpio = <&tlmm 10 0>;
285 qcom,platform-reset-gpio = <&tlmm 6 0>;
Shashank Babu Chinta Venkata13a41d42017-04-28 15:51:35 -0700286 qcom,panel-mode-gpio = <&tlmm 52 0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800287
288 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
289 vddio-supply = <&pm8998_l14>;
290 lab-supply = <&lab_regulator>;
291 ibb-supply = <&ibb_regulator>;
292 };
293
Narendra Muppallae8c25c82017-04-02 19:20:57 -0700294 dsi_sim_vid_display: qcom,dsi-display@8 {
295 compatible = "qcom,dsi-display";
296 label = "dsi_sim_vid_display";
297 qcom,display-type = "primary";
298
299 qcom,dsi-ctrl = <&mdss_dsi0>;
300 qcom,dsi-phy = <&mdss_dsi_phy0>;
301 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
302 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
303 clock-names = "src_byte_clk", "src_pixel_clk";
304
305 pinctrl-names = "panel_active", "panel_suspend";
306 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
307 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
308
309 qcom,dsi-panel = <&dsi_sim_vid>;
310 };
311
312 dsi_dual_sim_vid_display: qcom,dsi-display@9 {
313 compatible = "qcom,dsi-display";
314 label = "dsi_dual_sim_vid_display";
315 qcom,display-type = "primary";
316
317 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
318 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
319 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
320 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
321 clock-names = "src_byte_clk", "src_pixel_clk";
322
323 pinctrl-names = "panel_active", "panel_suspend";
324 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
325 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
326
327 qcom,dsi-panel = <&dsi_dual_sim_vid>;
328 };
329
Narendra Muppallaa1a55462017-04-04 18:07:27 -0700330 dsi_sim_cmd_display: qcom,dsi-display@10 {
331 compatible = "qcom,dsi-display";
332 label = "dsi_sim_cmd_display";
333 qcom,display-type = "primary";
334
335 qcom,dsi-ctrl = <&mdss_dsi0>;
336 qcom,dsi-phy = <&mdss_dsi_phy0>;
337 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
338 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
339 clock-names = "src_byte_clk", "src_pixel_clk";
340
341 pinctrl-names = "panel_active", "panel_suspend";
342 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
343 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
344
345 qcom,dsi-panel = <&dsi_sim_cmd>;
346 };
347
348 dsi_dual_sim_cmd_display: qcom,dsi-display@11 {
349 compatible = "qcom,dsi-display";
350 label = "dsi_dual_sim_cmd_display";
351 qcom,display-type = "primary";
352
353 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
354 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
355 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
356 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
357 clock-names = "src_byte_clk", "src_pixel_clk";
358
359 pinctrl-names = "panel_active", "panel_suspend";
360 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
361 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
362
363 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
364 };
365
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700366 sde_wb: qcom,wb-display@0 {
367 compatible = "qcom,wb-display";
368 cell-index = <0>;
369 label = "wb_display";
370 };
Padmanabhan Komanduruff557602017-05-01 13:39:26 -0700371
372 sde_dp: qcom,dp_display@0{
373 cell-index = <0>;
374 compatible = "qcom,dp-display";
375
376 gdsc-supply = <&mdss_core_gdsc>;
377 vdda-1p2-supply = <&pm8998_l26>;
378 vdda-0p9-supply = <&pm8998_l1>;
379
380 reg = <0xae90000 0xa84>,
381 <0x88eaa00 0x200>,
382 <0x88ea200 0x200>,
383 <0x88ea600 0x200>,
384 <0xaf02000 0x1a0>,
385 <0x780000 0x621c>,
386 <0x88ea030 0x10>,
387 <0x0aee1000 0x034>;
388 reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
389 "dp_mmss_cc", "qfprom_physical", "dp_pll",
390 "hdcp_physical";
391
392 interrupt-parent = <&mdss_mdp>;
393 interrupts = <12 0>;
394
395 clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
396 <&clock_rpmh RPMH_CXO_CLK>,
397 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
398 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
399 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
400 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
401 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
402 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
403 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
404 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
405 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
406 clock-names = "core_aux_clk", "core_usb_ref_clk_src",
407 "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
408 "core_usb_pipe_clk", "ctrl_link_clk",
409 "ctrl_link_iface_clk", "ctrl_crypto_clk",
410 "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";
411
412 qcom,dp-usbpd-detection = <&pmi8998_pdphy>;
413
414 qcom,aux-cfg-settings = [00 13 04 00 0a 26 0a 03 bb 03];
415
416 qcom,core-supply-entries {
417 #address-cells = <1>;
418 #size-cells = <0>;
419
420 qcom,core-supply-entry@0 {
421 reg = <0>;
422 qcom,supply-name = "gdsc";
423 qcom,supply-min-voltage = <0>;
424 qcom,supply-max-voltage = <0>;
425 qcom,supply-enable-load = <0>;
426 qcom,supply-disable-load = <0>;
427 };
428 };
429
430 qcom,ctrl-supply-entries {
431 #address-cells = <1>;
432 #size-cells = <0>;
433
434 qcom,ctrl-supply-entry@0 {
435 reg = <0>;
436 qcom,supply-name = "vdda-1p2";
437 qcom,supply-min-voltage = <1200000>;
438 qcom,supply-max-voltage = <1200000>;
439 qcom,supply-enable-load = <21800>;
440 qcom,supply-disable-load = <4>;
441 };
442 };
443
444 qcom,phy-supply-entries {
445 #address-cells = <1>;
446 #size-cells = <0>;
447
448 qcom,phy-supply-entry@0 {
449 reg = <0>;
450 qcom,supply-name = "vdda-0p9";
451 qcom,supply-min-voltage = <880000>;
452 qcom,supply-max-voltage = <880000>;
453 qcom,supply-enable-load = <36000>;
454 qcom,supply-disable-load = <32>;
455 };
456 };
457 };
458};
459
460&sde_dp {
461 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
462 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
463 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
464 qcom,aux-en-gpio = <&tlmm 43 0>;
465 qcom,aux-sel-gpio = <&tlmm 51 0>;
466 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700467};
468
469&mdss_mdp {
Padmanabhan Komanduruff557602017-05-01 13:39:26 -0700470 connectors = <&sde_rscc &sde_wb &sde_dp>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700471};
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700472
473&dsi_dual_nt35597_truly_video {
Shashank Babu Chinta Venkata690e6a02017-05-02 10:58:01 -0700474 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700475 qcom,mdss-dsi-t-clk-post = <0x0D>;
476 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700477 qcom,display-topology = <2 0 2>,
478 <1 0 2>;
479 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700480};
481
482&dsi_dual_nt35597_truly_cmd {
Shashank Babu Chinta Venkata690e6a02017-05-02 10:58:01 -0700483 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700484 qcom,mdss-dsi-t-clk-post = <0x0D>;
485 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700486 qcom,display-topology = <2 0 2>,
487 <1 0 2>;
488 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700489};
490
491&dsi_nt35597_truly_dsc_cmd {
Shashank Babu Chinta Venkata690e6a02017-05-02 10:58:01 -0700492 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700493 qcom,mdss-dsi-t-clk-post = <0x0b>;
494 qcom,mdss-dsi-t-clk-pre = <0x23>;
Vara Reddy199c2822017-05-19 10:14:44 -0700495 qcom,display-topology = <1 1 1>,
496 <2 2 1>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700497 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700498};
499
500&dsi_nt35597_truly_dsc_video {
Shashank Babu Chinta Venkata690e6a02017-05-02 10:58:01 -0700501 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700502 qcom,mdss-dsi-t-clk-post = <0x0b>;
503 qcom,mdss-dsi-t-clk-pre = <0x23>;
Vara Reddy199c2822017-05-19 10:14:44 -0700504 qcom,display-topology = <1 1 1>,
505 <2 2 1>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700506 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700507};
508
509&dsi_sharp_4k_dsc_video {
Shashank Babu Chinta Venkata29c856f2017-05-02 11:03:50 -0700510 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 06 04 03 04 00];
511 qcom,mdss-dsi-t-clk-post = <0x0c>;
512 qcom,mdss-dsi-t-clk-pre = <0x27>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700513 qcom,display-topology = <2 2 2>;
514 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700515};
516
517&dsi_sharp_4k_dsc_cmd {
Shashank Babu Chinta Venkata29c856f2017-05-02 11:03:50 -0700518 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 06 04 03 04 00];
519 qcom,mdss-dsi-t-clk-post = <0x0c>;
520 qcom,mdss-dsi-t-clk-pre = <0x27>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700521 qcom,display-topology = <2 2 2>;
522 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700523};
524
525&dsi_dual_sharp_1080_120hz_cmd {
Shashank Babu Chinta Venkata690e6a02017-05-02 10:58:01 -0700526 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 09 06 03 04 00];
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700527 qcom,mdss-dsi-t-clk-post = <0x0f>;
528 qcom,mdss-dsi-t-clk-pre = <0x36>;
Jeykumar Sankaranbfe3ed12017-04-24 18:53:54 -0700529 qcom,display-topology = <2 0 2>,
530 <1 0 2>;
531 qcom,default-topology-index = <0>;
532};
533
534&dsi_sharp_1080_cmd {
535 qcom,display-topology = <2 0 2>,
536 <1 0 2>;
537 qcom,default-topology-index = <0>;
Shashank Babu Chinta Venkata939a3a42017-03-30 13:00:25 -0700538};
Narendra Muppallae8c25c82017-04-02 19:20:57 -0700539
540&dsi_sim_vid {
541 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
542 qcom,mdss-dsi-t-clk-post = <0x0d>;
543 qcom,mdss-dsi-t-clk-pre = <0x2d>;
544};
545
546&dsi_dual_sim_vid {
547 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
548 qcom,mdss-dsi-t-clk-post = <0x0d>;
549 qcom,mdss-dsi-t-clk-pre = <0x2d>;
550};
Narendra Muppallaa1a55462017-04-04 18:07:27 -0700551
552&dsi_sim_cmd {
553 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
554 qcom,mdss-dsi-t-clk-post = <0x0d>;
555 qcom,mdss-dsi-t-clk-pre = <0x2d>;
556};
557
558&dsi_dual_sim_cmd {
559 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
560 qcom,mdss-dsi-t-clk-post = <0x0d>;
561 qcom,mdss-dsi-t-clk-pre = <0x2d>;
562};