Yinghai Lu | 5aeecaf | 2008-08-19 20:49:59 -0700 | [diff] [blame] | 1 | #include <linux/interrupt.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 2 | #include <linux/dmar.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3 | #include <linux/spinlock.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 4 | #include <linux/slab.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 5 | #include <linux/jiffies.h> |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 6 | #include <linux/hpet.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 7 | #include <linux/pci.h> |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 8 | #include <linux/irq.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 9 | #include <asm/io_apic.h> |
Yinghai Lu | 17483a1 | 2008-12-12 13:14:18 -0800 | [diff] [blame] | 10 | #include <asm/smp.h> |
Jaswinder Singh Rajput | 6d652ea | 2009-01-07 21:38:59 +0530 | [diff] [blame] | 11 | #include <asm/cpu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 12 | #include <linux/intel-iommu.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 13 | #include "intr_remapping.h" |
Alexander Beregalov | 46f06b72 | 2009-04-06 16:45:28 +0100 | [diff] [blame] | 14 | #include <acpi/acpi.h> |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 15 | #include <asm/pci-direct.h> |
| 16 | #include "pci.h" |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 17 | |
| 18 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 19 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
| 20 | static int ir_ioapic_num, ir_hpet_num; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 21 | int intr_remapping_enabled; |
| 22 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 23 | static int disable_intremap; |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 24 | static int disable_sourceid_checking; |
| 25 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 26 | static __init int setup_nointremap(char *str) |
| 27 | { |
| 28 | disable_intremap = 1; |
| 29 | return 0; |
| 30 | } |
| 31 | early_param("nointremap", setup_nointremap); |
| 32 | |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 33 | static __init int setup_intremap(char *str) |
| 34 | { |
| 35 | if (!str) |
| 36 | return -EINVAL; |
| 37 | |
| 38 | if (!strncmp(str, "on", 2)) |
| 39 | disable_intremap = 0; |
| 40 | else if (!strncmp(str, "off", 3)) |
| 41 | disable_intremap = 1; |
| 42 | else if (!strncmp(str, "nosid", 5)) |
| 43 | disable_sourceid_checking = 1; |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | early_param("intremap", setup_intremap); |
| 48 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 49 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
| 50 | { |
Thomas Gleixner | 349d676 | 2010-10-10 12:29:27 +0200 | [diff] [blame^] | 51 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
| 52 | return cfg ? &cfg->irq_2_iommu : NULL; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 53 | } |
| 54 | |
Yinghai Lu | 70590ea | 2009-08-26 16:21:54 -0700 | [diff] [blame] | 55 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 56 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 57 | return irq_2_iommu(irq); |
| 58 | } |
Thomas Gleixner | 0e1e367 | 2010-10-04 16:20:16 +0200 | [diff] [blame] | 59 | |
Thomas Gleixner | 349d676 | 2010-10-10 12:29:27 +0200 | [diff] [blame^] | 60 | static void irq_2_iommu_free(unsigned int irq) |
| 61 | { |
| 62 | } |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 63 | |
| 64 | static DEFINE_SPINLOCK(irq_2_ir_lock); |
| 65 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 66 | static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq) |
| 67 | { |
| 68 | struct irq_2_iommu *irq_iommu; |
| 69 | |
| 70 | irq_iommu = irq_2_iommu(irq); |
| 71 | |
| 72 | if (!irq_iommu) |
| 73 | return NULL; |
| 74 | |
| 75 | if (!irq_iommu->iommu) |
| 76 | return NULL; |
| 77 | |
| 78 | return irq_iommu; |
| 79 | } |
| 80 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 81 | int irq_remapped(int irq) |
| 82 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 83 | return valid_irq_2_iommu(irq) != NULL; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | int get_irte(int irq, struct irte *entry) |
| 87 | { |
| 88 | int index; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 89 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 90 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 91 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 92 | if (!entry) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 93 | return -1; |
| 94 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 95 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 96 | irq_iommu = valid_irq_2_iommu(irq); |
| 97 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 98 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 99 | return -1; |
| 100 | } |
| 101 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 102 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 103 | *entry = *(irq_iommu->iommu->ir_table->base + index); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 104 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 105 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
| 110 | { |
| 111 | struct ir_table *table = iommu->ir_table; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 112 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 113 | u16 index, start_index; |
| 114 | unsigned int mask = 0; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 115 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 116 | int i; |
| 117 | |
| 118 | if (!count) |
| 119 | return -1; |
| 120 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 121 | #ifndef CONFIG_SPARSE_IRQ |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 122 | /* protect irq_2_iommu_alloc later */ |
| 123 | if (irq >= nr_irqs) |
| 124 | return -1; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 125 | #endif |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 126 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 127 | /* |
| 128 | * start the IRTE search from index 0. |
| 129 | */ |
| 130 | index = start_index = 0; |
| 131 | |
| 132 | if (count > 1) { |
| 133 | count = __roundup_pow_of_two(count); |
| 134 | mask = ilog2(count); |
| 135 | } |
| 136 | |
| 137 | if (mask > ecap_max_handle_mask(iommu->ecap)) { |
| 138 | printk(KERN_ERR |
| 139 | "Requested mask %x exceeds the max invalidation handle" |
| 140 | " mask value %Lx\n", mask, |
| 141 | ecap_max_handle_mask(iommu->ecap)); |
| 142 | return -1; |
| 143 | } |
| 144 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 145 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 146 | do { |
| 147 | for (i = index; i < index + count; i++) |
| 148 | if (table->base[i].present) |
| 149 | break; |
| 150 | /* empty index found */ |
| 151 | if (i == index + count) |
| 152 | break; |
| 153 | |
| 154 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; |
| 155 | |
| 156 | if (index == start_index) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 157 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 158 | printk(KERN_ERR "can't allocate an IRTE\n"); |
| 159 | return -1; |
| 160 | } |
| 161 | } while (1); |
| 162 | |
| 163 | for (i = index; i < index + count; i++) |
| 164 | table->base[i].present = 1; |
| 165 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 166 | irq_iommu = irq_2_iommu_alloc(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 167 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 168 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 169 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
| 170 | return -1; |
| 171 | } |
| 172 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 173 | irq_iommu->iommu = iommu; |
| 174 | irq_iommu->irte_index = index; |
| 175 | irq_iommu->sub_handle = 0; |
| 176 | irq_iommu->irte_mask = mask; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 177 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 178 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 179 | |
| 180 | return index; |
| 181 | } |
| 182 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 183 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 184 | { |
| 185 | struct qi_desc desc; |
| 186 | |
| 187 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) |
| 188 | | QI_IEC_SELECTIVE; |
| 189 | desc.high = 0; |
| 190 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 191 | return qi_submit_sync(&desc, iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
| 195 | { |
| 196 | int index; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 197 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 198 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 199 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 200 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 201 | irq_iommu = valid_irq_2_iommu(irq); |
| 202 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 203 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 204 | return -1; |
| 205 | } |
| 206 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 207 | *sub_handle = irq_iommu->sub_handle; |
| 208 | index = irq_iommu->irte_index; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 209 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 210 | return index; |
| 211 | } |
| 212 | |
| 213 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
| 214 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 215 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 216 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 217 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 218 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | 7ddfb65 | 2008-08-20 17:22:51 -0700 | [diff] [blame] | 219 | |
| 220 | irq_iommu = irq_2_iommu_alloc(irq); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 221 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 222 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 223 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 224 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
| 225 | return -1; |
| 226 | } |
| 227 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 228 | irq_iommu->iommu = iommu; |
| 229 | irq_iommu->irte_index = index; |
| 230 | irq_iommu->sub_handle = subhandle; |
| 231 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 232 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 233 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 238 | int modify_irte(int irq, struct irte *irte_modified) |
| 239 | { |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 240 | int rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 241 | int index; |
| 242 | struct irte *irte; |
| 243 | struct intel_iommu *iommu; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 244 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 245 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 246 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 247 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 248 | irq_iommu = valid_irq_2_iommu(irq); |
| 249 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 250 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 251 | return -1; |
| 252 | } |
| 253 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 254 | iommu = irq_iommu->iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 255 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 256 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 257 | irte = &iommu->ir_table->base[index]; |
| 258 | |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 259 | set_64bit(&irte->low, irte_modified->low); |
| 260 | set_64bit(&irte->high, irte_modified->high); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 261 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
| 262 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 263 | rc = qi_flush_iec(iommu, index, 0); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 264 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 265 | |
| 266 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 267 | } |
| 268 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 269 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
| 270 | { |
| 271 | int i; |
| 272 | |
| 273 | for (i = 0; i < MAX_HPET_TBS; i++) |
| 274 | if (ir_hpet[i].id == hpet_id) |
| 275 | return ir_hpet[i].iommu; |
| 276 | return NULL; |
| 277 | } |
| 278 | |
Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 279 | struct intel_iommu *map_ioapic_to_ir(int apic) |
| 280 | { |
| 281 | int i; |
| 282 | |
| 283 | for (i = 0; i < MAX_IO_APICS; i++) |
| 284 | if (ir_ioapic[i].id == apic) |
| 285 | return ir_ioapic[i].iommu; |
| 286 | return NULL; |
| 287 | } |
| 288 | |
Suresh Siddha | 75c46fa | 2008-07-10 11:16:57 -0700 | [diff] [blame] | 289 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
| 290 | { |
| 291 | struct dmar_drhd_unit *drhd; |
| 292 | |
| 293 | drhd = dmar_find_matched_drhd_unit(dev); |
| 294 | if (!drhd) |
| 295 | return NULL; |
| 296 | |
| 297 | return drhd->iommu; |
| 298 | } |
| 299 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 300 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
| 301 | { |
| 302 | struct irte *start, *entry, *end; |
| 303 | struct intel_iommu *iommu; |
| 304 | int index; |
| 305 | |
| 306 | if (irq_iommu->sub_handle) |
| 307 | return 0; |
| 308 | |
| 309 | iommu = irq_iommu->iommu; |
| 310 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 311 | |
| 312 | start = iommu->ir_table->base + index; |
| 313 | end = start + (1 << irq_iommu->irte_mask); |
| 314 | |
| 315 | for (entry = start; entry < end; entry++) { |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 316 | set_64bit(&entry->low, 0); |
| 317 | set_64bit(&entry->high, 0); |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
| 321 | } |
| 322 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 323 | int free_irte(int irq) |
| 324 | { |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 325 | int rc = 0; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 326 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 327 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 328 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 329 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 330 | irq_iommu = valid_irq_2_iommu(irq); |
| 331 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 332 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 333 | return -1; |
| 334 | } |
| 335 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 336 | rc = clear_entries(irq_iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 337 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 338 | irq_iommu->iommu = NULL; |
| 339 | irq_iommu->irte_index = 0; |
| 340 | irq_iommu->sub_handle = 0; |
| 341 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 342 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 343 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 344 | |
Thomas Gleixner | 0e1e367 | 2010-10-04 16:20:16 +0200 | [diff] [blame] | 345 | irq_2_iommu_free(irq); |
| 346 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 347 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 348 | } |
| 349 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 350 | /* |
| 351 | * source validation type |
| 352 | */ |
| 353 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ |
| 354 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */ |
| 355 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
| 356 | |
| 357 | /* |
| 358 | * source-id qualifier |
| 359 | */ |
| 360 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ |
| 361 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore |
| 362 | * the third least significant bit |
| 363 | */ |
| 364 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore |
| 365 | * the second and third least significant bits |
| 366 | */ |
| 367 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore |
| 368 | * the least three significant bits |
| 369 | */ |
| 370 | |
| 371 | /* |
| 372 | * set SVT, SQ and SID fields of irte to verify |
| 373 | * source ids of interrupt requests |
| 374 | */ |
| 375 | static void set_irte_sid(struct irte *irte, unsigned int svt, |
| 376 | unsigned int sq, unsigned int sid) |
| 377 | { |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 378 | if (disable_sourceid_checking) |
| 379 | svt = SVT_NO_VERIFY; |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 380 | irte->svt = svt; |
| 381 | irte->sq = sq; |
| 382 | irte->sid = sid; |
| 383 | } |
| 384 | |
| 385 | int set_ioapic_sid(struct irte *irte, int apic) |
| 386 | { |
| 387 | int i; |
| 388 | u16 sid = 0; |
| 389 | |
| 390 | if (!irte) |
| 391 | return -1; |
| 392 | |
| 393 | for (i = 0; i < MAX_IO_APICS; i++) { |
| 394 | if (ir_ioapic[i].id == apic) { |
| 395 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
| 396 | break; |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | if (sid == 0) { |
| 401 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); |
| 402 | return -1; |
| 403 | } |
| 404 | |
| 405 | set_irte_sid(irte, 1, 0, sid); |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 410 | int set_hpet_sid(struct irte *irte, u8 id) |
| 411 | { |
| 412 | int i; |
| 413 | u16 sid = 0; |
| 414 | |
| 415 | if (!irte) |
| 416 | return -1; |
| 417 | |
| 418 | for (i = 0; i < MAX_HPET_TBS; i++) { |
| 419 | if (ir_hpet[i].id == id) { |
| 420 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
| 421 | break; |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | if (sid == 0) { |
| 426 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); |
| 427 | return -1; |
| 428 | } |
| 429 | |
| 430 | /* |
| 431 | * Should really use SQ_ALL_16. Some platforms are broken. |
| 432 | * While we figure out the right quirks for these broken platforms, use |
| 433 | * SQ_13_IGNORE_3 for now. |
| 434 | */ |
| 435 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 440 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
| 441 | { |
| 442 | struct pci_dev *bridge; |
| 443 | |
| 444 | if (!irte || !dev) |
| 445 | return -1; |
| 446 | |
| 447 | /* PCIe device or Root Complex integrated PCI device */ |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 448 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 449 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 450 | (dev->bus->number << 8) | dev->devfn); |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | bridge = pci_find_upstream_pcie_bridge(dev); |
| 455 | if (bridge) { |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 456 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 457 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
| 458 | (bridge->bus->number << 8) | dev->bus->number); |
| 459 | else /* this is a legacy PCI bridge */ |
| 460 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 461 | (bridge->bus->number << 8) | bridge->devfn); |
| 462 | } |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 467 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
| 468 | { |
| 469 | u64 addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 470 | u32 sts; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 471 | unsigned long flags; |
| 472 | |
| 473 | addr = virt_to_phys((void *)iommu->ir_table->base); |
| 474 | |
| 475 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 476 | |
| 477 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, |
| 478 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); |
| 479 | |
| 480 | /* Set interrupt-remapping table pointer */ |
Han, Weidong | 161fde0 | 2009-04-03 17:15:47 +0800 | [diff] [blame] | 481 | iommu->gcmd |= DMA_GCMD_SIRTP; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 482 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 483 | |
| 484 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 485 | readl, (sts & DMA_GSTS_IRTPS), sts); |
| 486 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 487 | |
| 488 | /* |
| 489 | * global invalidation of interrupt entry cache before enabling |
| 490 | * interrupt-remapping. |
| 491 | */ |
| 492 | qi_global_iec(iommu); |
| 493 | |
| 494 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 495 | |
| 496 | /* Enable interrupt-remapping */ |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 497 | iommu->gcmd |= DMA_GCMD_IRE; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 498 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 499 | |
| 500 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 501 | readl, (sts & DMA_GSTS_IRES), sts); |
| 502 | |
| 503 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 504 | } |
| 505 | |
| 506 | |
| 507 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) |
| 508 | { |
| 509 | struct ir_table *ir_table; |
| 510 | struct page *pages; |
| 511 | |
| 512 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), |
Suresh Siddha | fa4b57c | 2009-03-16 17:05:05 -0700 | [diff] [blame] | 513 | GFP_ATOMIC); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 514 | |
| 515 | if (!iommu->ir_table) |
| 516 | return -ENOMEM; |
| 517 | |
Suresh Siddha | 824cd75 | 2009-10-02 11:01:23 -0700 | [diff] [blame] | 518 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
| 519 | INTR_REMAP_PAGE_ORDER); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 520 | |
| 521 | if (!pages) { |
| 522 | printk(KERN_ERR "failed to allocate pages of order %d\n", |
| 523 | INTR_REMAP_PAGE_ORDER); |
| 524 | kfree(iommu->ir_table); |
| 525 | return -ENOMEM; |
| 526 | } |
| 527 | |
| 528 | ir_table->base = page_address(pages); |
| 529 | |
| 530 | iommu_set_intr_remapping(iommu, mode); |
| 531 | return 0; |
| 532 | } |
| 533 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 534 | /* |
| 535 | * Disable Interrupt Remapping. |
| 536 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 537 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 538 | { |
| 539 | unsigned long flags; |
| 540 | u32 sts; |
| 541 | |
| 542 | if (!ecap_ir_support(iommu->ecap)) |
| 543 | return; |
| 544 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 545 | /* |
| 546 | * global invalidation of interrupt entry cache before disabling |
| 547 | * interrupt-remapping. |
| 548 | */ |
| 549 | qi_global_iec(iommu); |
| 550 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 551 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 552 | |
| 553 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); |
| 554 | if (!(sts & DMA_GSTS_IRES)) |
| 555 | goto end; |
| 556 | |
| 557 | iommu->gcmd &= ~DMA_GCMD_IRE; |
| 558 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 559 | |
| 560 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 561 | readl, !(sts & DMA_GSTS_IRES), sts); |
| 562 | |
| 563 | end: |
| 564 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 565 | } |
| 566 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 567 | int __init intr_remapping_supported(void) |
| 568 | { |
| 569 | struct dmar_drhd_unit *drhd; |
| 570 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 571 | if (disable_intremap) |
| 572 | return 0; |
| 573 | |
Youquan Song | 074835f | 2009-09-09 12:05:39 -0400 | [diff] [blame] | 574 | if (!dmar_ir_support()) |
| 575 | return 0; |
| 576 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 577 | for_each_drhd_unit(drhd) { |
| 578 | struct intel_iommu *iommu = drhd->iommu; |
| 579 | |
| 580 | if (!ecap_ir_support(iommu->ecap)) |
| 581 | return 0; |
| 582 | } |
| 583 | |
| 584 | return 1; |
| 585 | } |
| 586 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 587 | int __init enable_intr_remapping(int eim) |
| 588 | { |
| 589 | struct dmar_drhd_unit *drhd; |
| 590 | int setup = 0; |
| 591 | |
Youquan Song | e936d07 | 2009-09-07 10:58:07 -0400 | [diff] [blame] | 592 | if (parse_ioapics_under_ir() != 1) { |
| 593 | printk(KERN_INFO "Not enable interrupt remapping\n"); |
| 594 | return -1; |
| 595 | } |
| 596 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 597 | for_each_drhd_unit(drhd) { |
| 598 | struct intel_iommu *iommu = drhd->iommu; |
| 599 | |
| 600 | /* |
Han, Weidong | 34aaaa9 | 2009-04-04 17:21:26 +0800 | [diff] [blame] | 601 | * If the queued invalidation is already initialized, |
| 602 | * shouldn't disable it. |
| 603 | */ |
| 604 | if (iommu->qi) |
| 605 | continue; |
| 606 | |
| 607 | /* |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 608 | * Clear previous faults. |
| 609 | */ |
| 610 | dmar_fault(-1, iommu); |
| 611 | |
| 612 | /* |
| 613 | * Disable intr remapping and queued invalidation, if already |
| 614 | * enabled prior to OS handover. |
| 615 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 616 | iommu_disable_intr_remapping(iommu); |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 617 | |
| 618 | dmar_disable_qi(iommu); |
| 619 | } |
| 620 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 621 | /* |
| 622 | * check for the Interrupt-remapping support |
| 623 | */ |
| 624 | for_each_drhd_unit(drhd) { |
| 625 | struct intel_iommu *iommu = drhd->iommu; |
| 626 | |
| 627 | if (!ecap_ir_support(iommu->ecap)) |
| 628 | continue; |
| 629 | |
| 630 | if (eim && !ecap_eim_support(iommu->ecap)) { |
| 631 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " |
| 632 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); |
| 633 | return -1; |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | /* |
| 638 | * Enable queued invalidation for all the DRHD's. |
| 639 | */ |
| 640 | for_each_drhd_unit(drhd) { |
| 641 | int ret; |
| 642 | struct intel_iommu *iommu = drhd->iommu; |
| 643 | ret = dmar_enable_qi(iommu); |
| 644 | |
| 645 | if (ret) { |
| 646 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " |
| 647 | " invalidation, ecap %Lx, ret %d\n", |
| 648 | drhd->reg_base_addr, iommu->ecap, ret); |
| 649 | return -1; |
| 650 | } |
| 651 | } |
| 652 | |
| 653 | /* |
| 654 | * Setup Interrupt-remapping for all the DRHD's now. |
| 655 | */ |
| 656 | for_each_drhd_unit(drhd) { |
| 657 | struct intel_iommu *iommu = drhd->iommu; |
| 658 | |
| 659 | if (!ecap_ir_support(iommu->ecap)) |
| 660 | continue; |
| 661 | |
| 662 | if (setup_intr_remapping(iommu, eim)) |
| 663 | goto error; |
| 664 | |
| 665 | setup = 1; |
| 666 | } |
| 667 | |
| 668 | if (!setup) |
| 669 | goto error; |
| 670 | |
| 671 | intr_remapping_enabled = 1; |
| 672 | |
| 673 | return 0; |
| 674 | |
| 675 | error: |
| 676 | /* |
| 677 | * handle error condition gracefully here! |
| 678 | */ |
| 679 | return -1; |
| 680 | } |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 681 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 682 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
| 683 | struct intel_iommu *iommu) |
| 684 | { |
| 685 | struct acpi_dmar_pci_path *path; |
| 686 | u8 bus; |
| 687 | int count; |
| 688 | |
| 689 | bus = scope->bus; |
| 690 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 691 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 692 | / sizeof(struct acpi_dmar_pci_path); |
| 693 | |
| 694 | while (--count > 0) { |
| 695 | /* |
| 696 | * Access PCI directly due to the PCI |
| 697 | * subsystem isn't initialized yet. |
| 698 | */ |
| 699 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 700 | PCI_SECONDARY_BUS); |
| 701 | path++; |
| 702 | } |
| 703 | ir_hpet[ir_hpet_num].bus = bus; |
| 704 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 705 | ir_hpet[ir_hpet_num].iommu = iommu; |
| 706 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; |
| 707 | ir_hpet_num++; |
| 708 | } |
| 709 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 710 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
| 711 | struct intel_iommu *iommu) |
| 712 | { |
| 713 | struct acpi_dmar_pci_path *path; |
| 714 | u8 bus; |
| 715 | int count; |
| 716 | |
| 717 | bus = scope->bus; |
| 718 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 719 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 720 | / sizeof(struct acpi_dmar_pci_path); |
| 721 | |
| 722 | while (--count > 0) { |
| 723 | /* |
| 724 | * Access PCI directly due to the PCI |
| 725 | * subsystem isn't initialized yet. |
| 726 | */ |
| 727 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 728 | PCI_SECONDARY_BUS); |
| 729 | path++; |
| 730 | } |
| 731 | |
| 732 | ir_ioapic[ir_ioapic_num].bus = bus; |
| 733 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 734 | ir_ioapic[ir_ioapic_num].iommu = iommu; |
| 735 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; |
| 736 | ir_ioapic_num++; |
| 737 | } |
| 738 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 739 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
| 740 | struct intel_iommu *iommu) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 741 | { |
| 742 | struct acpi_dmar_hardware_unit *drhd; |
| 743 | struct acpi_dmar_device_scope *scope; |
| 744 | void *start, *end; |
| 745 | |
| 746 | drhd = (struct acpi_dmar_hardware_unit *)header; |
| 747 | |
| 748 | start = (void *)(drhd + 1); |
| 749 | end = ((void *)drhd) + header->length; |
| 750 | |
| 751 | while (start < end) { |
| 752 | scope = start; |
| 753 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { |
| 754 | if (ir_ioapic_num == MAX_IO_APICS) { |
| 755 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); |
| 756 | return -1; |
| 757 | } |
| 758 | |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 759 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
| 760 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, |
| 761 | drhd->address, iommu->seq_id); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 762 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 763 | ir_parse_one_ioapic_scope(scope, iommu); |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 764 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
| 765 | if (ir_hpet_num == MAX_HPET_TBS) { |
| 766 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); |
| 767 | return -1; |
| 768 | } |
| 769 | |
| 770 | printk(KERN_INFO "HPET id %d under DRHD base" |
| 771 | " 0x%Lx\n", scope->enumeration_id, |
| 772 | drhd->address); |
| 773 | |
| 774 | ir_parse_one_hpet_scope(scope, iommu); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 775 | } |
| 776 | start += scope->length; |
| 777 | } |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
| 782 | /* |
| 783 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping |
| 784 | * hardware unit. |
| 785 | */ |
| 786 | int __init parse_ioapics_under_ir(void) |
| 787 | { |
| 788 | struct dmar_drhd_unit *drhd; |
| 789 | int ir_supported = 0; |
| 790 | |
| 791 | for_each_drhd_unit(drhd) { |
| 792 | struct intel_iommu *iommu = drhd->iommu; |
| 793 | |
| 794 | if (ecap_ir_support(iommu->ecap)) { |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 795 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 796 | return -1; |
| 797 | |
| 798 | ir_supported = 1; |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | if (ir_supported && ir_ioapic_num != nr_ioapics) { |
| 803 | printk(KERN_WARNING |
| 804 | "Not all IO-APIC's listed under remapping hardware\n"); |
| 805 | return -1; |
| 806 | } |
| 807 | |
| 808 | return ir_supported; |
| 809 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 810 | |
| 811 | void disable_intr_remapping(void) |
| 812 | { |
| 813 | struct dmar_drhd_unit *drhd; |
| 814 | struct intel_iommu *iommu = NULL; |
| 815 | |
| 816 | /* |
| 817 | * Disable Interrupt-remapping for all the DRHD's now. |
| 818 | */ |
| 819 | for_each_iommu(iommu, drhd) { |
| 820 | if (!ecap_ir_support(iommu->ecap)) |
| 821 | continue; |
| 822 | |
| 823 | iommu_disable_intr_remapping(iommu); |
| 824 | } |
| 825 | } |
| 826 | |
| 827 | int reenable_intr_remapping(int eim) |
| 828 | { |
| 829 | struct dmar_drhd_unit *drhd; |
| 830 | int setup = 0; |
| 831 | struct intel_iommu *iommu = NULL; |
| 832 | |
| 833 | for_each_iommu(iommu, drhd) |
| 834 | if (iommu->qi) |
| 835 | dmar_reenable_qi(iommu); |
| 836 | |
| 837 | /* |
| 838 | * Setup Interrupt-remapping for all the DRHD's now. |
| 839 | */ |
| 840 | for_each_iommu(iommu, drhd) { |
| 841 | if (!ecap_ir_support(iommu->ecap)) |
| 842 | continue; |
| 843 | |
| 844 | /* Set up interrupt remapping for iommu.*/ |
| 845 | iommu_set_intr_remapping(iommu, eim); |
| 846 | setup = 1; |
| 847 | } |
| 848 | |
| 849 | if (!setup) |
| 850 | goto error; |
| 851 | |
| 852 | return 0; |
| 853 | |
| 854 | error: |
| 855 | /* |
| 856 | * handle error condition gracefully here! |
| 857 | */ |
| 858 | return -1; |
| 859 | } |
| 860 | |