blob: dd1cd990451820ffde2bef6cd1ca4aa77b3d3f2f [file] [log] [blame]
Lennert Buytenhekc680b772006-09-18 23:24:52 +01001/*
2 * arch/arm/mach-iop32x/iq31244.c
3 *
4 * Board support code for the Intel EP80219 and IQ31244 platforms.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 * Copyright (C) 2004 Intel Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/mtd/physmap.h>
28#include <linux/platform_device.h>
Russell Kingfced80c2008-09-06 12:10:45 +010029#include <linux/io.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/hardware.h>
Russell King0ba8b9b2008-08-10 18:08:10 +010031#include <asm/cputype.h>
Lennert Buytenhekc680b772006-09-18 23:24:52 +010032#include <asm/irq.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/pci.h>
36#include <asm/mach/time.h>
37#include <asm/mach-types.h>
38#include <asm/page.h>
39#include <asm/pgtable.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010040#include <mach/time.h>
Lennert Buytenhekc680b772006-09-18 23:24:52 +010041
42/*
Dan Williams094f1272007-03-16 19:31:06 +010043 * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
44 * same machine id, and the processor type was used to select board type.
45 * However this assumption breaks for an iq80219 board which is an iop219
46 * processor on an iq31244 board. The force_ep80219 flag has been added
47 * for old boot loaders using the iq31244 machine id for an ep80219 platform.
Lennert Buytenhekc680b772006-09-18 23:24:52 +010048 */
Dan Williams094f1272007-03-16 19:31:06 +010049static int force_ep80219;
50
Lennert Buytenhekc680b772006-09-18 23:24:52 +010051static int is_80219(void)
52{
Russell King0ba8b9b2008-08-10 18:08:10 +010053 return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
Lennert Buytenhekc680b772006-09-18 23:24:52 +010054}
55
Dan Williams094f1272007-03-16 19:31:06 +010056static int is_ep80219(void)
57{
58 if (machine_is_ep80219() || force_ep80219)
59 return 1;
60 else
61 return 0;
62}
63
Lennert Buytenhekc680b772006-09-18 23:24:52 +010064
65/*
66 * EP80219/IQ31244 timer tick configuration.
67 */
68static void __init iq31244_timer_init(void)
69{
Dan Williams094f1272007-03-16 19:31:06 +010070 if (is_ep80219()) {
Lennert Buytenhekc680b772006-09-18 23:24:52 +010071 /* 33.333 MHz crystal. */
Dan Williams3668b452007-02-13 17:13:34 +010072 iop_init_time(200000000);
Lennert Buytenhekc680b772006-09-18 23:24:52 +010073 } else {
74 /* 33.000 MHz crystal. */
Dan Williams3668b452007-02-13 17:13:34 +010075 iop_init_time(198000000);
Lennert Buytenhekc680b772006-09-18 23:24:52 +010076 }
77}
78
79static struct sys_timer iq31244_timer = {
80 .init = iq31244_timer_init,
Dan Williams3668b452007-02-13 17:13:34 +010081 .offset = iop_gettimeoffset,
Lennert Buytenhekc680b772006-09-18 23:24:52 +010082};
83
84
85/*
86 * IQ31244 I/O.
87 */
88static struct map_desc iq31244_io_desc[] __initdata = {
89 { /* on-board devices */
90 .virtual = IQ31244_UART,
91 .pfn = __phys_to_pfn(IQ31244_UART),
92 .length = 0x00100000,
93 .type = MT_DEVICE,
94 },
95};
96
97void __init iq31244_map_io(void)
98{
99 iop3xx_map_io();
100 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
101}
102
103
104/*
105 * EP80219/IQ31244 PCI.
106 */
Dan Williamsd73d8012007-05-15 01:03:36 +0100107static int __init
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100108ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
109{
110 int irq;
111
112 if (slot == 0) {
113 /* CFlash */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100114 irq = IRQ_IOP32X_XINT1;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100115 } else if (slot == 1) {
116 /* 82551 Pro 100 */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100117 irq = IRQ_IOP32X_XINT0;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100118 } else if (slot == 2) {
119 /* PCI-X Slot */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100120 irq = IRQ_IOP32X_XINT3;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100121 } else if (slot == 3) {
122 /* SATA */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100123 irq = IRQ_IOP32X_XINT2;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100124 } else {
125 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
126 "device PCI:%d:%d:%d\n", dev->bus->number,
127 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
128 irq = -1;
129 }
130
131 return irq;
132}
133
134static struct hw_pci ep80219_pci __initdata = {
135 .swizzle = pci_std_swizzle,
136 .nr_controllers = 1,
137 .setup = iop3xx_pci_setup,
138 .preinit = iop3xx_pci_preinit,
139 .scan = iop3xx_pci_scan_bus,
140 .map_irq = ep80219_pci_map_irq,
141};
142
Dan Williamsd73d8012007-05-15 01:03:36 +0100143static int __init
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100144iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
145{
146 int irq;
147
148 if (slot == 0) {
149 /* CFlash */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100150 irq = IRQ_IOP32X_XINT1;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100151 } else if (slot == 1) {
152 /* SATA */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100153 irq = IRQ_IOP32X_XINT2;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100154 } else if (slot == 2) {
155 /* PCI-X Slot */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100156 irq = IRQ_IOP32X_XINT3;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100157 } else if (slot == 3) {
158 /* 82546 GigE */
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100159 irq = IRQ_IOP32X_XINT0;
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100160 } else {
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100161 printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100162 "device PCI:%d:%d:%d\n", dev->bus->number,
163 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
164 irq = -1;
165 }
166
167 return irq;
168}
169
170static struct hw_pci iq31244_pci __initdata = {
171 .swizzle = pci_std_swizzle,
172 .nr_controllers = 1,
173 .setup = iop3xx_pci_setup,
174 .preinit = iop3xx_pci_preinit,
175 .scan = iop3xx_pci_scan_bus,
176 .map_irq = iq31244_pci_map_irq,
177};
178
179static int __init iq31244_pci_init(void)
180{
Dan Williamsc34002c2008-03-26 19:12:38 -0700181 if (is_ep80219())
182 pci_common_init(&ep80219_pci);
183 else if (machine_is_iq31244()) {
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100184 if (is_80219()) {
Dan Williams094f1272007-03-16 19:31:06 +0100185 printk("note: iq31244 board type has been selected\n");
186 printk("note: to select ep80219 operation:\n");
187 printk("\t1/ specify \"force_ep80219\" on the kernel"
188 " command line\n");
189 printk("\t2/ update boot loader to pass"
190 " the ep80219 id: %d\n", MACH_TYPE_EP80219);
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100191 }
Dan Williamsc34002c2008-03-26 19:12:38 -0700192 pci_common_init(&iq31244_pci);
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100193 }
194
195 return 0;
196}
197
198subsys_initcall(iq31244_pci_init);
199
200
201/*
202 * IQ31244 machine initialisation.
203 */
204static struct physmap_flash_data iq31244_flash_data = {
205 .width = 2,
206};
207
208static struct resource iq31244_flash_resource = {
209 .start = 0xf0000000,
210 .end = 0xf07fffff,
211 .flags = IORESOURCE_MEM,
212};
213
214static struct platform_device iq31244_flash_device = {
215 .name = "physmap-flash",
216 .id = 0,
217 .dev = {
218 .platform_data = &iq31244_flash_data,
219 },
220 .num_resources = 1,
221 .resource = &iq31244_flash_resource,
222};
223
224static struct plat_serial8250_port iq31244_serial_port[] = {
225 {
226 .mapbase = IQ31244_UART,
227 .membase = (char *)IQ31244_UART,
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100228 .irq = IRQ_IOP32X_XINT1,
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100229 .flags = UPF_SKIP_TEST,
230 .iotype = UPIO_MEM,
231 .regshift = 0,
232 .uartclk = 1843200,
233 },
234 { },
235};
236
237static struct resource iq31244_uart_resource = {
238 .start = IQ31244_UART,
239 .end = IQ31244_UART + 7,
240 .flags = IORESOURCE_MEM,
241};
242
243static struct platform_device iq31244_serial_device = {
244 .name = "serial8250",
245 .id = PLAT8250_DEV_PLATFORM,
246 .dev = {
247 .platform_data = iq31244_serial_port,
248 },
249 .num_resources = 1,
250 .resource = &iq31244_uart_resource,
251};
252
253/*
254 * This function will send a SHUTDOWN_COMPLETE message to the PIC
255 * controller over I2C. We are not using the i2c subsystem since
256 * we are going to power off and it may be removed
257 */
258void ep80219_power_off(void)
259{
260 /*
261 * Send the Address byte w/ the start condition
262 */
263 *IOP3XX_IDBR1 = 0x60;
264 *IOP3XX_ICR1 = 0xE9;
265 mdelay(1);
266
267 /*
268 * Send the START_MSG byte w/ no start or stop condition
269 */
270 *IOP3XX_IDBR1 = 0x0F;
271 *IOP3XX_ICR1 = 0xE8;
272 mdelay(1);
273
274 /*
275 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
276 * stop condition
277 */
278 *IOP3XX_IDBR1 = 0x03;
279 *IOP3XX_ICR1 = 0xE8;
280 mdelay(1);
281
282 /*
283 * Send an ignored byte w/ stop condition
284 */
285 *IOP3XX_IDBR1 = 0x00;
286 *IOP3XX_ICR1 = 0xEA;
287
288 while (1)
289 ;
290}
291
292static void __init iq31244_init_machine(void)
293{
294 platform_device_register(&iop3xx_i2c0_device);
295 platform_device_register(&iop3xx_i2c1_device);
296 platform_device_register(&iq31244_flash_device);
297 platform_device_register(&iq31244_serial_device);
Dan Williams2492c842007-01-02 13:52:31 -0700298 platform_device_register(&iop3xx_dma_0_channel);
299 platform_device_register(&iop3xx_dma_1_channel);
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100300
Dan Williams094f1272007-03-16 19:31:06 +0100301 if (is_ep80219())
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100302 pm_power_off = ep80219_power_off;
Dan Williams2492c842007-01-02 13:52:31 -0700303
304 if (!is_80219())
305 platform_device_register(&iop3xx_aau_channel);
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100306}
307
Dan Williams094f1272007-03-16 19:31:06 +0100308static int __init force_ep80219_setup(char *str)
309{
310 force_ep80219 = 1;
311 return 1;
312}
313
314__setup("force_ep80219", force_ep80219_setup);
315
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100316MACHINE_START(IQ31244, "Intel IQ31244")
317 /* Maintainer: Intel Corp. */
318 .phys_io = IQ31244_UART,
319 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
320 .boot_params = 0xa0000100,
321 .map_io = iq31244_map_io,
Lennert Buytenhekc852ac82006-09-18 23:26:25 +0100322 .init_irq = iop32x_init_irq,
Lennert Buytenhekc680b772006-09-18 23:24:52 +0100323 .timer = &iq31244_timer,
324 .init_machine = iq31244_init_machine,
325MACHINE_END
Dan Williams094f1272007-03-16 19:31:06 +0100326
327/* There should have been an ep80219 machine identifier from the beginning.
328 * Boot roms older than March 2007 do not know the ep80219 machine id. Pass
329 * "force_ep80219" on the kernel command line, otherwise iq31244 operation
330 * will be selected.
331 */
332MACHINE_START(EP80219, "Intel EP80219")
333 /* Maintainer: Intel Corp. */
334 .phys_io = IQ31244_UART,
335 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
336 .boot_params = 0xa0000100,
337 .map_io = iq31244_map_io,
338 .init_irq = iop32x_init_irq,
339 .timer = &iq31244_timer,
340 .init_machine = iq31244_init_machine,
341MACHINE_END