| Chander Kashyap | 34dcedf | 2013-06-19 00:29:35 +0900 | [diff] [blame^] | 1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC device tree source |
| 3 | * |
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. |
| 8 | * EXYNOS5420 based board files can include this file and provide |
| 9 | * values for board specfic bindings. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include "exynos5.dtsi" |
| 17 | / { |
| 18 | compatible = "samsung,exynos5420"; |
| 19 | |
| 20 | cpus { |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; |
| 23 | |
| 24 | cpu0: cpu@0 { |
| 25 | device_type = "cpu"; |
| 26 | compatible = "arm,cortex-a15"; |
| 27 | reg = <0x0>; |
| 28 | clock-frequency = <1800000000>; |
| 29 | }; |
| 30 | |
| 31 | cpu1: cpu@1 { |
| 32 | device_type = "cpu"; |
| 33 | compatible = "arm,cortex-a15"; |
| 34 | reg = <0x1>; |
| 35 | clock-frequency = <1800000000>; |
| 36 | }; |
| 37 | |
| 38 | cpu2: cpu@2 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "arm,cortex-a15"; |
| 41 | reg = <0x2>; |
| 42 | clock-frequency = <1800000000>; |
| 43 | }; |
| 44 | |
| 45 | cpu3: cpu@3 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,cortex-a15"; |
| 48 | reg = <0x3>; |
| 49 | clock-frequency = <1800000000>; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | clock: clock-controller@0x10010000 { |
| 54 | compatible = "samsung,exynos5420-clock"; |
| 55 | reg = <0x10010000 0x30000>; |
| 56 | #clock-cells = <1>; |
| 57 | }; |
| 58 | |
| 59 | mct@101C0000 { |
| 60 | compatible = "samsung,exynos4210-mct"; |
| 61 | reg = <0x101C0000 0x800>; |
| 62 | interrupt-controller; |
| 63 | #interrups-cells = <1>; |
| 64 | interrupt-parent = <&mct_map>; |
| 65 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; |
| 66 | clocks = <&clock 1>, <&clock 315>; |
| 67 | clock-names = "fin_pll", "mct"; |
| 68 | |
| 69 | mct_map: mct-map { |
| 70 | #interrupt-cells = <1>; |
| 71 | #address-cells = <0>; |
| 72 | #size-cells = <0>; |
| 73 | interrupt-map = <0 &combiner 23 3>, |
| 74 | <1 &combiner 23 4>, |
| 75 | <2 &combiner 25 2>, |
| 76 | <3 &combiner 25 3>, |
| 77 | <4 &gic 0 120 0>, |
| 78 | <5 &gic 0 121 0>, |
| 79 | <6 &gic 0 122 0>, |
| 80 | <7 &gic 0 123 0>; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | serial@12C00000 { |
| 85 | clocks = <&clock 257>, <&clock 128>; |
| 86 | clock-names = "uart", "clk_uart_baud0"; |
| 87 | }; |
| 88 | |
| 89 | serial@12C10000 { |
| 90 | clocks = <&clock 258>, <&clock 129>; |
| 91 | clock-names = "uart", "clk_uart_baud0"; |
| 92 | }; |
| 93 | |
| 94 | serial@12C20000 { |
| 95 | clocks = <&clock 259>, <&clock 130>; |
| 96 | clock-names = "uart", "clk_uart_baud0"; |
| 97 | }; |
| 98 | |
| 99 | serial@12C30000 { |
| 100 | clocks = <&clock 260>, <&clock 131>; |
| 101 | clock-names = "uart", "clk_uart_baud0"; |
| 102 | }; |
| 103 | }; |