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gerrit-public.fairphone.software / kernel / msm-4.9 / 351638e7deeed2ec8ce451b53d33921b3da68f83 / . / drivers / net / can / c_can / c_can.h
blob: d2e1c21b143f4ae729edd45312de1db0a804f438 [file] [log] [blame]
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
13 * Bosch C_CAN user manual can be obtained from:
14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
15 * users_manual_c_can.pdf
16 *
17 * This file is licensed under the terms of the GNU General Public
18 * License version 2. This program is licensed "as is" without any
19 * warranty of any kind, whether express or implied.
20 */
21
22#ifndef C_CAN_H
23#define C_CAN_H
24
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]25enum reg {
26 C_CAN_CTRL_REG = 0,
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]27 C_CAN_CTRL_EX_REG,
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]28 C_CAN_STS_REG,
29 C_CAN_ERR_CNT_REG,
30 C_CAN_BTR_REG,
31 C_CAN_INT_REG,
32 C_CAN_TEST_REG,
33 C_CAN_BRPEXT_REG,
34 C_CAN_IF1_COMREQ_REG,
35 C_CAN_IF1_COMMSK_REG,
36 C_CAN_IF1_MASK1_REG,
37 C_CAN_IF1_MASK2_REG,
38 C_CAN_IF1_ARB1_REG,
39 C_CAN_IF1_ARB2_REG,
40 C_CAN_IF1_MSGCTRL_REG,
41 C_CAN_IF1_DATA1_REG,
42 C_CAN_IF1_DATA2_REG,
43 C_CAN_IF1_DATA3_REG,
44 C_CAN_IF1_DATA4_REG,
45 C_CAN_IF2_COMREQ_REG,
46 C_CAN_IF2_COMMSK_REG,
47 C_CAN_IF2_MASK1_REG,
48 C_CAN_IF2_MASK2_REG,
49 C_CAN_IF2_ARB1_REG,
50 C_CAN_IF2_ARB2_REG,
51 C_CAN_IF2_MSGCTRL_REG,
52 C_CAN_IF2_DATA1_REG,
53 C_CAN_IF2_DATA2_REG,
54 C_CAN_IF2_DATA3_REG,
55 C_CAN_IF2_DATA4_REG,
56 C_CAN_TXRQST1_REG,
57 C_CAN_TXRQST2_REG,
58 C_CAN_NEWDAT1_REG,
59 C_CAN_NEWDAT2_REG,
60 C_CAN_INTPND1_REG,
61 C_CAN_INTPND2_REG,
62 C_CAN_MSGVAL1_REG,
63 C_CAN_MSGVAL2_REG,
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]64};
65
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]66static const u16 reg_map_c_can[] = {
67 [C_CAN_CTRL_REG] = 0x00,
68 [C_CAN_STS_REG] = 0x02,
69 [C_CAN_ERR_CNT_REG] = 0x04,
70 [C_CAN_BTR_REG] = 0x06,
71 [C_CAN_INT_REG] = 0x08,
72 [C_CAN_TEST_REG] = 0x0A,
73 [C_CAN_BRPEXT_REG] = 0x0C,
74 [C_CAN_IF1_COMREQ_REG] = 0x10,
75 [C_CAN_IF1_COMMSK_REG] = 0x12,
76 [C_CAN_IF1_MASK1_REG] = 0x14,
77 [C_CAN_IF1_MASK2_REG] = 0x16,
78 [C_CAN_IF1_ARB1_REG] = 0x18,
79 [C_CAN_IF1_ARB2_REG] = 0x1A,
80 [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
81 [C_CAN_IF1_DATA1_REG] = 0x1E,
82 [C_CAN_IF1_DATA2_REG] = 0x20,
83 [C_CAN_IF1_DATA3_REG] = 0x22,
84 [C_CAN_IF1_DATA4_REG] = 0x24,
85 [C_CAN_IF2_COMREQ_REG] = 0x40,
86 [C_CAN_IF2_COMMSK_REG] = 0x42,
87 [C_CAN_IF2_MASK1_REG] = 0x44,
88 [C_CAN_IF2_MASK2_REG] = 0x46,
89 [C_CAN_IF2_ARB1_REG] = 0x48,
90 [C_CAN_IF2_ARB2_REG] = 0x4A,
91 [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
92 [C_CAN_IF2_DATA1_REG] = 0x4E,
93 [C_CAN_IF2_DATA2_REG] = 0x50,
94 [C_CAN_IF2_DATA3_REG] = 0x52,
95 [C_CAN_IF2_DATA4_REG] = 0x54,
96 [C_CAN_TXRQST1_REG] = 0x80,
97 [C_CAN_TXRQST2_REG] = 0x82,
98 [C_CAN_NEWDAT1_REG] = 0x90,
99 [C_CAN_NEWDAT2_REG] = 0x92,
100 [C_CAN_INTPND1_REG] = 0xA0,
101 [C_CAN_INTPND2_REG] = 0xA2,
102 [C_CAN_MSGVAL1_REG] = 0xB0,
103 [C_CAN_MSGVAL2_REG] = 0xB2,
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]104};
105
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]106static const u16 reg_map_d_can[] = {
107 [C_CAN_CTRL_REG] = 0x00,
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]108 [C_CAN_CTRL_EX_REG] = 0x02,
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]109 [C_CAN_STS_REG] = 0x04,
110 [C_CAN_ERR_CNT_REG] = 0x08,
111 [C_CAN_BTR_REG] = 0x0C,
112 [C_CAN_BRPEXT_REG] = 0x0E,
113 [C_CAN_INT_REG] = 0x10,
114 [C_CAN_TEST_REG] = 0x14,
115 [C_CAN_TXRQST1_REG] = 0x88,
116 [C_CAN_TXRQST2_REG] = 0x8A,
117 [C_CAN_NEWDAT1_REG] = 0x9C,
118 [C_CAN_NEWDAT2_REG] = 0x9E,
119 [C_CAN_INTPND1_REG] = 0xB0,
120 [C_CAN_INTPND2_REG] = 0xB2,
121 [C_CAN_MSGVAL1_REG] = 0xC4,
122 [C_CAN_MSGVAL2_REG] = 0xC6,
123 [C_CAN_IF1_COMREQ_REG] = 0x100,
124 [C_CAN_IF1_COMMSK_REG] = 0x102,
125 [C_CAN_IF1_MASK1_REG] = 0x104,
126 [C_CAN_IF1_MASK2_REG] = 0x106,
127 [C_CAN_IF1_ARB1_REG] = 0x108,
128 [C_CAN_IF1_ARB2_REG] = 0x10A,
129 [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
130 [C_CAN_IF1_DATA1_REG] = 0x110,
131 [C_CAN_IF1_DATA2_REG] = 0x112,
132 [C_CAN_IF1_DATA3_REG] = 0x114,
133 [C_CAN_IF1_DATA4_REG] = 0x116,
134 [C_CAN_IF2_COMREQ_REG] = 0x120,
135 [C_CAN_IF2_COMMSK_REG] = 0x122,
136 [C_CAN_IF2_MASK1_REG] = 0x124,
137 [C_CAN_IF2_MASK2_REG] = 0x126,
138 [C_CAN_IF2_ARB1_REG] = 0x128,
139 [C_CAN_IF2_ARB2_REG] = 0x12A,
140 [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
141 [C_CAN_IF2_DATA1_REG] = 0x130,
142 [C_CAN_IF2_DATA2_REG] = 0x132,
143 [C_CAN_IF2_DATA3_REG] = 0x134,
144 [C_CAN_IF2_DATA4_REG] = 0x136,
145};
146
147enum c_can_dev_id {
AnilKumar Chf27b1db2012-08-02 18:43:09 +0530[diff] [blame]148 BOSCH_C_CAN_PLATFORM,
149 BOSCH_C_CAN,
150 BOSCH_D_CAN,
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]151};
152
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]153/* c_can private data structure */
154struct c_can_priv {
155 struct can_priv can; /* must be the first member */
156 struct napi_struct napi;
157 struct net_device *dev;
AnilKumar Ch4cdd34b2012-08-20 16:50:54 +0530[diff] [blame]158 struct device *device;
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]159 int tx_object;
160 int current_status;
161 int last_status;
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]162 u16 (*read_reg) (struct c_can_priv *priv, enum reg index);
163 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val);
164 void __iomem *base;
165 const u16 *regs;
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]166 unsigned long irq_flags; /* for request_irq() */
167 unsigned int tx_next;
168 unsigned int tx_echo;
169 void *priv; /* for board-specific data */
AnilKumar Ch148c87c2012-05-23 17:45:10 +0530[diff] [blame]170 u16 irqstatus;
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]171 enum c_can_dev_id type;
AnilKumar Ch52cde852012-11-21 11:14:10 +0530[diff] [blame]172 u32 __iomem *raminit_ctrlreg;
173 unsigned int instance;
174 void (*raminit) (const struct c_can_priv *priv, bool enable);
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]175};
176
177struct net_device *alloc_c_can_dev(void);
178void free_c_can_dev(struct net_device *dev);
179int register_c_can_dev(struct net_device *dev);
180void unregister_c_can_dev(struct net_device *dev);
181
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]182#ifdef CONFIG_PM
183int c_can_power_up(struct net_device *dev);
184int c_can_power_down(struct net_device *dev);
185#endif
186
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]187#endif /* C_CAN_H */