blob: 83f6bddf578b28268986601c868f9076925d2605 [file] [log] [blame]
Ralf Baechle35189fa2006-06-18 16:39:46 +01001/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <asm/gdb-stub.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
29#error Debug port used by serial driver
30#endif
31
32#define UART_CLK 25000000
33#define BASE_BAUD (UART_CLK / 16)
34#define REGISTER_BASE_0 0x0208UL
35#define REGISTER_BASE_1 0x0238UL
36
37#define REGISTER_BASE_DBG REGISTER_BASE_1
38
39#define CPRR 0x0004
40#define UACFG 0x0200
41#define UAINTS 0x0204
42#define UARBR (REGISTER_BASE_DBG + 0x0000)
43#define UATHR (REGISTER_BASE_DBG + 0x0004)
44#define UADLL (REGISTER_BASE_DBG + 0x0008)
45#define UAIER (REGISTER_BASE_DBG + 0x000c)
46#define UADLH (REGISTER_BASE_DBG + 0x0010)
47#define UAIIR (REGISTER_BASE_DBG + 0x0014)
48#define UAFCR (REGISTER_BASE_DBG + 0x0018)
49#define UALCR (REGISTER_BASE_DBG + 0x001c)
50#define UAMCR (REGISTER_BASE_DBG + 0x0020)
51#define UALSR (REGISTER_BASE_DBG + 0x0024)
52#define UAMSR (REGISTER_BASE_DBG + 0x0028)
53#define UASCR (REGISTER_BASE_DBG + 0x002c)
54
55#define PARITY_NONE 0
56#define PARITY_ODD 0x08
57#define PARITY_EVEN 0x18
58#define PARITY_MARK 0x28
59#define PARITY_SPACE 0x38
60
61#define DATA_5BIT 0x0
62#define DATA_6BIT 0x1
63#define DATA_7BIT 0x2
64#define DATA_8BIT 0x3
65
66#define STOP_1BIT 0x0
67#define STOP_2BIT 0x4
68
69#define BAUD_DBG 57600
70#define PARITY_DBG PARITY_NONE
71#define DATA_DBG DATA_8BIT
72#define STOP_DBG STOP_1BIT
73
74/* Initialize the serial port for KGDB debugging */
75void __init excite_kgdb_init(void)
76{
77 const u32 divisor = BASE_BAUD / BAUD_DBG;
78
79 /* Take the UART out of reset */
80 titan_writel(0x00ff1cff, CPRR);
81 titan_writel(0x00000000, UACFG);
82 titan_writel(0x00000002, UACFG);
83
84 titan_writel(0x0, UALCR);
85 titan_writel(0x0, UAIER);
86
87 /* Disable FIFOs */
88 titan_writel(0x00, UAFCR);
89
90 titan_writel(0x80, UALCR);
91 titan_writel(divisor & 0xff, UADLL);
92 titan_writel((divisor & 0xff00) >> 8, UADLH);
93 titan_writel(0x0, UALCR);
94
95 titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
96
97 /* Enable receiver interrupt */
98 titan_readl(UARBR);
99 titan_writel(0x1, UAIER);
100}
101
102int getDebugChar(void)
103{
104 while (!(titan_readl(UALSR) & 0x1));
105 return titan_readl(UARBR);
106}
107
108int putDebugChar(int data)
109{
110 while (!(titan_readl(UALSR) & 0x20));
111 titan_writel(data, UATHR);
112 return 1;
113}
114
115/* KGDB interrupt handler */
116asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
117{
118 if (unlikely(
119 ((titan_readl(UAIIR) & 0x7) == 4)
120 && ((titan_readl(UARBR) & 0xff) == 0x3)))
121 set_async_breakpoint(&regs->cp0_epc);
122}