Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Support for PCI bridges found on Power Macintoshes. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org) |
| 5 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/string.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/bootmem.h> |
| 19 | |
| 20 | #include <asm/sections.h> |
| 21 | #include <asm/io.h> |
| 22 | #include <asm/prom.h> |
| 23 | #include <asm/pci-bridge.h> |
| 24 | #include <asm/machdep.h> |
| 25 | #include <asm/pmac_feature.h> |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 26 | #ifdef CONFIG_PPC64 |
| 27 | #include <asm/iommu.h> |
| 28 | #include <asm/ppc-pci.h> |
| 29 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 30 | |
| 31 | #undef DEBUG |
| 32 | |
| 33 | #ifdef DEBUG |
| 34 | #define DBG(x...) printk(x) |
| 35 | #else |
| 36 | #define DBG(x...) |
| 37 | #endif |
| 38 | |
| 39 | static int add_bridge(struct device_node *dev); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 40 | |
| 41 | /* XXX Could be per-controller, but I don't think we risk anything by |
| 42 | * assuming we won't have both UniNorth and Bandit */ |
| 43 | static int has_uninorth; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 44 | #ifdef CONFIG_PPC64 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 45 | static struct pci_controller *u3_agp; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 46 | static struct pci_controller *u3_ht; |
| 47 | #endif /* CONFIG_PPC64 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 48 | |
| 49 | extern u8 pci_cache_line_size; |
| 50 | extern int pcibios_assign_bus_offset; |
| 51 | |
| 52 | struct device_node *k2_skiplist[2]; |
| 53 | |
| 54 | /* |
| 55 | * Magic constants for enabling cache coherency in the bandit/PSX bridge. |
| 56 | */ |
| 57 | #define BANDIT_DEVID_2 8 |
| 58 | #define BANDIT_REVID 3 |
| 59 | |
| 60 | #define BANDIT_DEVNUM 11 |
| 61 | #define BANDIT_MAGIC 0x50 |
| 62 | #define BANDIT_COHERENT 0x40 |
| 63 | |
| 64 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) |
| 65 | { |
| 66 | for (; node != 0;node = node->sibling) { |
| 67 | int * bus_range; |
| 68 | unsigned int *class_code; |
| 69 | int len; |
| 70 | |
| 71 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ |
| 72 | class_code = (unsigned int *) get_property(node, "class-code", NULL); |
| 73 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
| 74 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) |
| 75 | continue; |
| 76 | bus_range = (int *) get_property(node, "bus-range", &len); |
| 77 | if (bus_range != NULL && len > 2 * sizeof(int)) { |
| 78 | if (bus_range[1] > higher) |
| 79 | higher = bus_range[1]; |
| 80 | } |
| 81 | higher = fixup_one_level_bus_range(node->child, higher); |
| 82 | } |
| 83 | return higher; |
| 84 | } |
| 85 | |
| 86 | /* This routine fixes the "bus-range" property of all bridges in the |
| 87 | * system since they tend to have their "last" member wrong on macs |
| 88 | * |
| 89 | * Note that the bus numbers manipulated here are OF bus numbers, they |
| 90 | * are not Linux bus numbers. |
| 91 | */ |
| 92 | static void __init fixup_bus_range(struct device_node *bridge) |
| 93 | { |
| 94 | int * bus_range; |
| 95 | int len; |
| 96 | |
| 97 | /* Lookup the "bus-range" property for the hose */ |
| 98 | bus_range = (int *) get_property(bridge, "bus-range", &len); |
| 99 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 100 | printk(KERN_WARNING "Can't get bus-range for %s\n", |
| 101 | bridge->full_name); |
| 102 | return; |
| 103 | } |
| 104 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. |
| 109 | * |
| 110 | * The "Bandit" version is present in all early PCI PowerMacs, |
| 111 | * and up to the first ones using Grackle. Some machines may |
| 112 | * have 2 bandit controllers (2 PCI busses). |
| 113 | * |
| 114 | * "Chaos" is used in some "Bandit"-type machines as a bridge |
| 115 | * for the separate display bus. It is accessed the same |
| 116 | * way as bandit, but cannot be probed for devices. It therefore |
| 117 | * has its own config access functions. |
| 118 | * |
| 119 | * The "UniNorth" version is present in all Core99 machines |
| 120 | * (iBook, G4, new IMacs, and all the recent Apple machines). |
| 121 | * It contains 3 controllers in one ASIC. |
| 122 | * |
| 123 | * The U3 is the bridge used on G5 machines. It contains an |
| 124 | * AGP bus which is dealt with the old UniNorth access routines |
| 125 | * and a HyperTransport bus which uses its own set of access |
| 126 | * functions. |
| 127 | */ |
| 128 | |
| 129 | #define MACRISC_CFA0(devfn, off) \ |
| 130 | ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ |
| 131 | | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ |
| 132 | | (((unsigned long)(off)) & 0xFCUL)) |
| 133 | |
| 134 | #define MACRISC_CFA1(bus, devfn, off) \ |
| 135 | ((((unsigned long)(bus)) << 16) \ |
| 136 | |(((unsigned long)(devfn)) << 8) \ |
| 137 | |(((unsigned long)(off)) & 0xFCUL) \ |
| 138 | |1UL) |
| 139 | |
| 140 | static unsigned long macrisc_cfg_access(struct pci_controller* hose, |
| 141 | u8 bus, u8 dev_fn, u8 offset) |
| 142 | { |
| 143 | unsigned int caddr; |
| 144 | |
| 145 | if (bus == hose->first_busno) { |
| 146 | if (dev_fn < (11 << 3)) |
| 147 | return 0; |
| 148 | caddr = MACRISC_CFA0(dev_fn, offset); |
| 149 | } else |
| 150 | caddr = MACRISC_CFA1(bus, dev_fn, offset); |
| 151 | |
| 152 | /* Uninorth will return garbage if we don't read back the value ! */ |
| 153 | do { |
| 154 | out_le32(hose->cfg_addr, caddr); |
| 155 | } while (in_le32(hose->cfg_addr) != caddr); |
| 156 | |
| 157 | offset &= has_uninorth ? 0x07 : 0x03; |
| 158 | return ((unsigned long)hose->cfg_data) + offset; |
| 159 | } |
| 160 | |
| 161 | static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, |
| 162 | int offset, int len, u32 *val) |
| 163 | { |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 164 | struct pci_controller *hose; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 165 | unsigned long addr; |
| 166 | |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 167 | hose = pci_bus_to_host(bus); |
| 168 | if (hose == NULL) |
| 169 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 170 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 171 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); |
| 172 | if (!addr) |
| 173 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 174 | /* |
| 175 | * Note: the caller has already checked that offset is |
| 176 | * suitably aligned and that len is 1, 2 or 4. |
| 177 | */ |
| 178 | switch (len) { |
| 179 | case 1: |
| 180 | *val = in_8((u8 *)addr); |
| 181 | break; |
| 182 | case 2: |
| 183 | *val = in_le16((u16 *)addr); |
| 184 | break; |
| 185 | default: |
| 186 | *val = in_le32((u32 *)addr); |
| 187 | break; |
| 188 | } |
| 189 | return PCIBIOS_SUCCESSFUL; |
| 190 | } |
| 191 | |
| 192 | static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, |
| 193 | int offset, int len, u32 val) |
| 194 | { |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 195 | struct pci_controller *hose; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 196 | unsigned long addr; |
| 197 | |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 198 | hose = pci_bus_to_host(bus); |
| 199 | if (hose == NULL) |
| 200 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 201 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 202 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); |
| 203 | if (!addr) |
| 204 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 205 | /* |
| 206 | * Note: the caller has already checked that offset is |
| 207 | * suitably aligned and that len is 1, 2 or 4. |
| 208 | */ |
| 209 | switch (len) { |
| 210 | case 1: |
| 211 | out_8((u8 *)addr, val); |
| 212 | (void) in_8((u8 *)addr); |
| 213 | break; |
| 214 | case 2: |
| 215 | out_le16((u16 *)addr, val); |
| 216 | (void) in_le16((u16 *)addr); |
| 217 | break; |
| 218 | default: |
| 219 | out_le32((u32 *)addr, val); |
| 220 | (void) in_le32((u32 *)addr); |
| 221 | break; |
| 222 | } |
| 223 | return PCIBIOS_SUCCESSFUL; |
| 224 | } |
| 225 | |
| 226 | static struct pci_ops macrisc_pci_ops = |
| 227 | { |
| 228 | macrisc_read_config, |
| 229 | macrisc_write_config |
| 230 | }; |
| 231 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 232 | #ifdef CONFIG_PPC32 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 233 | /* |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 234 | * Verify that a specific (bus, dev_fn) exists on chaos |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 235 | */ |
| 236 | static int |
| 237 | chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) |
| 238 | { |
| 239 | struct device_node *np; |
| 240 | u32 *vendor, *device; |
| 241 | |
| 242 | np = pci_busdev_to_OF_node(bus, devfn); |
| 243 | if (np == NULL) |
| 244 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 245 | |
| 246 | vendor = (u32 *)get_property(np, "vendor-id", NULL); |
| 247 | device = (u32 *)get_property(np, "device-id", NULL); |
| 248 | if (vendor == NULL || device == NULL) |
| 249 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 250 | |
| 251 | if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) |
| 252 | && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) |
| 253 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 254 | |
| 255 | return PCIBIOS_SUCCESSFUL; |
| 256 | } |
| 257 | |
| 258 | static int |
| 259 | chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 260 | int len, u32 *val) |
| 261 | { |
| 262 | int result = chaos_validate_dev(bus, devfn, offset); |
| 263 | if (result == PCIBIOS_BAD_REGISTER_NUMBER) |
| 264 | *val = ~0U; |
| 265 | if (result != PCIBIOS_SUCCESSFUL) |
| 266 | return result; |
| 267 | return macrisc_read_config(bus, devfn, offset, len, val); |
| 268 | } |
| 269 | |
| 270 | static int |
| 271 | chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 272 | int len, u32 val) |
| 273 | { |
| 274 | int result = chaos_validate_dev(bus, devfn, offset); |
| 275 | if (result != PCIBIOS_SUCCESSFUL) |
| 276 | return result; |
| 277 | return macrisc_write_config(bus, devfn, offset, len, val); |
| 278 | } |
| 279 | |
| 280 | static struct pci_ops chaos_pci_ops = |
| 281 | { |
| 282 | chaos_read_config, |
| 283 | chaos_write_config |
| 284 | }; |
| 285 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 286 | static void __init setup_chaos(struct pci_controller *hose, |
| 287 | struct reg_property *addr) |
| 288 | { |
| 289 | /* assume a `chaos' bridge */ |
| 290 | hose->ops = &chaos_pci_ops; |
| 291 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); |
| 292 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); |
| 293 | } |
| 294 | #else |
| 295 | #define setup_chaos(hose, addr) |
| 296 | #endif /* CONFIG_PPC32 */ |
| 297 | |
| 298 | #ifdef CONFIG_PPC64 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 299 | /* |
| 300 | * These versions of U3 HyperTransport config space access ops do not |
| 301 | * implement self-view of the HT host yet |
| 302 | */ |
| 303 | |
| 304 | /* |
| 305 | * This function deals with some "special cases" devices. |
| 306 | * |
| 307 | * 0 -> No special case |
| 308 | * 1 -> Skip the device but act as if the access was successfull |
| 309 | * (return 0xff's on reads, eventually, cache config space |
| 310 | * accesses in a later version) |
| 311 | * -1 -> Hide the device (unsuccessful acess) |
| 312 | */ |
| 313 | static int u3_ht_skip_device(struct pci_controller *hose, |
| 314 | struct pci_bus *bus, unsigned int devfn) |
| 315 | { |
| 316 | struct device_node *busdn, *dn; |
| 317 | int i; |
| 318 | |
| 319 | /* We only allow config cycles to devices that are in OF device-tree |
| 320 | * as we are apparently having some weird things going on with some |
| 321 | * revs of K2 on recent G5s |
| 322 | */ |
| 323 | if (bus->self) |
| 324 | busdn = pci_device_to_OF_node(bus->self); |
| 325 | else |
| 326 | busdn = hose->arch_data; |
| 327 | for (dn = busdn->child; dn; dn = dn->sibling) |
| 328 | if (dn->data && PCI_DN(dn)->devfn == devfn) |
| 329 | break; |
| 330 | if (dn == NULL) |
| 331 | return -1; |
| 332 | |
| 333 | /* |
| 334 | * When a device in K2 is powered down, we die on config |
| 335 | * cycle accesses. Fix that here. |
| 336 | */ |
| 337 | for (i=0; i<2; i++) |
| 338 | if (k2_skiplist[i] == dn) |
| 339 | return 1; |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | #define U3_HT_CFA0(devfn, off) \ |
| 345 | ((((unsigned long)devfn) << 8) | offset) |
| 346 | #define U3_HT_CFA1(bus, devfn, off) \ |
| 347 | (U3_HT_CFA0(devfn, off) \ |
| 348 | + (((unsigned long)bus) << 16) \ |
| 349 | + 0x01000000UL) |
| 350 | |
| 351 | static unsigned long u3_ht_cfg_access(struct pci_controller* hose, |
| 352 | u8 bus, u8 devfn, u8 offset) |
| 353 | { |
| 354 | if (bus == hose->first_busno) { |
| 355 | /* For now, we don't self probe U3 HT bridge */ |
| 356 | if (PCI_SLOT(devfn) == 0) |
| 357 | return 0; |
| 358 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); |
| 359 | } else |
| 360 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); |
| 361 | } |
| 362 | |
| 363 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, |
| 364 | int offset, int len, u32 *val) |
| 365 | { |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 366 | struct pci_controller *hose; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 367 | unsigned long addr; |
| 368 | |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 369 | hose = pci_bus_to_host(bus); |
| 370 | if (hose == NULL) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 371 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 372 | |
| 373 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
| 374 | if (!addr) |
| 375 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 376 | |
| 377 | switch (u3_ht_skip_device(hose, bus, devfn)) { |
| 378 | case 0: |
| 379 | break; |
| 380 | case 1: |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 381 | switch (len) { |
| 382 | case 1: |
| 383 | *val = 0xff; break; |
| 384 | case 2: |
| 385 | *val = 0xffff; break; |
| 386 | default: |
| 387 | *val = 0xfffffffful; break; |
| 388 | } |
| 389 | return PCIBIOS_SUCCESSFUL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 390 | default: |
| 391 | return PCIBIOS_DEVICE_NOT_FOUND; |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 392 | } |
| 393 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 394 | /* |
| 395 | * Note: the caller has already checked that offset is |
| 396 | * suitably aligned and that len is 1, 2 or 4. |
| 397 | */ |
| 398 | switch (len) { |
| 399 | case 1: |
| 400 | *val = in_8((u8 *)addr); |
| 401 | break; |
| 402 | case 2: |
| 403 | *val = in_le16((u16 *)addr); |
| 404 | break; |
| 405 | default: |
| 406 | *val = in_le32((u32 *)addr); |
| 407 | break; |
| 408 | } |
| 409 | return PCIBIOS_SUCCESSFUL; |
| 410 | } |
| 411 | |
| 412 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, |
| 413 | int offset, int len, u32 val) |
| 414 | { |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 415 | struct pci_controller *hose; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 416 | unsigned long addr; |
| 417 | |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 418 | hose = pci_bus_to_host(bus); |
| 419 | if (hose == NULL) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 420 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 421 | |
| 422 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
| 423 | if (!addr) |
| 424 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 425 | |
| 426 | switch (u3_ht_skip_device(hose, bus, devfn)) { |
| 427 | case 0: |
| 428 | break; |
| 429 | case 1: |
| 430 | return PCIBIOS_SUCCESSFUL; |
| 431 | default: |
| 432 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 433 | } |
| 434 | |
| 435 | /* |
| 436 | * Note: the caller has already checked that offset is |
| 437 | * suitably aligned and that len is 1, 2 or 4. |
| 438 | */ |
| 439 | switch (len) { |
| 440 | case 1: |
| 441 | out_8((u8 *)addr, val); |
| 442 | (void) in_8((u8 *)addr); |
| 443 | break; |
| 444 | case 2: |
| 445 | out_le16((u16 *)addr, val); |
| 446 | (void) in_le16((u16 *)addr); |
| 447 | break; |
| 448 | default: |
| 449 | out_le32((u32 *)addr, val); |
| 450 | (void) in_le32((u32 *)addr); |
| 451 | break; |
| 452 | } |
| 453 | return PCIBIOS_SUCCESSFUL; |
| 454 | } |
| 455 | |
| 456 | static struct pci_ops u3_ht_pci_ops = |
| 457 | { |
| 458 | u3_ht_read_config, |
| 459 | u3_ht_write_config |
| 460 | }; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 461 | #endif /* CONFIG_PPC64 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 462 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 463 | #ifdef CONFIG_PPC32 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 464 | /* |
| 465 | * For a bandit bridge, turn on cache coherency if necessary. |
| 466 | * N.B. we could clean this up using the hose ops directly. |
| 467 | */ |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 468 | static void __init init_bandit(struct pci_controller *bp) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 469 | { |
| 470 | unsigned int vendev, magic; |
| 471 | int rev; |
| 472 | |
| 473 | /* read the word at offset 0 in config space for device 11 */ |
| 474 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); |
| 475 | udelay(2); |
| 476 | vendev = in_le32(bp->cfg_data); |
| 477 | if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + |
| 478 | PCI_VENDOR_ID_APPLE) { |
| 479 | /* read the revision id */ |
| 480 | out_le32(bp->cfg_addr, |
| 481 | (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); |
| 482 | udelay(2); |
| 483 | rev = in_8(bp->cfg_data); |
| 484 | if (rev != BANDIT_REVID) |
| 485 | printk(KERN_WARNING |
| 486 | "Unknown revision %d for bandit\n", rev); |
| 487 | } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { |
| 488 | printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); |
| 489 | return; |
| 490 | } |
| 491 | |
| 492 | /* read the word at offset 0x50 */ |
| 493 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); |
| 494 | udelay(2); |
| 495 | magic = in_le32(bp->cfg_data); |
| 496 | if ((magic & BANDIT_COHERENT) != 0) |
| 497 | return; |
| 498 | magic |= BANDIT_COHERENT; |
| 499 | udelay(2); |
| 500 | out_le32(bp->cfg_data, magic); |
| 501 | printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); |
| 502 | } |
| 503 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 504 | /* |
| 505 | * Tweak the PCI-PCI bridge chip on the blue & white G3s. |
| 506 | */ |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 507 | static void __init init_p2pbridge(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 508 | { |
| 509 | struct device_node *p2pbridge; |
| 510 | struct pci_controller* hose; |
| 511 | u8 bus, devfn; |
| 512 | u16 val; |
| 513 | |
| 514 | /* XXX it would be better here to identify the specific |
| 515 | PCI-PCI bridge chip we have. */ |
| 516 | if ((p2pbridge = find_devices("pci-bridge")) == 0 |
| 517 | || p2pbridge->parent == NULL |
| 518 | || strcmp(p2pbridge->parent->name, "pci") != 0) |
| 519 | return; |
| 520 | if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { |
| 521 | DBG("Can't find PCI infos for PCI<->PCI bridge\n"); |
| 522 | return; |
| 523 | } |
| 524 | /* Warning: At this point, we have not yet renumbered all busses. |
| 525 | * So we must use OF walking to find out hose |
| 526 | */ |
| 527 | hose = pci_find_hose_for_OF_device(p2pbridge); |
| 528 | if (!hose) { |
| 529 | DBG("Can't find hose for PCI<->PCI bridge\n"); |
| 530 | return; |
| 531 | } |
| 532 | if (early_read_config_word(hose, bus, devfn, |
| 533 | PCI_BRIDGE_CONTROL, &val) < 0) { |
| 534 | printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n"); |
| 535 | return; |
| 536 | } |
| 537 | val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; |
| 538 | early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); |
| 539 | } |
| 540 | |
| 541 | /* |
| 542 | * Some Apple desktop machines have a NEC PD720100A USB2 controller |
| 543 | * on the motherboard. Open Firmware, on these, will disable the |
| 544 | * EHCI part of it so it behaves like a pair of OHCI's. This fixup |
| 545 | * code re-enables it ;) |
| 546 | */ |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 547 | static void __init fixup_nec_usb2(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 548 | { |
| 549 | struct device_node *nec; |
| 550 | |
| 551 | for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { |
| 552 | struct pci_controller *hose; |
| 553 | u32 data, *prop; |
| 554 | u8 bus, devfn; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 555 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 556 | prop = (u32 *)get_property(nec, "vendor-id", NULL); |
| 557 | if (prop == NULL) |
| 558 | continue; |
| 559 | if (0x1033 != *prop) |
| 560 | continue; |
| 561 | prop = (u32 *)get_property(nec, "device-id", NULL); |
| 562 | if (prop == NULL) |
| 563 | continue; |
| 564 | if (0x0035 != *prop) |
| 565 | continue; |
| 566 | prop = (u32 *)get_property(nec, "reg", NULL); |
| 567 | if (prop == NULL) |
| 568 | continue; |
| 569 | devfn = (prop[0] >> 8) & 0xff; |
| 570 | bus = (prop[0] >> 16) & 0xff; |
| 571 | if (PCI_FUNC(devfn) != 0) |
| 572 | continue; |
| 573 | hose = pci_find_hose_for_OF_device(nec); |
| 574 | if (!hose) |
| 575 | continue; |
| 576 | early_read_config_dword(hose, bus, devfn, 0xe4, &data); |
| 577 | if (data & 1UL) { |
| 578 | printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n"); |
| 579 | data &= ~1UL; |
| 580 | early_write_config_dword(hose, bus, devfn, 0xe4, data); |
| 581 | early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE, |
| 582 | nec->intrs[0].line); |
| 583 | } |
| 584 | } |
| 585 | } |
| 586 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 587 | #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \ |
| 588 | | (((o) & ~3) << 24)) |
| 589 | |
| 590 | #define GRACKLE_PICR1_STG 0x00000040 |
| 591 | #define GRACKLE_PICR1_LOOPSNOOP 0x00000010 |
| 592 | |
| 593 | /* N.B. this is called before bridges is initialized, so we can't |
| 594 | use grackle_pcibios_{read,write}_config_dword. */ |
| 595 | static inline void grackle_set_stg(struct pci_controller* bp, int enable) |
| 596 | { |
| 597 | unsigned int val; |
| 598 | |
| 599 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); |
| 600 | val = in_le32(bp->cfg_data); |
| 601 | val = enable? (val | GRACKLE_PICR1_STG) : |
| 602 | (val & ~GRACKLE_PICR1_STG); |
| 603 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); |
| 604 | out_le32(bp->cfg_data, val); |
| 605 | (void)in_le32(bp->cfg_data); |
| 606 | } |
| 607 | |
| 608 | static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) |
| 609 | { |
| 610 | unsigned int val; |
| 611 | |
| 612 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); |
| 613 | val = in_le32(bp->cfg_data); |
| 614 | val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : |
| 615 | (val & ~GRACKLE_PICR1_LOOPSNOOP); |
| 616 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); |
| 617 | out_le32(bp->cfg_data, val); |
| 618 | (void)in_le32(bp->cfg_data); |
| 619 | } |
| 620 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 621 | void __init setup_grackle(struct pci_controller *hose) |
| 622 | { |
| 623 | setup_indirect_pci(hose, 0xfec00000, 0xfee00000); |
| 624 | if (machine_is_compatible("AAPL,PowerBook1998")) |
| 625 | grackle_set_loop_snoop(hose, 1); |
| 626 | #if 0 /* Disabled for now, HW problems ??? */ |
| 627 | grackle_set_stg(hose, 1); |
| 628 | #endif |
| 629 | } |
| 630 | |
| 631 | static void __init setup_bandit(struct pci_controller *hose, |
| 632 | struct reg_property *addr) |
| 633 | { |
| 634 | hose->ops = ¯isc_pci_ops; |
| 635 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); |
| 636 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); |
| 637 | init_bandit(hose); |
| 638 | } |
| 639 | |
| 640 | static int __init setup_uninorth(struct pci_controller *hose, |
| 641 | struct reg_property *addr) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 642 | { |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 643 | pci_assign_all_buses = 1; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 644 | has_uninorth = 1; |
| 645 | hose->ops = ¯isc_pci_ops; |
| 646 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); |
| 647 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); |
| 648 | /* We "know" that the bridge at f2000000 has the PCI slots. */ |
| 649 | return addr->address == 0xf2000000; |
| 650 | } |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 651 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 652 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 653 | #ifdef CONFIG_PPC64 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 654 | static void __init setup_u3_agp(struct pci_controller* hose) |
| 655 | { |
| 656 | /* On G5, we move AGP up to high bus number so we don't need |
| 657 | * to reassign bus numbers for HT. If we ever have P2P bridges |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 658 | * on AGP, we'll have to move pci_assign_all_busses to the |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 659 | * pci_controller structure so we enable it for AGP and not for |
| 660 | * HT childs. |
| 661 | * We hard code the address because of the different size of |
| 662 | * the reg address cell, we shall fix that by killing struct |
| 663 | * reg_property and using some accessor functions instead |
| 664 | */ |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 665 | hose->first_busno = 0xf0; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 666 | hose->last_busno = 0xff; |
| 667 | has_uninorth = 1; |
| 668 | hose->ops = ¯isc_pci_ops; |
| 669 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); |
| 670 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); |
| 671 | |
| 672 | u3_agp = hose; |
| 673 | } |
| 674 | |
| 675 | static void __init setup_u3_ht(struct pci_controller* hose) |
| 676 | { |
| 677 | struct device_node *np = (struct device_node *)hose->arch_data; |
| 678 | int i, cur; |
| 679 | |
| 680 | hose->ops = &u3_ht_pci_ops; |
| 681 | |
| 682 | /* We hard code the address because of the different size of |
| 683 | * the reg address cell, we shall fix that by killing struct |
| 684 | * reg_property and using some accessor functions instead |
| 685 | */ |
| 686 | hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); |
| 687 | |
| 688 | /* |
| 689 | * /ht node doesn't expose a "ranges" property, so we "remove" regions that |
| 690 | * have been allocated to AGP. So far, this version of the code doesn't assign |
| 691 | * any of the 0xfxxxxxxx "fine" memory regions to /ht. |
| 692 | * We need to fix that sooner or later by either parsing all child "ranges" |
| 693 | * properties or figuring out the U3 address space decoding logic and |
| 694 | * then read its configuration register (if any). |
| 695 | */ |
| 696 | hose->io_base_phys = 0xf4000000; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 697 | hose->pci_io_size = 0x00400000; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 698 | hose->io_resource.name = np->full_name; |
| 699 | hose->io_resource.start = 0; |
| 700 | hose->io_resource.end = 0x003fffff; |
| 701 | hose->io_resource.flags = IORESOURCE_IO; |
| 702 | hose->pci_mem_offset = 0; |
| 703 | hose->first_busno = 0; |
| 704 | hose->last_busno = 0xef; |
| 705 | hose->mem_resources[0].name = np->full_name; |
| 706 | hose->mem_resources[0].start = 0x80000000; |
| 707 | hose->mem_resources[0].end = 0xefffffff; |
| 708 | hose->mem_resources[0].flags = IORESOURCE_MEM; |
| 709 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 710 | u3_ht = hose; |
| 711 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 712 | if (u3_agp == NULL) { |
| 713 | DBG("U3 has no AGP, using full resource range\n"); |
| 714 | return; |
| 715 | } |
| 716 | |
| 717 | /* We "remove" the AGP resources from the resources allocated to HT, that |
| 718 | * is we create "holes". However, that code does assumptions that so far |
| 719 | * happen to be true (cross fingers...), typically that resources in the |
| 720 | * AGP node are properly ordered |
| 721 | */ |
| 722 | cur = 0; |
| 723 | for (i=0; i<3; i++) { |
| 724 | struct resource *res = &u3_agp->mem_resources[i]; |
| 725 | if (res->flags != IORESOURCE_MEM) |
| 726 | continue; |
| 727 | /* We don't care about "fine" resources */ |
| 728 | if (res->start >= 0xf0000000) |
| 729 | continue; |
| 730 | /* Check if it's just a matter of "shrinking" us in one direction */ |
| 731 | if (hose->mem_resources[cur].start == res->start) { |
| 732 | DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", |
| 733 | cur, hose->mem_resources[cur].start, res->end + 1); |
| 734 | hose->mem_resources[cur].start = res->end + 1; |
| 735 | continue; |
| 736 | } |
| 737 | if (hose->mem_resources[cur].end == res->end) { |
| 738 | DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", |
| 739 | cur, hose->mem_resources[cur].end, res->start - 1); |
| 740 | hose->mem_resources[cur].end = res->start - 1; |
| 741 | continue; |
| 742 | } |
| 743 | /* No, it's not the case, we need a hole */ |
| 744 | if (cur == 2) { |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 745 | /* not enough resources for a hole, we drop part of the range */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 746 | printk(KERN_WARNING "Running out of resources for /ht host !\n"); |
| 747 | hose->mem_resources[cur].end = res->start - 1; |
| 748 | continue; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 749 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 750 | cur++; |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 751 | DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 752 | cur-1, res->start - 1, cur, res->end + 1); |
| 753 | hose->mem_resources[cur].name = np->full_name; |
| 754 | hose->mem_resources[cur].flags = IORESOURCE_MEM; |
| 755 | hose->mem_resources[cur].start = res->end + 1; |
| 756 | hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; |
| 757 | hose->mem_resources[cur-1].end = res->start - 1; |
| 758 | } |
| 759 | } |
| 760 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 761 | /* XXX this needs to be converged between ppc32 and ppc64... */ |
| 762 | static struct pci_controller * __init pcibios_alloc_controller(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 763 | { |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 764 | struct pci_controller *hose; |
| 765 | |
| 766 | hose = alloc_bootmem(sizeof(struct pci_controller)); |
| 767 | if (hose) |
| 768 | pci_setup_pci_controller(hose); |
| 769 | return hose; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 770 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 771 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 772 | |
| 773 | /* |
| 774 | * We assume that if we have a G3 powermac, we have one bridge called |
| 775 | * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, |
| 776 | * if we have one or more bandit or chaos bridges, we don't have a MPC106. |
| 777 | */ |
| 778 | static int __init add_bridge(struct device_node *dev) |
| 779 | { |
| 780 | int len; |
| 781 | struct pci_controller *hose; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 782 | #ifdef CONFIG_PPC32 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 783 | struct reg_property *addr; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 784 | #endif |
| 785 | char *disp_name; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 786 | int *bus_range; |
| 787 | int primary = 1; |
| 788 | |
| 789 | DBG("Adding PCI host bridge %s\n", dev->full_name); |
| 790 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 791 | #ifdef CONFIG_PPC32 |
| 792 | /* XXX fix this */ |
| 793 | addr = (struct reg_property *) get_property(dev, "reg", &len); |
| 794 | if (addr == NULL || len < sizeof(*addr)) { |
| 795 | printk(KERN_WARNING "Can't use %s: no address\n", |
| 796 | dev->full_name); |
| 797 | return -ENODEV; |
| 798 | } |
| 799 | #endif |
| 800 | bus_range = (int *) get_property(dev, "bus-range", &len); |
| 801 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 802 | printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", |
| 803 | dev->full_name); |
| 804 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 805 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 806 | hose = pcibios_alloc_controller(); |
| 807 | if (!hose) |
| 808 | return -ENOMEM; |
| 809 | hose->arch_data = dev; |
| 810 | hose->first_busno = bus_range ? bus_range[0] : 0; |
| 811 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 812 | |
| 813 | disp_name = NULL; |
| 814 | #ifdef CONFIG_POWER4 |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 815 | if (device_is_compatible(dev, "u3-agp")) { |
| 816 | setup_u3_agp(hose); |
| 817 | disp_name = "U3-AGP"; |
| 818 | primary = 0; |
| 819 | } else if (device_is_compatible(dev, "u3-ht")) { |
| 820 | setup_u3_ht(hose); |
| 821 | disp_name = "U3-HT"; |
| 822 | primary = 1; |
| 823 | } |
| 824 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", |
| 825 | disp_name, hose->first_busno, hose->last_busno); |
| 826 | #else |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 827 | if (device_is_compatible(dev, "uni-north")) { |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 828 | primary = setup_uninorth(hose, addr); |
| 829 | disp_name = "UniNorth"; |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 830 | } else if (strcmp(dev->name, "pci") == 0) { |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 831 | /* XXX assume this is a mpc106 (grackle) */ |
| 832 | setup_grackle(hose); |
| 833 | disp_name = "Grackle (MPC106)"; |
| 834 | } else if (strcmp(dev->name, "bandit") == 0) { |
| 835 | setup_bandit(hose, addr); |
| 836 | disp_name = "Bandit"; |
| 837 | } else if (strcmp(dev->name, "chaos") == 0) { |
| 838 | setup_chaos(hose, addr); |
| 839 | disp_name = "Chaos"; |
| 840 | primary = 0; |
| 841 | } |
| 842 | printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. Firmware bus number: %d->%d\n", |
| 843 | disp_name, addr->address, hose->first_busno, hose->last_busno); |
| 844 | #endif |
| 845 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
| 846 | hose, hose->cfg_addr, hose->cfg_data); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 847 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 848 | /* Interpret the "ranges" property */ |
| 849 | /* This also maps the I/O region and sets isa_io/mem_base */ |
| 850 | pci_process_bridge_OF_ranges(hose, dev, primary); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 851 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 852 | /* Fixup "bus-range" OF property */ |
| 853 | fixup_bus_range(dev); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
| 858 | static void __init |
| 859 | pcibios_fixup_OF_interrupts(void) |
| 860 | { |
| 861 | struct pci_dev* dev = NULL; |
| 862 | |
| 863 | /* |
| 864 | * Open Firmware often doesn't initialize the |
| 865 | * PCI_INTERRUPT_LINE config register properly, so we |
| 866 | * should find the device node and apply the interrupt |
| 867 | * obtained from the OF device-tree |
| 868 | */ |
| 869 | for_each_pci_dev(dev) { |
| 870 | struct device_node *node; |
| 871 | node = pci_device_to_OF_node(dev); |
| 872 | /* this is the node, see if it has interrupts */ |
| 873 | if (node && node->n_intrs > 0) |
| 874 | dev->irq = node->intrs[0].line; |
| 875 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); |
| 876 | } |
| 877 | } |
| 878 | |
| 879 | void __init |
| 880 | pmac_pcibios_fixup(void) |
| 881 | { |
| 882 | /* Fixup interrupts according to OF tree */ |
| 883 | pcibios_fixup_OF_interrupts(); |
| 884 | } |
| 885 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 886 | #ifdef CONFIG_PPC64 |
| 887 | static void __init pmac_fixup_phb_resources(void) |
| 888 | { |
| 889 | struct pci_controller *hose, *tmp; |
| 890 | |
| 891 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
| 892 | printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", |
| 893 | hose->global_number, |
| 894 | hose->io_resource.start, hose->io_resource.end); |
| 895 | } |
| 896 | } |
| 897 | #endif |
| 898 | |
| 899 | void __init pmac_pci_init(void) |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 900 | { |
| 901 | struct device_node *np, *root; |
| 902 | struct device_node *ht = NULL; |
| 903 | |
| 904 | root = of_find_node_by_path("/"); |
| 905 | if (root == NULL) { |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 906 | printk(KERN_CRIT "pmac_pci_init: can't find root " |
| 907 | "of device tree\n"); |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 908 | return; |
| 909 | } |
| 910 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { |
| 911 | if (np->name == NULL) |
| 912 | continue; |
| 913 | if (strcmp(np->name, "bandit") == 0 |
| 914 | || strcmp(np->name, "chaos") == 0 |
| 915 | || strcmp(np->name, "pci") == 0) { |
| 916 | if (add_bridge(np) == 0) |
| 917 | of_node_get(np); |
| 918 | } |
| 919 | if (strcmp(np->name, "ht") == 0) { |
| 920 | of_node_get(np); |
| 921 | ht = np; |
| 922 | } |
| 923 | } |
| 924 | of_node_put(root); |
| 925 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 926 | #ifdef CONFIG_PPC64 |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 927 | /* Probe HT last as it relies on the agp resources to be already |
| 928 | * setup |
| 929 | */ |
| 930 | if (ht && add_bridge(ht) != 0) |
| 931 | of_node_put(ht); |
| 932 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 933 | /* |
| 934 | * We need to call pci_setup_phb_io for the HT bridge first |
| 935 | * so it gets the I/O port numbers starting at 0, and we |
| 936 | * need to call it for the AGP bridge after that so it gets |
| 937 | * small positive I/O port numbers. |
| 938 | */ |
| 939 | if (u3_ht) |
| 940 | pci_setup_phb_io(u3_ht, 1); |
| 941 | if (u3_agp) |
| 942 | pci_setup_phb_io(u3_agp, 0); |
| 943 | |
| 944 | /* |
| 945 | * On ppc64, fixup the IO resources on our host bridges as |
| 946 | * the common code does it only for children of the host bridges |
| 947 | */ |
| 948 | pmac_fixup_phb_resources(); |
| 949 | |
| 950 | /* Setup the linkage between OF nodes and PHBs */ |
| 951 | pci_devs_phb_init(); |
| 952 | |
| 953 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We |
| 954 | * assume there is no P2P bridge on the AGP bus, which should be a |
| 955 | * safe assumptions hopefully. |
| 956 | */ |
| 957 | if (u3_agp) { |
| 958 | struct device_node *np = u3_agp->arch_data; |
| 959 | PCI_DN(np)->busno = 0xf0; |
| 960 | for (np = np->child; np; np = np->sibling) |
| 961 | PCI_DN(np)->busno = 0xf0; |
| 962 | } |
| 963 | |
| 964 | /* map in PCI I/O space */ |
| 965 | phbs_remap_io(); |
| 966 | |
| 967 | /* pmac_check_ht_link(); */ |
| 968 | |
| 969 | /* Tell pci.c to not use the common resource allocation mechanism */ |
| 970 | pci_probe_only = 1; |
| 971 | |
| 972 | /* Allow all IO */ |
| 973 | io_page_mask = -1; |
| 974 | |
| 975 | #else /* CONFIG_PPC64 */ |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 976 | init_p2pbridge(); |
| 977 | fixup_nec_usb2(); |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 978 | |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 979 | /* We are still having some issues with the Xserve G4, enabling |
| 980 | * some offset between bus number and domains for now when we |
| 981 | * assign all busses should help for now |
| 982 | */ |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 983 | if (pci_assign_all_buses) |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 984 | pcibios_assign_bus_offset = 0x10; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 985 | #endif |
Paul Mackerras | 3c3f42d | 2005-10-10 22:58:41 +1000 | [diff] [blame] | 986 | } |
| 987 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 988 | int |
| 989 | pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) |
| 990 | { |
| 991 | struct device_node* node; |
| 992 | int updatecfg = 0; |
| 993 | int uninorth_child; |
| 994 | |
| 995 | node = pci_device_to_OF_node(dev); |
| 996 | |
| 997 | /* We don't want to enable USB controllers absent from the OF tree |
| 998 | * (iBook second controller) |
| 999 | */ |
| 1000 | if (dev->vendor == PCI_VENDOR_ID_APPLE |
| 1001 | && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) |
| 1002 | && !node) { |
| 1003 | printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", |
| 1004 | pci_name(dev)); |
| 1005 | return -EINVAL; |
| 1006 | } |
| 1007 | |
| 1008 | if (!node) |
| 1009 | return 0; |
| 1010 | |
| 1011 | uninorth_child = node->parent && |
| 1012 | device_is_compatible(node->parent, "uni-north"); |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 1013 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1014 | /* Firewire & GMAC were disabled after PCI probe, the driver is |
| 1015 | * claiming them, we must re-enable them now. |
| 1016 | */ |
| 1017 | if (uninorth_child && !strcmp(node->name, "firewire") && |
| 1018 | (device_is_compatible(node, "pci106b,18") || |
| 1019 | device_is_compatible(node, "pci106b,30") || |
| 1020 | device_is_compatible(node, "pci11c1,5811"))) { |
| 1021 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); |
| 1022 | pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); |
| 1023 | updatecfg = 1; |
| 1024 | } |
| 1025 | if (uninorth_child && !strcmp(node->name, "ethernet") && |
| 1026 | device_is_compatible(node, "gmac")) { |
| 1027 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); |
| 1028 | updatecfg = 1; |
| 1029 | } |
| 1030 | |
| 1031 | if (updatecfg) { |
| 1032 | u16 cmd; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 1033 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1034 | /* |
| 1035 | * Make sure PCI is correctly configured |
| 1036 | * |
| 1037 | * We use old pci_bios versions of the function since, by |
| 1038 | * default, gmac is not powered up, and so will be absent |
| 1039 | * from the kernel initial PCI lookup. |
| 1040 | * |
| 1041 | * Should be replaced by 2.4 new PCI mechanisms and really |
| 1042 | * register the device. |
| 1043 | */ |
| 1044 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 1045 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
| 1046 | | PCI_COMMAND_INVALIDATE; |
| 1047 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1048 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); |
| 1049 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, |
| 1050 | L1_CACHE_BYTES >> 2); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1051 | } |
| 1052 | |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
| 1056 | /* We power down some devices after they have been probed. They'll |
| 1057 | * be powered back on later on |
| 1058 | */ |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 1059 | void __init pmac_pcibios_after_init(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1060 | { |
| 1061 | struct device_node* nd; |
| 1062 | |
| 1063 | #ifdef CONFIG_BLK_DEV_IDE |
| 1064 | struct pci_dev *dev = NULL; |
| 1065 | |
| 1066 | /* OF fails to initialize IDE controllers on macs |
| 1067 | * (and maybe other machines) |
| 1068 | * |
| 1069 | * Ideally, this should be moved to the IDE layer, but we need |
| 1070 | * to check specifically with Andre Hedrick how to do it cleanly |
| 1071 | * since the common IDE code seem to care about the fact that the |
| 1072 | * BIOS may have disabled a controller. |
| 1073 | * |
| 1074 | * -- BenH |
| 1075 | */ |
| 1076 | for_each_pci_dev(dev) { |
| 1077 | if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) |
| 1078 | pci_enable_device(dev); |
| 1079 | } |
| 1080 | #endif /* CONFIG_BLK_DEV_IDE */ |
| 1081 | |
| 1082 | nd = find_devices("firewire"); |
| 1083 | while (nd) { |
| 1084 | if (nd->parent && (device_is_compatible(nd, "pci106b,18") || |
| 1085 | device_is_compatible(nd, "pci106b,30") || |
| 1086 | device_is_compatible(nd, "pci11c1,5811")) |
| 1087 | && device_is_compatible(nd->parent, "uni-north")) { |
| 1088 | pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); |
| 1089 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); |
| 1090 | } |
| 1091 | nd = nd->next; |
| 1092 | } |
| 1093 | nd = find_devices("ethernet"); |
| 1094 | while (nd) { |
| 1095 | if (nd->parent && device_is_compatible(nd, "gmac") |
| 1096 | && device_is_compatible(nd->parent, "uni-north")) |
| 1097 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); |
| 1098 | nd = nd->next; |
| 1099 | } |
| 1100 | } |
| 1101 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1102 | #ifdef CONFIG_PPC32 |
| 1103 | void pmac_pci_fixup_cardbus(struct pci_dev* dev) |
| 1104 | { |
| 1105 | if (_machine != _MACH_Pmac) |
| 1106 | return; |
| 1107 | /* |
| 1108 | * Fix the interrupt routing on the various cardbus bridges |
| 1109 | * used on powerbooks |
| 1110 | */ |
| 1111 | if (dev->vendor != PCI_VENDOR_ID_TI) |
| 1112 | return; |
| 1113 | if (dev->device == PCI_DEVICE_ID_TI_1130 || |
| 1114 | dev->device == PCI_DEVICE_ID_TI_1131) { |
| 1115 | u8 val; |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame^] | 1116 | /* Enable PCI interrupt */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1117 | if (pci_read_config_byte(dev, 0x91, &val) == 0) |
| 1118 | pci_write_config_byte(dev, 0x91, val | 0x30); |
| 1119 | /* Disable ISA interrupt mode */ |
| 1120 | if (pci_read_config_byte(dev, 0x92, &val) == 0) |
| 1121 | pci_write_config_byte(dev, 0x92, val & ~0x06); |
| 1122 | } |
| 1123 | if (dev->device == PCI_DEVICE_ID_TI_1210 || |
| 1124 | dev->device == PCI_DEVICE_ID_TI_1211 || |
| 1125 | dev->device == PCI_DEVICE_ID_TI_1410 || |
| 1126 | dev->device == PCI_DEVICE_ID_TI_1510) { |
| 1127 | u8 val; |
| 1128 | /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA |
| 1129 | signal out the MFUNC0 pin */ |
| 1130 | if (pci_read_config_byte(dev, 0x8c, &val) == 0) |
| 1131 | pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); |
| 1132 | /* Disable ISA interrupt mode */ |
| 1133 | if (pci_read_config_byte(dev, 0x92, &val) == 0) |
| 1134 | pci_write_config_byte(dev, 0x92, val & ~0x06); |
| 1135 | } |
| 1136 | } |
| 1137 | |
| 1138 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); |
| 1139 | |
| 1140 | void pmac_pci_fixup_pciata(struct pci_dev* dev) |
| 1141 | { |
| 1142 | u8 progif = 0; |
| 1143 | |
| 1144 | /* |
| 1145 | * On PowerMacs, we try to switch any PCI ATA controller to |
| 1146 | * fully native mode |
| 1147 | */ |
| 1148 | if (_machine != _MACH_Pmac) |
| 1149 | return; |
| 1150 | /* Some controllers don't have the class IDE */ |
| 1151 | if (dev->vendor == PCI_VENDOR_ID_PROMISE) |
| 1152 | switch(dev->device) { |
| 1153 | case PCI_DEVICE_ID_PROMISE_20246: |
| 1154 | case PCI_DEVICE_ID_PROMISE_20262: |
| 1155 | case PCI_DEVICE_ID_PROMISE_20263: |
| 1156 | case PCI_DEVICE_ID_PROMISE_20265: |
| 1157 | case PCI_DEVICE_ID_PROMISE_20267: |
| 1158 | case PCI_DEVICE_ID_PROMISE_20268: |
| 1159 | case PCI_DEVICE_ID_PROMISE_20269: |
| 1160 | case PCI_DEVICE_ID_PROMISE_20270: |
| 1161 | case PCI_DEVICE_ID_PROMISE_20271: |
| 1162 | case PCI_DEVICE_ID_PROMISE_20275: |
| 1163 | case PCI_DEVICE_ID_PROMISE_20276: |
| 1164 | case PCI_DEVICE_ID_PROMISE_20277: |
| 1165 | goto good; |
| 1166 | } |
| 1167 | /* Others, check PCI class */ |
| 1168 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) |
| 1169 | return; |
| 1170 | good: |
| 1171 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); |
| 1172 | if ((progif & 5) != 5) { |
| 1173 | printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev)); |
| 1174 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); |
| 1175 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || |
| 1176 | (progif & 5) != 5) |
| 1177 | printk(KERN_ERR "Rewrite of PROGIF failed !\n"); |
| 1178 | } |
| 1179 | } |
| 1180 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); |
| 1181 | #endif |
| 1182 | |
| 1183 | /* |
| 1184 | * Disable second function on K2-SATA, it's broken |
| 1185 | * and disable IO BARs on first one |
| 1186 | */ |
| 1187 | static void fixup_k2_sata(struct pci_dev* dev) |
| 1188 | { |
| 1189 | int i; |
| 1190 | u16 cmd; |
| 1191 | |
| 1192 | if (PCI_FUNC(dev->devfn) > 0) { |
| 1193 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1194 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
| 1195 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1196 | for (i = 0; i < 6; i++) { |
| 1197 | dev->resource[i].start = dev->resource[i].end = 0; |
| 1198 | dev->resource[i].flags = 0; |
| 1199 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); |
| 1200 | } |
| 1201 | } else { |
| 1202 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1203 | cmd &= ~PCI_COMMAND_IO; |
| 1204 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1205 | for (i = 0; i < 5; i++) { |
| 1206 | dev->resource[i].start = dev->resource[i].end = 0; |
| 1207 | dev->resource[i].flags = 0; |
| 1208 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); |
| 1209 | } |
| 1210 | } |
| 1211 | } |
| 1212 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); |
| 1213 | |