Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _MHI_INT_H |
| 14 | #define _MHI_INT_H |
| 15 | |
| 16 | extern struct bus_type mhi_bus_type; |
| 17 | |
| 18 | /* MHI mmio register mapping */ |
| 19 | #define PCI_INVALID_READ(val) (val == U32_MAX) |
| 20 | #define MHI_REG_SIZE (SZ_4K) |
| 21 | |
| 22 | #define MHIREGLEN (0x0) |
| 23 | #define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF) |
| 24 | #define MHIREGLEN_MHIREGLEN_SHIFT (0) |
| 25 | |
| 26 | #define MHIVER (0x8) |
| 27 | #define MHIVER_MHIVER_MASK (0xFFFFFFFF) |
| 28 | #define MHIVER_MHIVER_SHIFT (0) |
| 29 | |
| 30 | #define MHICFG (0x10) |
| 31 | #define MHICFG_NHWER_MASK (0xFF000000) |
| 32 | #define MHICFG_NHWER_SHIFT (24) |
| 33 | #define MHICFG_NER_MASK (0xFF0000) |
| 34 | #define MHICFG_NER_SHIFT (16) |
| 35 | #define MHICFG_NHWCH_MASK (0xFF00) |
| 36 | #define MHICFG_NHWCH_SHIFT (8) |
| 37 | #define MHICFG_NCH_MASK (0xFF) |
| 38 | #define MHICFG_NCH_SHIFT (0) |
| 39 | |
| 40 | #define CHDBOFF (0x18) |
| 41 | #define CHDBOFF_CHDBOFF_MASK (0xFFFFFFFF) |
| 42 | #define CHDBOFF_CHDBOFF_SHIFT (0) |
| 43 | |
| 44 | #define ERDBOFF (0x20) |
| 45 | #define ERDBOFF_ERDBOFF_MASK (0xFFFFFFFF) |
| 46 | #define ERDBOFF_ERDBOFF_SHIFT (0) |
| 47 | |
| 48 | #define BHIOFF (0x28) |
| 49 | #define BHIOFF_BHIOFF_MASK (0xFFFFFFFF) |
| 50 | #define BHIOFF_BHIOFF_SHIFT (0) |
| 51 | |
| 52 | #define BHIEOFF (0x2C) |
| 53 | #define BHIEOFF_BHIEOFF_MASK (0xFFFFFFFF) |
| 54 | #define BHIEOFF_BHIEOFF_SHIFT (0) |
| 55 | |
| 56 | #define DEBUGOFF (0x30) |
| 57 | #define DEBUGOFF_DEBUGOFF_MASK (0xFFFFFFFF) |
| 58 | #define DEBUGOFF_DEBUGOFF_SHIFT (0) |
| 59 | |
| 60 | #define MHICTRL (0x38) |
| 61 | #define MHICTRL_MHISTATE_MASK (0x0000FF00) |
| 62 | #define MHICTRL_MHISTATE_SHIFT (8) |
| 63 | #define MHICTRL_RESET_MASK (0x2) |
| 64 | #define MHICTRL_RESET_SHIFT (1) |
| 65 | |
| 66 | #define MHISTATUS (0x48) |
| 67 | #define MHISTATUS_MHISTATE_MASK (0x0000FF00) |
| 68 | #define MHISTATUS_MHISTATE_SHIFT (8) |
| 69 | #define MHISTATUS_SYSERR_MASK (0x4) |
| 70 | #define MHISTATUS_SYSERR_SHIFT (2) |
| 71 | #define MHISTATUS_READY_MASK (0x1) |
| 72 | #define MHISTATUS_READY_SHIFT (0) |
| 73 | |
| 74 | #define CCABAP_LOWER (0x58) |
| 75 | #define CCABAP_LOWER_CCABAP_LOWER_MASK (0xFFFFFFFF) |
| 76 | #define CCABAP_LOWER_CCABAP_LOWER_SHIFT (0) |
| 77 | |
| 78 | #define CCABAP_HIGHER (0x5C) |
| 79 | #define CCABAP_HIGHER_CCABAP_HIGHER_MASK (0xFFFFFFFF) |
| 80 | #define CCABAP_HIGHER_CCABAP_HIGHER_SHIFT (0) |
| 81 | |
| 82 | #define ECABAP_LOWER (0x60) |
| 83 | #define ECABAP_LOWER_ECABAP_LOWER_MASK (0xFFFFFFFF) |
| 84 | #define ECABAP_LOWER_ECABAP_LOWER_SHIFT (0) |
| 85 | |
| 86 | #define ECABAP_HIGHER (0x64) |
| 87 | #define ECABAP_HIGHER_ECABAP_HIGHER_MASK (0xFFFFFFFF) |
| 88 | #define ECABAP_HIGHER_ECABAP_HIGHER_SHIFT (0) |
| 89 | |
| 90 | #define CRCBAP_LOWER (0x68) |
| 91 | #define CRCBAP_LOWER_CRCBAP_LOWER_MASK (0xFFFFFFFF) |
| 92 | #define CRCBAP_LOWER_CRCBAP_LOWER_SHIFT (0) |
| 93 | |
| 94 | #define CRCBAP_HIGHER (0x6C) |
| 95 | #define CRCBAP_HIGHER_CRCBAP_HIGHER_MASK (0xFFFFFFFF) |
| 96 | #define CRCBAP_HIGHER_CRCBAP_HIGHER_SHIFT (0) |
| 97 | |
| 98 | #define CRDB_LOWER (0x70) |
| 99 | #define CRDB_LOWER_CRDB_LOWER_MASK (0xFFFFFFFF) |
| 100 | #define CRDB_LOWER_CRDB_LOWER_SHIFT (0) |
| 101 | |
| 102 | #define CRDB_HIGHER (0x74) |
| 103 | #define CRDB_HIGHER_CRDB_HIGHER_MASK (0xFFFFFFFF) |
| 104 | #define CRDB_HIGHER_CRDB_HIGHER_SHIFT (0) |
| 105 | |
| 106 | #define MHICTRLBASE_LOWER (0x80) |
| 107 | #define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK (0xFFFFFFFF) |
| 108 | #define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_SHIFT (0) |
| 109 | |
| 110 | #define MHICTRLBASE_HIGHER (0x84) |
| 111 | #define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK (0xFFFFFFFF) |
| 112 | #define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_SHIFT (0) |
| 113 | |
| 114 | #define MHICTRLLIMIT_LOWER (0x88) |
| 115 | #define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK (0xFFFFFFFF) |
| 116 | #define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_SHIFT (0) |
| 117 | |
| 118 | #define MHICTRLLIMIT_HIGHER (0x8C) |
| 119 | #define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK (0xFFFFFFFF) |
| 120 | #define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_SHIFT (0) |
| 121 | |
| 122 | #define MHIDATABASE_LOWER (0x98) |
| 123 | #define MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK (0xFFFFFFFF) |
| 124 | #define MHIDATABASE_LOWER_MHIDATABASE_LOWER_SHIFT (0) |
| 125 | |
| 126 | #define MHIDATABASE_HIGHER (0x9C) |
| 127 | #define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK (0xFFFFFFFF) |
| 128 | #define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_SHIFT (0) |
| 129 | |
| 130 | #define MHIDATALIMIT_LOWER (0xA0) |
| 131 | #define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK (0xFFFFFFFF) |
| 132 | #define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_SHIFT (0) |
| 133 | |
| 134 | #define MHIDATALIMIT_HIGHER (0xA4) |
| 135 | #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK (0xFFFFFFFF) |
| 136 | #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT (0) |
| 137 | |
| 138 | /* Host request register */ |
| 139 | #define MHI_SOC_RESET_REQ_OFFSET (0xB0) |
| 140 | #define MHI_SOC_RESET_REQ BIT(0) |
| 141 | |
| 142 | /* MHI misc capability registers */ |
| 143 | #define MISC_OFFSET (0x24) |
| 144 | #define MISC_CAP_MASK (0xFFFFFFFF) |
| 145 | #define MISC_CAP_SHIFT (0) |
| 146 | |
| 147 | #define CAP_CAPID_MASK (0xFF000000) |
| 148 | #define CAP_CAPID_SHIFT (24) |
| 149 | #define CAP_NEXT_CAP_MASK (0x00FFF000) |
| 150 | #define CAP_NEXT_CAP_SHIFT (12) |
| 151 | |
| 152 | /* MHI Timesync offsets */ |
| 153 | #define TIMESYNC_CFG_OFFSET (0x00) |
| 154 | #define TIMESYNC_CFG_CAPID_MASK (CAP_CAPID_MASK) |
| 155 | #define TIMESYNC_CFG_CAPID_SHIFT (CAP_CAPID_SHIFT) |
| 156 | #define TIMESYNC_CFG_NEXT_OFF_MASK (CAP_NEXT_CAP_MASK) |
| 157 | #define TIMESYNC_CFG_NEXT_OFF_SHIFT (CAP_NEXT_CAP_SHIFT) |
| 158 | #define TIMESYNC_CFG_NUMCMD_MASK (0xFF) |
| 159 | #define TIMESYNC_CFG_NUMCMD_SHIFT (0) |
| 160 | #define TIMESYNC_DB_OFFSET (0x4) |
| 161 | #define TIMESYNC_TIME_LOW_OFFSET (0x8) |
| 162 | #define TIMESYNC_TIME_HIGH_OFFSET (0xC) |
| 163 | |
| 164 | #define TIMESYNC_CAP_ID (2) |
| 165 | |
| 166 | /* MHI Bandwidth scaling offsets */ |
| 167 | #define BW_SCALE_CFG_OFFSET (0x04) |
| 168 | #define BW_SCALE_CFG_CHAN_DB_ID_MASK (0xFE000000) |
| 169 | #define BW_SCALE_CFG_CHAN_DB_ID_SHIFT (25) |
| 170 | #define BW_SCALE_CFG_ENABLED_MASK (0x01000000) |
| 171 | #define BW_SCALE_CFG_ENABLED_SHIFT (24) |
| 172 | #define BW_SCALE_CFG_ER_ID_MASK (0x00F80000) |
| 173 | #define BW_SCALE_CFG_ER_ID_SHIFT (19) |
| 174 | |
| 175 | #define BW_SCALE_CAP_ID (3) |
| 176 | |
| 177 | /* MHI BHI offfsets */ |
| 178 | #define BHI_BHIVERSION_MINOR (0x00) |
| 179 | #define BHI_BHIVERSION_MAJOR (0x04) |
| 180 | #define BHI_IMGADDR_LOW (0x08) |
| 181 | #define BHI_IMGADDR_HIGH (0x0C) |
| 182 | #define BHI_IMGSIZE (0x10) |
| 183 | #define BHI_RSVD1 (0x14) |
| 184 | #define BHI_IMGTXDB (0x18) |
| 185 | #define BHI_TXDB_SEQNUM_BMSK (0x3FFFFFFF) |
| 186 | #define BHI_TXDB_SEQNUM_SHFT (0) |
| 187 | #define BHI_RSVD2 (0x1C) |
| 188 | #define BHI_INTVEC (0x20) |
| 189 | #define BHI_RSVD3 (0x24) |
| 190 | #define BHI_EXECENV (0x28) |
| 191 | #define BHI_STATUS (0x2C) |
| 192 | #define BHI_ERRCODE (0x30) |
| 193 | #define BHI_ERRDBG1 (0x34) |
| 194 | #define BHI_ERRDBG2 (0x38) |
| 195 | #define BHI_ERRDBG3 (0x3C) |
| 196 | #define BHI_SERIALNU (0x40) |
| 197 | #define BHI_SBLANTIROLLVER (0x44) |
| 198 | #define BHI_NUMSEG (0x48) |
| 199 | #define BHI_MSMHWID(n) (0x4C + (0x4 * n)) |
| 200 | #define BHI_OEMPKHASH(n) (0x64 + (0x4 * n)) |
| 201 | #define BHI_RSVD5 (0xC4) |
| 202 | #define BHI_STATUS_MASK (0xC0000000) |
| 203 | #define BHI_STATUS_SHIFT (30) |
| 204 | #define BHI_STATUS_ERROR (3) |
| 205 | #define BHI_STATUS_SUCCESS (2) |
| 206 | #define BHI_STATUS_RESET (0) |
| 207 | |
| 208 | /* MHI BHIE offsets */ |
| 209 | #define BHIE_MSMSOCID_OFFS (0x0000) |
| 210 | #define BHIE_TXVECADDR_LOW_OFFS (0x002C) |
| 211 | #define BHIE_TXVECADDR_HIGH_OFFS (0x0030) |
| 212 | #define BHIE_TXVECSIZE_OFFS (0x0034) |
| 213 | #define BHIE_TXVECDB_OFFS (0x003C) |
| 214 | #define BHIE_TXVECDB_SEQNUM_BMSK (0x3FFFFFFF) |
| 215 | #define BHIE_TXVECDB_SEQNUM_SHFT (0) |
| 216 | #define BHIE_TXVECSTATUS_OFFS (0x0044) |
| 217 | #define BHIE_TXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF) |
| 218 | #define BHIE_TXVECSTATUS_SEQNUM_SHFT (0) |
| 219 | #define BHIE_TXVECSTATUS_STATUS_BMSK (0xC0000000) |
| 220 | #define BHIE_TXVECSTATUS_STATUS_SHFT (30) |
| 221 | #define BHIE_TXVECSTATUS_STATUS_RESET (0x00) |
| 222 | #define BHIE_TXVECSTATUS_STATUS_XFER_COMPL (0x02) |
| 223 | #define BHIE_TXVECSTATUS_STATUS_ERROR (0x03) |
| 224 | #define BHIE_RXVECADDR_LOW_OFFS (0x0060) |
| 225 | #define BHIE_RXVECADDR_HIGH_OFFS (0x0064) |
| 226 | #define BHIE_RXVECSIZE_OFFS (0x0068) |
| 227 | #define BHIE_RXVECDB_OFFS (0x0070) |
| 228 | #define BHIE_RXVECDB_SEQNUM_BMSK (0x3FFFFFFF) |
| 229 | #define BHIE_RXVECDB_SEQNUM_SHFT (0) |
| 230 | #define BHIE_RXVECSTATUS_OFFS (0x0078) |
| 231 | #define BHIE_RXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF) |
| 232 | #define BHIE_RXVECSTATUS_SEQNUM_SHFT (0) |
| 233 | #define BHIE_RXVECSTATUS_STATUS_BMSK (0xC0000000) |
| 234 | #define BHIE_RXVECSTATUS_STATUS_SHFT (30) |
| 235 | #define BHIE_RXVECSTATUS_STATUS_RESET (0x00) |
| 236 | #define BHIE_RXVECSTATUS_STATUS_XFER_COMPL (0x02) |
| 237 | #define BHIE_RXVECSTATUS_STATUS_ERROR (0x03) |
| 238 | |
| 239 | #define SOC_HW_VERSION_OFFS (0x224) |
| 240 | #define SOC_HW_VERSION_FAM_NUM_BMSK (0xF0000000) |
| 241 | #define SOC_HW_VERSION_FAM_NUM_SHFT (28) |
| 242 | #define SOC_HW_VERSION_DEV_NUM_BMSK (0x0FFF0000) |
| 243 | #define SOC_HW_VERSION_DEV_NUM_SHFT (16) |
| 244 | #define SOC_HW_VERSION_MAJOR_VER_BMSK (0x0000FF00) |
| 245 | #define SOC_HW_VERSION_MAJOR_VER_SHFT (8) |
| 246 | #define SOC_HW_VERSION_MINOR_VER_BMSK (0x000000FF) |
| 247 | #define SOC_HW_VERSION_MINOR_VER_SHFT (0) |
| 248 | |
| 249 | /* timesync time calculations */ |
| 250 | #define LOCAL_TICKS_TO_US(x) (div_u64((x) * 100ULL, \ |
| 251 | div_u64(mhi_cntrl->local_timer_freq, 10000ULL))) |
| 252 | #define REMOTE_TICKS_TO_US(x) (div_u64((x) * 100ULL, \ |
| 253 | div_u64(mhi_cntrl->remote_timer_freq, 10000ULL))) |
| 254 | |
| 255 | struct mhi_event_ctxt { |
| 256 | u32 reserved : 8; |
| 257 | u32 intmodc : 8; |
| 258 | u32 intmodt : 16; |
| 259 | u32 ertype; |
| 260 | u32 msivec; |
| 261 | |
| 262 | u64 rbase __packed __aligned(4); |
| 263 | u64 rlen __packed __aligned(4); |
| 264 | u64 rp __packed __aligned(4); |
| 265 | u64 wp __packed __aligned(4); |
| 266 | }; |
| 267 | |
| 268 | struct mhi_chan_ctxt { |
| 269 | u32 chstate : 8; |
| 270 | u32 brstmode : 2; |
| 271 | u32 pollcfg : 6; |
| 272 | u32 reserved : 16; |
| 273 | u32 chtype; |
| 274 | u32 erindex; |
| 275 | |
| 276 | u64 rbase __packed __aligned(4); |
| 277 | u64 rlen __packed __aligned(4); |
| 278 | u64 rp __packed __aligned(4); |
| 279 | u64 wp __packed __aligned(4); |
| 280 | }; |
| 281 | |
| 282 | struct mhi_cmd_ctxt { |
| 283 | u32 reserved0; |
| 284 | u32 reserved1; |
| 285 | u32 reserved2; |
| 286 | |
| 287 | u64 rbase __packed __aligned(4); |
| 288 | u64 rlen __packed __aligned(4); |
| 289 | u64 rp __packed __aligned(4); |
| 290 | u64 wp __packed __aligned(4); |
| 291 | }; |
| 292 | |
| 293 | struct mhi_tre { |
| 294 | u64 ptr; |
| 295 | u32 dword[2]; |
| 296 | }; |
| 297 | |
| 298 | struct bhi_vec_entry { |
| 299 | u64 dma_addr; |
| 300 | u64 size; |
| 301 | }; |
| 302 | |
| 303 | enum mhi_cmd_type { |
| 304 | MHI_CMD_TYPE_NOP = 1, |
| 305 | MHI_CMD_TYPE_RESET = 16, |
| 306 | MHI_CMD_TYPE_STOP = 17, |
| 307 | MHI_CMD_TYPE_START = 18, |
| 308 | MHI_CMD_TYPE_TSYNC = 24, |
| 309 | }; |
| 310 | |
| 311 | /* no operation command */ |
| 312 | #define MHI_TRE_CMD_NOOP_PTR (0) |
| 313 | #define MHI_TRE_CMD_NOOP_DWORD0 (0) |
| 314 | #define MHI_TRE_CMD_NOOP_DWORD1 (MHI_CMD_TYPE_NOP << 16) |
| 315 | |
| 316 | /* channel reset command */ |
| 317 | #define MHI_TRE_CMD_RESET_PTR (0) |
| 318 | #define MHI_TRE_CMD_RESET_DWORD0 (0) |
| 319 | #define MHI_TRE_CMD_RESET_DWORD1(chid) ((chid << 24) | \ |
| 320 | (MHI_CMD_TYPE_RESET << 16)) |
| 321 | |
| 322 | /* channel stop command */ |
| 323 | #define MHI_TRE_CMD_STOP_PTR (0) |
| 324 | #define MHI_TRE_CMD_STOP_DWORD0 (0) |
| 325 | #define MHI_TRE_CMD_STOP_DWORD1(chid) ((chid << 24) | (MHI_CMD_TYPE_STOP << 16)) |
| 326 | |
| 327 | /* channel start command */ |
| 328 | #define MHI_TRE_CMD_START_PTR (0) |
| 329 | #define MHI_TRE_CMD_START_DWORD0 (0) |
| 330 | #define MHI_TRE_CMD_START_DWORD1(chid) ((chid << 24) | \ |
| 331 | (MHI_CMD_TYPE_START << 16)) |
| 332 | |
| 333 | /* time sync cfg command */ |
| 334 | #define MHI_TRE_CMD_TSYNC_CFG_PTR (0) |
| 335 | #define MHI_TRE_CMD_TSYNC_CFG_DWORD0 (0) |
| 336 | #define MHI_TRE_CMD_TSYNC_CFG_DWORD1(er) ((MHI_CMD_TYPE_TSYNC << 16) | \ |
| 337 | (er << 24)) |
| 338 | |
| 339 | #define MHI_TRE_GET_CMD_CHID(tre) (((tre)->dword[1] >> 24) & 0xFF) |
| 340 | #define MHI_TRE_GET_CMD_TYPE(tre) (((tre)->dword[1] >> 16) & 0xFF) |
| 341 | |
| 342 | /* event descriptor macros */ |
| 343 | #define MHI_TRE_EV_PTR(ptr) (ptr) |
| 344 | #define MHI_TRE_EV_DWORD0(code, len) ((code << 24) | len) |
| 345 | #define MHI_TRE_EV_DWORD1(chid, type) ((chid << 24) | (type << 16)) |
| 346 | #define MHI_TRE_GET_EV_PTR(tre) ((tre)->ptr) |
| 347 | #define MHI_TRE_GET_EV_CODE(tre) (((tre)->dword[0] >> 24) & 0xFF) |
| 348 | #define MHI_TRE_GET_EV_LEN(tre) ((tre)->dword[0] & 0xFFFF) |
| 349 | #define MHI_TRE_GET_EV_CHID(tre) (((tre)->dword[1] >> 24) & 0xFF) |
| 350 | #define MHI_TRE_GET_EV_TYPE(tre) (((tre)->dword[1] >> 16) & 0xFF) |
| 351 | #define MHI_TRE_GET_EV_STATE(tre) (((tre)->dword[0] >> 24) & 0xFF) |
| 352 | #define MHI_TRE_GET_EV_EXECENV(tre) (((tre)->dword[0] >> 24) & 0xFF) |
| 353 | #define MHI_TRE_GET_EV_TSYNC_SEQ(tre) ((tre)->dword[0]) |
| 354 | #define MHI_TRE_GET_EV_TIME(tre) ((tre)->ptr) |
| 355 | #define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits((tre)->ptr) |
| 356 | #define MHI_TRE_GET_EV_VEID(tre) (((tre)->dword[0] >> 16) & 0xFF) |
| 357 | #define MHI_TRE_GET_EV_LINKSPEED(tre) (((tre)->dword[1] >> 24) & 0xFF) |
| 358 | #define MHI_TRE_GET_EV_LINKWIDTH(tre) ((tre)->dword[0] & 0xFF) |
| 359 | #define MHI_TRE_GET_EV_BW_REQ_SEQ(tre) (((tre)->dword[0] >> 8) & 0xFF) |
| 360 | |
| 361 | /* transfer descriptor macros */ |
| 362 | #define MHI_TRE_DATA_PTR(ptr) (ptr) |
| 363 | #define MHI_TRE_DATA_DWORD0(len) (len & MHI_MAX_MTU) |
| 364 | #define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) ((2 << 16) | (bei << 10) \ |
| 365 | | (ieot << 9) | (ieob << 8) | chain) |
| 366 | |
| 367 | /* rsc transfer descriptor macros */ |
| 368 | #define MHI_RSCTRE_DATA_PTR(ptr, len) (((u64)len << 48) | ptr) |
| 369 | #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) |
| 370 | #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) |
| 371 | |
| 372 | enum MHI_CMD { |
| 373 | MHI_CMD_RESET_CHAN, |
| 374 | MHI_CMD_START_CHAN, |
| 375 | MHI_CMD_TIMSYNC_CFG, |
| 376 | }; |
| 377 | |
| 378 | enum MHI_PKT_TYPE { |
| 379 | MHI_PKT_TYPE_INVALID = 0x0, |
| 380 | MHI_PKT_TYPE_NOOP_CMD = 0x1, |
| 381 | MHI_PKT_TYPE_TRANSFER = 0x2, |
| 382 | MHI_PKT_TYPE_COALESCING = 0x8, |
| 383 | MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10, |
| 384 | MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11, |
| 385 | MHI_PKT_TYPE_START_CHAN_CMD = 0x12, |
| 386 | MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20, |
| 387 | MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21, |
| 388 | MHI_PKT_TYPE_TX_EVENT = 0x22, |
| 389 | MHI_PKT_TYPE_RSC_TX_EVENT = 0x28, |
| 390 | MHI_PKT_TYPE_EE_EVENT = 0x40, |
| 391 | MHI_PKT_TYPE_TSYNC_EVENT = 0x48, |
| 392 | MHI_PKT_TYPE_BW_REQ_EVENT = 0x50, |
| 393 | MHI_PKT_TYPE_STALE_EVENT, /* internal event */ |
| 394 | }; |
| 395 | |
| 396 | /* MHI transfer completion events */ |
| 397 | enum MHI_EV_CCS { |
| 398 | MHI_EV_CC_INVALID = 0x0, |
| 399 | MHI_EV_CC_SUCCESS = 0x1, |
| 400 | MHI_EV_CC_EOT = 0x2, |
| 401 | MHI_EV_CC_OVERFLOW = 0x3, |
| 402 | MHI_EV_CC_EOB = 0x4, |
| 403 | MHI_EV_CC_OOB = 0x5, |
| 404 | MHI_EV_CC_DB_MODE = 0x6, |
| 405 | MHI_EV_CC_UNDEFINED_ERR = 0x10, |
| 406 | MHI_EV_CC_BAD_TRE = 0x11, |
| 407 | }; |
| 408 | |
| 409 | enum MHI_CH_STATE { |
| 410 | MHI_CH_STATE_DISABLED = 0x0, |
| 411 | MHI_CH_STATE_ENABLED = 0x1, |
| 412 | MHI_CH_STATE_RUNNING = 0x2, |
| 413 | MHI_CH_STATE_SUSPENDED = 0x3, |
| 414 | MHI_CH_STATE_STOP = 0x4, |
| 415 | MHI_CH_STATE_ERROR = 0x5, |
| 416 | }; |
| 417 | |
| 418 | enum MHI_BRSTMODE { |
| 419 | MHI_BRSTMODE_DISABLE = 0x2, |
| 420 | MHI_BRSTMODE_ENABLE = 0x3, |
| 421 | }; |
| 422 | |
| 423 | #define MHI_INVALID_BRSTMODE(mode) (mode != MHI_BRSTMODE_DISABLE && \ |
| 424 | mode != MHI_BRSTMODE_ENABLE) |
| 425 | |
| 426 | extern const char * const mhi_ee_str[MHI_EE_MAX]; |
| 427 | #define TO_MHI_EXEC_STR(ee) (((ee) >= MHI_EE_MAX) ? \ |
| 428 | "INVALID_EE" : mhi_ee_str[ee]) |
| 429 | |
| 430 | #define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \ |
| 431 | ee == MHI_EE_EDL) |
| 432 | |
| 433 | #define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW) |
| 434 | |
| 435 | enum MHI_ST_TRANSITION { |
| 436 | MHI_ST_TRANSITION_PBL, |
| 437 | MHI_ST_TRANSITION_READY, |
| 438 | MHI_ST_TRANSITION_SBL, |
| 439 | MHI_ST_TRANSITION_MISSION_MODE, |
| 440 | MHI_ST_TRANSITION_MAX, |
| 441 | }; |
| 442 | |
| 443 | extern const char * const mhi_state_tran_str[MHI_ST_TRANSITION_MAX]; |
| 444 | #define TO_MHI_STATE_TRANS_STR(state) (((state) >= MHI_ST_TRANSITION_MAX) ? \ |
| 445 | "INVALID_STATE" : mhi_state_tran_str[state]) |
| 446 | |
| 447 | extern const char * const mhi_state_str[MHI_STATE_MAX]; |
| 448 | #define TO_MHI_STATE_STR(state) ((state >= MHI_STATE_MAX || \ |
| 449 | !mhi_state_str[state]) ? \ |
| 450 | "INVALID_STATE" : mhi_state_str[state]) |
| 451 | |
| 452 | enum { |
| 453 | MHI_PM_BIT_DISABLE, |
| 454 | MHI_PM_BIT_POR, |
| 455 | MHI_PM_BIT_M0, |
| 456 | MHI_PM_BIT_M2, |
| 457 | MHI_PM_BIT_M3_ENTER, |
| 458 | MHI_PM_BIT_M3, |
| 459 | MHI_PM_BIT_M3_EXIT, |
| 460 | MHI_PM_BIT_FW_DL_ERR, |
| 461 | MHI_PM_BIT_SYS_ERR_DETECT, |
| 462 | MHI_PM_BIT_SYS_ERR_PROCESS, |
| 463 | MHI_PM_BIT_SHUTDOWN_PROCESS, |
| 464 | MHI_PM_BIT_LD_ERR_FATAL_DETECT, |
| 465 | MHI_PM_BIT_MAX |
| 466 | }; |
| 467 | |
| 468 | /* internal power states */ |
| 469 | enum MHI_PM_STATE { |
| 470 | MHI_PM_DISABLE = BIT(MHI_PM_BIT_DISABLE), /* MHI is not enabled */ |
| 471 | MHI_PM_POR = BIT(MHI_PM_BIT_POR), /* reset state */ |
| 472 | MHI_PM_M0 = BIT(MHI_PM_BIT_M0), |
| 473 | MHI_PM_M2 = BIT(MHI_PM_BIT_M2), |
| 474 | MHI_PM_M3_ENTER = BIT(MHI_PM_BIT_M3_ENTER), |
| 475 | MHI_PM_M3 = BIT(MHI_PM_BIT_M3), |
| 476 | MHI_PM_M3_EXIT = BIT(MHI_PM_BIT_M3_EXIT), |
| 477 | /* firmware download failure state */ |
| 478 | MHI_PM_FW_DL_ERR = BIT(MHI_PM_BIT_FW_DL_ERR), |
| 479 | MHI_PM_SYS_ERR_DETECT = BIT(MHI_PM_BIT_SYS_ERR_DETECT), |
| 480 | MHI_PM_SYS_ERR_PROCESS = BIT(MHI_PM_BIT_SYS_ERR_PROCESS), |
| 481 | MHI_PM_SHUTDOWN_PROCESS = BIT(MHI_PM_BIT_SHUTDOWN_PROCESS), |
| 482 | /* link not accessible */ |
| 483 | MHI_PM_LD_ERR_FATAL_DETECT = BIT(MHI_PM_BIT_LD_ERR_FATAL_DETECT), |
| 484 | }; |
| 485 | |
| 486 | #define MHI_REG_ACCESS_VALID(pm_state) ((pm_state & (MHI_PM_POR | MHI_PM_M0 | \ |
| 487 | MHI_PM_M2 | MHI_PM_M3_ENTER | MHI_PM_M3_EXIT | \ |
| 488 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SYS_ERR_PROCESS | \ |
| 489 | MHI_PM_SHUTDOWN_PROCESS | MHI_PM_FW_DL_ERR))) |
| 490 | #define MHI_PM_IN_ERROR_STATE(pm_state) (pm_state >= MHI_PM_FW_DL_ERR) |
| 491 | #define MHI_PM_IN_FATAL_STATE(pm_state) (pm_state == MHI_PM_LD_ERR_FATAL_DETECT) |
| 492 | #define MHI_DB_ACCESS_VALID(mhi_cntrl) (mhi_cntrl->pm_state & \ |
| 493 | mhi_cntrl->db_access) |
| 494 | #define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \ |
| 495 | MHI_PM_M2 | MHI_PM_M3_EXIT)) |
| 496 | #define MHI_WAKE_DB_SET_VALID(pm_state) (pm_state & MHI_PM_M2) |
| 497 | #define MHI_WAKE_DB_FORCE_SET_VALID(pm_state) MHI_WAKE_DB_CLEAR_VALID(pm_state) |
| 498 | #define MHI_EVENT_ACCESS_INVALID(pm_state) (pm_state == MHI_PM_DISABLE || \ |
| 499 | MHI_PM_IN_ERROR_STATE(pm_state)) |
| 500 | #define MHI_PM_IN_SUSPEND_STATE(pm_state) (pm_state & \ |
| 501 | (MHI_PM_M3_ENTER | MHI_PM_M3)) |
| 502 | |
| 503 | /* accepted buffer type for the channel */ |
| 504 | enum MHI_XFER_TYPE { |
| 505 | MHI_XFER_BUFFER, |
| 506 | MHI_XFER_SKB, |
| 507 | MHI_XFER_SCLIST, |
| 508 | MHI_XFER_NOP, /* CPU offload channel, host does not accept transfer */ |
| 509 | MHI_XFER_DMA, /* receive dma address, already mapped by client */ |
| 510 | MHI_XFER_RSC_DMA, /* RSC type, accept premapped buffer */ |
| 511 | }; |
| 512 | |
| 513 | #define NR_OF_CMD_RINGS (1) |
| 514 | #define CMD_EL_PER_RING (128) |
| 515 | #define PRIMARY_CMD_RING (0) |
| 516 | #define MHI_BW_SCALE_CHAN_DB (126) |
| 517 | #define MHI_DEV_WAKE_DB (127) |
| 518 | #define MHI_MAX_MTU (0xffff) |
| 519 | |
| 520 | #define MHI_BW_SCALE_SETUP(er_index) ((MHI_BW_SCALE_CHAN_DB << \ |
| 521 | BW_SCALE_CFG_CHAN_DB_ID_SHIFT) & BW_SCALE_CFG_CHAN_DB_ID_MASK | \ |
| 522 | (1 << BW_SCALE_CFG_ENABLED_SHIFT) & BW_SCALE_CFG_ENABLED_MASK | \ |
| 523 | ((er_index) << BW_SCALE_CFG_ER_ID_SHIFT) & BW_SCALE_CFG_ER_ID_MASK) |
| 524 | |
| 525 | #define MHI_BW_SCALE_RESULT(status, seq) ((status & 0xF) << 8 | (seq & 0xFF)) |
| 526 | #define MHI_BW_SCALE_NACK 0xF |
| 527 | |
| 528 | enum MHI_ER_TYPE { |
| 529 | MHI_ER_TYPE_INVALID = 0x0, |
| 530 | MHI_ER_TYPE_VALID = 0x1, |
| 531 | }; |
| 532 | |
| 533 | enum mhi_er_priority { |
| 534 | MHI_ER_PRIORITY_HIGH, |
| 535 | MHI_ER_PRIORITY_MEDIUM, |
| 536 | MHI_ER_PRIORITY_LOW, |
| 537 | }; |
| 538 | |
| 539 | #define IS_MHI_ER_PRIORITY_LOW(ev) (ev->priority >= MHI_ER_PRIORITY_LOW) |
| 540 | #define IS_MHI_ER_PRIORITY_HIGH(ev) (ev->priority == MHI_ER_PRIORITY_HIGH) |
| 541 | |
| 542 | enum mhi_er_data_type { |
| 543 | MHI_ER_DATA_ELEMENT_TYPE, |
| 544 | MHI_ER_CTRL_ELEMENT_TYPE, |
| 545 | MHI_ER_TSYNC_ELEMENT_TYPE, |
| 546 | MHI_ER_BW_SCALE_ELEMENT_TYPE, |
| 547 | MHI_ER_DATA_TYPE_MAX = MHI_ER_BW_SCALE_ELEMENT_TYPE, |
| 548 | }; |
| 549 | |
| 550 | enum mhi_ch_ee_mask { |
| 551 | MHI_CH_EE_PBL = BIT(MHI_EE_PBL), |
| 552 | MHI_CH_EE_SBL = BIT(MHI_EE_SBL), |
| 553 | MHI_CH_EE_AMSS = BIT(MHI_EE_AMSS), |
| 554 | MHI_CH_EE_RDDM = BIT(MHI_EE_RDDM), |
| 555 | MHI_CH_EE_PTHRU = BIT(MHI_EE_PTHRU), |
| 556 | MHI_CH_EE_WFW = BIT(MHI_EE_WFW), |
| 557 | MHI_CH_EE_EDL = BIT(MHI_EE_EDL), |
| 558 | }; |
| 559 | |
| 560 | enum mhi_ch_type { |
| 561 | MHI_CH_TYPE_INVALID = 0, |
| 562 | MHI_CH_TYPE_OUTBOUND = DMA_TO_DEVICE, |
| 563 | MHI_CH_TYPE_INBOUND = DMA_FROM_DEVICE, |
| 564 | MHI_CH_TYPE_INBOUND_COALESCED = 3, |
| 565 | }; |
| 566 | |
| 567 | struct db_cfg { |
| 568 | bool reset_req; |
| 569 | bool db_mode; |
| 570 | u32 pollcfg; |
| 571 | enum MHI_BRSTMODE brstmode; |
| 572 | dma_addr_t db_val; |
| 573 | void (*process_db)(struct mhi_controller *mhi_cntrl, |
| 574 | struct db_cfg *db_cfg, void __iomem *io_addr, |
| 575 | dma_addr_t db_val); |
| 576 | }; |
| 577 | |
| 578 | struct mhi_pm_transitions { |
| 579 | enum MHI_PM_STATE from_state; |
| 580 | u32 to_states; |
| 581 | }; |
| 582 | |
| 583 | struct state_transition { |
| 584 | struct list_head node; |
| 585 | enum MHI_ST_TRANSITION state; |
| 586 | }; |
| 587 | |
| 588 | struct mhi_ctxt { |
| 589 | struct mhi_event_ctxt *er_ctxt; |
| 590 | struct mhi_chan_ctxt *chan_ctxt; |
| 591 | struct mhi_cmd_ctxt *cmd_ctxt; |
| 592 | dma_addr_t er_ctxt_addr; |
| 593 | dma_addr_t chan_ctxt_addr; |
| 594 | dma_addr_t cmd_ctxt_addr; |
| 595 | }; |
| 596 | |
| 597 | struct mhi_ring { |
| 598 | dma_addr_t dma_handle; |
| 599 | dma_addr_t iommu_base; |
| 600 | u64 *ctxt_wp; /* point to ctxt wp */ |
| 601 | void *pre_aligned; |
| 602 | void *base; |
| 603 | void *rp; |
| 604 | void *wp; |
| 605 | size_t el_size; |
| 606 | size_t len; |
| 607 | size_t elements; |
| 608 | size_t alloc_size; |
| 609 | void __iomem *db_addr; |
| 610 | }; |
| 611 | |
| 612 | struct mhi_cmd { |
| 613 | struct mhi_ring ring; |
| 614 | spinlock_t lock; |
| 615 | }; |
| 616 | |
| 617 | struct mhi_buf_info { |
| 618 | dma_addr_t p_addr; |
| 619 | void *v_addr; |
| 620 | void *bb_addr; |
| 621 | void *wp; |
| 622 | size_t len; |
| 623 | void *cb_buf; |
| 624 | bool used; /* indicate element is free to use */ |
| 625 | bool pre_mapped; /* already pre-mapped by client */ |
| 626 | enum dma_data_direction dir; |
| 627 | }; |
| 628 | |
| 629 | struct mhi_event { |
| 630 | struct list_head node; |
| 631 | u32 er_index; |
| 632 | u32 intmod; |
| 633 | u32 msi; |
| 634 | int chan; /* this event ring is dedicated to a channel */ |
| 635 | enum mhi_er_priority priority; |
| 636 | enum mhi_er_data_type data_type; |
| 637 | struct mhi_ring ring; |
| 638 | struct db_cfg db_cfg; |
| 639 | bool hw_ring; |
| 640 | bool cl_manage; |
| 641 | bool offload_ev; /* managed by a device driver */ |
| 642 | bool request_irq; /* has dedicated interrupt handler */ |
| 643 | spinlock_t lock; |
| 644 | struct mhi_chan *mhi_chan; /* dedicated to channel */ |
| 645 | struct tasklet_struct task; |
| 646 | int (*process_event)(struct mhi_controller *mhi_cntrl, |
| 647 | struct mhi_event *mhi_event, |
| 648 | u32 event_quota); |
| 649 | struct mhi_controller *mhi_cntrl; |
| 650 | }; |
| 651 | |
| 652 | struct mhi_chan { |
| 653 | u32 chan; |
| 654 | const char *name; |
| 655 | /* |
| 656 | * important, when consuming increment tre_ring first, when releasing |
| 657 | * decrement buf_ring first. If tre_ring has space, buf_ring |
| 658 | * guranteed to have space so we do not need to check both rings. |
| 659 | */ |
| 660 | struct mhi_ring buf_ring; |
| 661 | struct mhi_ring tre_ring; |
| 662 | u32 er_index; |
| 663 | u32 intmod; |
| 664 | enum mhi_ch_type type; |
| 665 | enum dma_data_direction dir; |
| 666 | struct db_cfg db_cfg; |
| 667 | u32 ee_mask; |
| 668 | enum MHI_XFER_TYPE xfer_type; |
| 669 | enum MHI_CH_STATE ch_state; |
| 670 | enum MHI_EV_CCS ccs; |
| 671 | bool lpm_notify; |
| 672 | bool configured; |
| 673 | bool offload_ch; |
| 674 | bool pre_alloc; |
| 675 | bool auto_start; |
| 676 | bool wake_capable; /* channel should wake up system */ |
| 677 | /* functions that generate the transfer ring elements */ |
| 678 | int (*gen_tre)(struct mhi_controller *, struct mhi_chan *, void *, |
| 679 | void *, size_t, enum MHI_FLAGS); |
| 680 | int (*queue_xfer)(struct mhi_device *, struct mhi_chan *, void *, |
| 681 | size_t, enum MHI_FLAGS); |
| 682 | /* xfer call back */ |
| 683 | struct mhi_device *mhi_dev; |
| 684 | void (*xfer_cb)(struct mhi_device *, struct mhi_result *); |
| 685 | struct mutex mutex; |
| 686 | struct completion completion; |
| 687 | rwlock_t lock; |
| 688 | struct list_head node; |
| 689 | }; |
| 690 | |
| 691 | struct tsync_node { |
| 692 | struct list_head node; |
| 693 | u32 sequence; |
| 694 | u64 local_time; |
| 695 | u64 remote_time; |
| 696 | struct mhi_device *mhi_dev; |
| 697 | void (*cb_func)(struct mhi_device *mhi_dev, u32 sequence, |
| 698 | u64 local_time, u64 remote_time); |
| 699 | }; |
| 700 | |
| 701 | struct mhi_timesync { |
| 702 | u32 er_index; |
| 703 | void __iomem *db; |
| 704 | void __iomem *time_reg; |
| 705 | enum MHI_EV_CCS ccs; |
| 706 | struct completion completion; |
| 707 | spinlock_t lock; /* list protection */ |
| 708 | struct mutex lpm_mutex; /* lpm protection */ |
| 709 | struct list_head head; |
| 710 | }; |
| 711 | |
| 712 | struct mhi_bus { |
| 713 | struct list_head controller_list; |
| 714 | struct mutex lock; |
| 715 | }; |
| 716 | |
| 717 | /* default MHI timeout */ |
| 718 | #define MHI_TIMEOUT_MS (1000) |
| 719 | extern struct mhi_bus mhi_bus; |
| 720 | |
| 721 | /* debug fs related functions */ |
| 722 | int mhi_debugfs_mhi_chan_show(struct seq_file *m, void *d); |
| 723 | int mhi_debugfs_mhi_event_show(struct seq_file *m, void *d); |
| 724 | int mhi_debugfs_mhi_states_show(struct seq_file *m, void *d); |
| 725 | int mhi_debugfs_trigger_reset(void *data, u64 val); |
| 726 | |
| 727 | void mhi_deinit_debugfs(struct mhi_controller *mhi_cntrl); |
| 728 | void mhi_init_debugfs(struct mhi_controller *mhi_cntrl); |
| 729 | |
| 730 | /* power management apis */ |
| 731 | enum MHI_PM_STATE __must_check mhi_tryset_pm_state( |
| 732 | struct mhi_controller *mhi_cntrl, |
| 733 | enum MHI_PM_STATE state); |
| 734 | const char *to_mhi_pm_state_str(enum MHI_PM_STATE state); |
| 735 | void mhi_reset_chan(struct mhi_controller *mhi_cntrl, |
| 736 | struct mhi_chan *mhi_chan); |
| 737 | enum mhi_ee mhi_get_exec_env(struct mhi_controller *mhi_cntrl); |
| 738 | int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, |
| 739 | enum MHI_ST_TRANSITION state); |
| 740 | void mhi_pm_st_worker(struct work_struct *work); |
| 741 | void mhi_fw_load_worker(struct work_struct *work); |
| 742 | void mhi_pm_sys_err_worker(struct work_struct *work); |
| 743 | void mhi_low_priority_worker(struct work_struct *work); |
| 744 | int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl); |
| 745 | void mhi_ctrl_ev_task(unsigned long data); |
| 746 | int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl); |
| 747 | void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl); |
| 748 | int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl); |
| 749 | void mhi_notify(struct mhi_device *mhi_dev, enum MHI_CB cb_reason); |
| 750 | int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, |
| 751 | struct mhi_event *mhi_event, u32 event_quota); |
| 752 | int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, |
| 753 | struct mhi_event *mhi_event, u32 event_quota); |
| 754 | int mhi_process_tsync_event_ring(struct mhi_controller *mhi_cntrl, |
| 755 | struct mhi_event *mhi_event, u32 event_quota); |
| 756 | int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, |
| 757 | struct mhi_event *mhi_event, u32 event_quota); |
| 758 | int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, |
| 759 | enum MHI_CMD cmd); |
| 760 | int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl); |
| 761 | |
| 762 | /* queue transfer buffer */ |
| 763 | int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, |
| 764 | void *buf, void *cb, size_t buf_len, enum MHI_FLAGS flags); |
| 765 | int mhi_queue_buf(struct mhi_device *mhi_dev, struct mhi_chan *mhi_chan, |
| 766 | void *buf, size_t len, enum MHI_FLAGS mflags); |
| 767 | int mhi_queue_skb(struct mhi_device *mhi_dev, struct mhi_chan *mhi_chan, |
| 768 | void *buf, size_t len, enum MHI_FLAGS mflags); |
| 769 | int mhi_queue_sclist(struct mhi_device *mhi_dev, struct mhi_chan *mhi_chan, |
| 770 | void *buf, size_t len, enum MHI_FLAGS mflags); |
| 771 | int mhi_queue_nop(struct mhi_device *mhi_dev, struct mhi_chan *mhi_chan, |
| 772 | void *buf, size_t len, enum MHI_FLAGS mflags); |
| 773 | int mhi_queue_dma(struct mhi_device *mhi_dev, struct mhi_chan *mhi_chan, |
| 774 | void *buf, size_t len, enum MHI_FLAGS mflags); |
| 775 | |
| 776 | /* register access methods */ |
| 777 | void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg, |
| 778 | void __iomem *db_addr, dma_addr_t wp); |
| 779 | void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, |
| 780 | struct db_cfg *db_mode, void __iomem *db_addr, |
| 781 | dma_addr_t wp); |
| 782 | int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, |
| 783 | void __iomem *base, u32 offset, u32 *out); |
| 784 | int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, |
| 785 | void __iomem *base, u32 offset, u32 mask, |
| 786 | u32 shift, u32 *out); |
| 787 | void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, |
| 788 | u32 offset, u32 val); |
| 789 | void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, |
| 790 | u32 offset, u32 mask, u32 shift, u32 val); |
| 791 | void mhi_ring_er_db(struct mhi_event *mhi_event); |
| 792 | void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, |
| 793 | dma_addr_t wp); |
| 794 | void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd); |
| 795 | void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, |
| 796 | struct mhi_chan *mhi_chan); |
| 797 | int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, u32 capability, |
| 798 | u32 *offset); |
| 799 | void *mhi_to_virtual(struct mhi_ring *ring, dma_addr_t addr); |
| 800 | int mhi_init_timesync(struct mhi_controller *mhi_cntrl); |
| 801 | int mhi_create_timesync_sysfs(struct mhi_controller *mhi_cntrl); |
| 802 | void mhi_destroy_timesync(struct mhi_controller *mhi_cntrl); |
| 803 | int mhi_create_vote_sysfs(struct mhi_controller *mhi_cntrl); |
| 804 | void mhi_destroy_vote_sysfs(struct mhi_controller *mhi_cntrl); |
| 805 | int mhi_early_notify_device(struct device *dev, void *data); |
| 806 | |
| 807 | /* timesync log support */ |
| 808 | static inline void mhi_timesync_log(struct mhi_controller *mhi_cntrl) |
| 809 | { |
| 810 | struct mhi_timesync *mhi_tsync = mhi_cntrl->mhi_tsync; |
| 811 | |
| 812 | if (mhi_tsync && mhi_cntrl->tsync_log) |
| 813 | mhi_cntrl->tsync_log(mhi_cntrl, |
| 814 | readq_no_log(mhi_tsync->time_reg)); |
| 815 | } |
| 816 | |
| 817 | /* memory allocation methods */ |
| 818 | static inline void *mhi_alloc_coherent(struct mhi_controller *mhi_cntrl, |
| 819 | size_t size, |
| 820 | dma_addr_t *dma_handle, |
| 821 | gfp_t gfp) |
| 822 | { |
| 823 | void *buf = dma_zalloc_coherent(mhi_cntrl->dev, size, dma_handle, gfp); |
| 824 | |
| 825 | if (buf) |
| 826 | atomic_add(size, &mhi_cntrl->alloc_size); |
| 827 | |
| 828 | return buf; |
| 829 | } |
| 830 | static inline void mhi_free_coherent(struct mhi_controller *mhi_cntrl, |
| 831 | size_t size, |
| 832 | void *vaddr, |
| 833 | dma_addr_t dma_handle) |
| 834 | { |
| 835 | atomic_sub(size, &mhi_cntrl->alloc_size); |
| 836 | dma_free_coherent(mhi_cntrl->dev, size, vaddr, dma_handle); |
| 837 | } |
| 838 | struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl); |
| 839 | static inline void mhi_dealloc_device(struct mhi_controller *mhi_cntrl, |
| 840 | struct mhi_device *mhi_dev) |
| 841 | { |
| 842 | kfree(mhi_dev); |
| 843 | } |
| 844 | int mhi_destroy_device(struct device *dev, void *data); |
| 845 | void mhi_create_devices(struct mhi_controller *mhi_cntrl); |
| 846 | int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, |
| 847 | struct image_info **image_info, size_t alloc_size); |
| 848 | void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, |
| 849 | struct image_info *image_info); |
| 850 | |
| 851 | int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, |
| 852 | struct mhi_buf_info *buf_info); |
| 853 | int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, |
| 854 | struct mhi_buf_info *buf_info); |
| 855 | void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, |
| 856 | struct mhi_buf_info *buf_info); |
| 857 | void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, |
| 858 | struct mhi_buf_info *buf_info); |
| 859 | |
| 860 | /* initialization methods */ |
| 861 | int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, |
| 862 | struct mhi_chan *mhi_chan); |
| 863 | void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, |
| 864 | struct mhi_chan *mhi_chan); |
| 865 | int mhi_init_mmio(struct mhi_controller *mhi_cntrl); |
| 866 | int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl); |
| 867 | void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl); |
| 868 | int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl); |
| 869 | void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl); |
| 870 | int mhi_dtr_init(void); |
| 871 | void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, |
| 872 | struct image_info *img_info); |
| 873 | int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, |
| 874 | struct mhi_chan *mhi_chan); |
| 875 | |
| 876 | /* isr handlers */ |
| 877 | irqreturn_t mhi_msi_handlr(int irq_number, void *dev); |
| 878 | irqreturn_t mhi_intvec_threaded_handlr(int irq_number, void *dev); |
| 879 | irqreturn_t mhi_intvec_handlr(int irq_number, void *dev); |
| 880 | void mhi_ev_task(unsigned long data); |
| 881 | |
| 882 | #ifdef CONFIG_MHI_DEBUG |
| 883 | |
| 884 | #define MHI_ASSERT(cond, msg) do { \ |
| 885 | if (cond) \ |
| 886 | panic(msg); \ |
| 887 | } while (0) |
| 888 | |
| 889 | #else |
| 890 | |
| 891 | #define MHI_ASSERT(cond, msg) do { \ |
| 892 | if (cond) { \ |
| 893 | MHI_ERR(msg); \ |
| 894 | WARN_ON(cond); \ |
| 895 | } \ |
| 896 | } while (0) |
| 897 | |
| 898 | #endif |
| 899 | |
| 900 | #endif /* _MHI_INT_H */ |