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Chander Kashyap34dcedf2013-06-19 00:29:35 +09001/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "exynos5.dtsi"
Padmavathi Venna0bd03f62013-08-19 04:56:33 +090017#include "exynos5420-pinctrl.dtsi"
Chander Kashyap34dcedf2013-06-19 00:29:35 +090018/ {
19 compatible = "samsung,exynos5420";
20
Leela Krishna Amudalad81c6cb2013-06-19 22:16:06 +090021 aliases {
22 pinctrl0 = &pinctrl_0;
23 pinctrl1 = &pinctrl_1;
24 pinctrl2 = &pinctrl_2;
25 pinctrl3 = &pinctrl_3;
26 pinctrl4 = &pinctrl_4;
27 };
28
Chander Kashyap34dcedf2013-06-19 00:29:35 +090029 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0x0>;
37 clock-frequency = <1800000000>;
38 };
39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x1>;
44 clock-frequency = <1800000000>;
45 };
46
47 cpu2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0x2>;
51 clock-frequency = <1800000000>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <0x3>;
58 clock-frequency = <1800000000>;
59 };
60 };
61
62 clock: clock-controller@0x10010000 {
63 compatible = "samsung,exynos5420-clock";
64 reg = <0x10010000 0x30000>;
65 #clock-cells = <1>;
66 };
67
Arun Kumar Kf09d0622013-08-19 04:43:01 +090068 codec@11000000 {
69 compatible = "samsung,mfc-v7";
70 reg = <0x11000000 0x10000>;
71 interrupts = <0 96 0>;
72 clocks = <&clock 401>;
73 clock-names = "mfc";
74 };
75
Chander Kashyap34dcedf2013-06-19 00:29:35 +090076 mct@101C0000 {
77 compatible = "samsung,exynos4210-mct";
78 reg = <0x101C0000 0x800>;
79 interrupt-controller;
80 #interrups-cells = <1>;
81 interrupt-parent = <&mct_map>;
82 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
83 clocks = <&clock 1>, <&clock 315>;
84 clock-names = "fin_pll", "mct";
85
86 mct_map: mct-map {
87 #interrupt-cells = <1>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 interrupt-map = <0 &combiner 23 3>,
91 <1 &combiner 23 4>,
92 <2 &combiner 25 2>,
93 <3 &combiner 25 3>,
94 <4 &gic 0 120 0>,
95 <5 &gic 0 121 0>,
96 <6 &gic 0 122 0>,
97 <7 &gic 0 123 0>;
98 };
99 };
100
Yadwinder Singh Brardcfca2c2013-08-14 17:08:32 +0900101 gsc_pd: power-domain@10044000 {
102 compatible = "samsung,exynos4210-pd";
103 reg = <0x10044000 0x20>;
104 };
105
106 isp_pd: power-domain@10044020 {
107 compatible = "samsung,exynos4210-pd";
108 reg = <0x10044020 0x20>;
109 };
110
111 mfc_pd: power-domain@10044060 {
112 compatible = "samsung,exynos4210-pd";
113 reg = <0x10044060 0x20>;
114 };
115
116 disp_pd: power-domain@100440C0 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x100440C0 0x20>;
119 };
120
121 mau_pd: power-domain@100440E0 {
122 compatible = "samsung,exynos4210-pd";
123 reg = <0x100440E0 0x20>;
124 };
125
126 g2d_pd: power-domain@10044100 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x10044100 0x20>;
129 };
130
131 msc_pd: power-domain@10044120 {
132 compatible = "samsung,exynos4210-pd";
133 reg = <0x10044120 0x20>;
134 };
135
Leela Krishna Amudalad81c6cb2013-06-19 22:16:06 +0900136 pinctrl_0: pinctrl@13400000 {
137 compatible = "samsung,exynos5420-pinctrl";
138 reg = <0x13400000 0x1000>;
139 interrupts = <0 45 0>;
140
141 wakeup-interrupt-controller {
142 compatible = "samsung,exynos4210-wakeup-eint";
143 interrupt-parent = <&gic>;
144 interrupts = <0 32 0>;
145 };
146 };
147
148 pinctrl_1: pinctrl@13410000 {
149 compatible = "samsung,exynos5420-pinctrl";
150 reg = <0x13410000 0x1000>;
151 interrupts = <0 78 0>;
152 };
153
154 pinctrl_2: pinctrl@14000000 {
155 compatible = "samsung,exynos5420-pinctrl";
156 reg = <0x14000000 0x1000>;
157 interrupts = <0 46 0>;
158 };
159
160 pinctrl_3: pinctrl@14010000 {
161 compatible = "samsung,exynos5420-pinctrl";
162 reg = <0x14010000 0x1000>;
163 interrupts = <0 50 0>;
164 };
165
166 pinctrl_4: pinctrl@03860000 {
167 compatible = "samsung,exynos5420-pinctrl";
168 reg = <0x03860000 0x1000>;
169 interrupts = <0 47 0>;
170 };
171
Chander Kashyap34dcedf2013-06-19 00:29:35 +0900172 serial@12C00000 {
173 clocks = <&clock 257>, <&clock 128>;
174 clock-names = "uart", "clk_uart_baud0";
175 };
176
177 serial@12C10000 {
178 clocks = <&clock 258>, <&clock 129>;
179 clock-names = "uart", "clk_uart_baud0";
180 };
181
182 serial@12C20000 {
183 clocks = <&clock 259>, <&clock 130>;
184 clock-names = "uart", "clk_uart_baud0";
185 };
186
187 serial@12C30000 {
188 clocks = <&clock 260>, <&clock 131>;
189 clock-names = "uart", "clk_uart_baud0";
190 };
Vikas Sajjanee3381d2013-08-14 17:08:33 +0900191
Vikas Sajjan1339d332013-08-14 17:15:06 +0900192 dp_phy: video-phy@10040728 {
193 compatible = "samsung,exynos5250-dp-video-phy";
194 reg = <0x10040728 4>;
195 #phy-cells = <0>;
196 };
197
198 dp-controller@145B0000 {
199 clocks = <&clock 412>;
200 clock-names = "dp";
201 phys = <&dp_phy>;
202 phy-names = "dp";
203 };
204
Vikas Sajjanee3381d2013-08-14 17:08:33 +0900205 fimd@14400000 {
206 samsung,power-domain = <&disp_pd>;
207 clocks = <&clock 147>, <&clock 421>;
208 clock-names = "sclk_fimd", "fimd";
209 };
Chander Kashyap34dcedf2013-06-19 00:29:35 +0900210};