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Shawn Guo9a8d6d52013-04-02 14:04:45 +08001
Shawn Guo7c1da582013-02-04 23:09:16 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Troy Kiskyf89f5b42013-11-14 14:02:11 -070011#include <dt-bindings/interrupt-controller/irq.h>
Shawn Guo9a8d6d52013-04-02 14:04:45 +080012#include "imx6dl-pinfunc.h"
Shawn Guoc56009b2f2013-07-11 13:58:36 +080013#include "imx6qdl.dtsi"
Shawn Guo7c1da582013-02-04 23:09:16 +080014
15/ {
Vladimir Zapolskiy225fc6d2014-10-29 16:36:30 +020016 aliases {
17 i2c3 = &i2c4;
18 };
19
Shawn Guo7c1da582013-02-04 23:09:16 +080020 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,cortex-a9";
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010026 device_type = "cpu";
Shawn Guo7c1da582013-02-04 23:09:16 +080027 reg = <0>;
28 next-level-cache = <&L2>;
Anson Huang978ed902013-12-19 10:02:10 -050029 operating-points = <
30 /* kHz uV */
Anson Huang4c61a1e2014-12-05 16:23:49 +080031 996000 1250000
Anson Huang978ed902013-12-19 10:02:10 -050032 792000 1175000
33 396000 1075000
34 >;
35 fsl,soc-operating-points = <
36 /* ARM kHz SOC-PU uV */
37 996000 1175000
38 792000 1175000
39 396000 1175000
40 >;
41 clock-latency = <61036>; /* two CLK32 periods */
Shawn Guo8888f652014-06-15 20:36:50 +080042 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
Anson Huang978ed902013-12-19 10:02:10 -050047 clock-names = "arm", "pll2_pfd2_396m", "step",
48 "pll1_sw", "pll1_sys";
49 arm-supply = <&reg_arm>;
50 pu-supply = <&reg_pu>;
51 soc-supply = <&reg_soc>;
Shawn Guo7c1da582013-02-04 23:09:16 +080052 };
53
54 cpu@1 {
55 compatible = "arm,cortex-a9";
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010056 device_type = "cpu";
Shawn Guo7c1da582013-02-04 23:09:16 +080057 reg = <1>;
58 next-level-cache = <&L2>;
59 };
60 };
61
62 soc {
Shawn Guo951ebf52013-07-23 15:25:13 +080063 ocram: sram@00900000 {
64 compatible = "mmio-sram";
65 reg = <0x00900000 0x20000>;
Shawn Guo8888f652014-06-15 20:36:50 +080066 clocks = <&clks IMX6QDL_CLK_OCRAM>;
Shawn Guo951ebf52013-07-23 15:25:13 +080067 };
68
Shawn Guo7c1da582013-02-04 23:09:16 +080069 aips1: aips-bus@02000000 {
Shawn Guo9a8d6d52013-04-02 14:04:45 +080070 iomuxc: iomuxc@020e0000 {
71 compatible = "fsl,imx6dl-iomuxc";
Shawn Guo9a8d6d52013-04-02 14:04:45 +080072 };
73
Shawn Guo7c1da582013-02-04 23:09:16 +080074 pxp: pxp@020f0000 {
75 reg = <0x020f0000 0x4000>;
Troy Kiskyf89f5b42013-11-14 14:02:11 -070076 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guo7c1da582013-02-04 23:09:16 +080077 };
78
79 epdc: epdc@020f4000 {
80 reg = <0x020f4000 0x4000>;
Troy Kiskyf89f5b42013-11-14 14:02:11 -070081 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guo7c1da582013-02-04 23:09:16 +080082 };
83
84 lcdif: lcdif@020f8000 {
85 reg = <0x020f8000 0x4000>;
Troy Kiskyf89f5b42013-11-14 14:02:11 -070086 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guo7c1da582013-02-04 23:09:16 +080087 };
88 };
89
90 aips2: aips-bus@02100000 {
91 i2c4: i2c@021f8000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
Iain Patonb92d7762014-05-09 16:01:56 +010094 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7c1da582013-02-04 23:09:16 +080095 reg = <0x021f8000 0x4000>;
Troy Kiskyf89f5b42013-11-14 14:02:11 -070096 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guo8888f652014-06-15 20:36:50 +080097 clocks = <&clks IMX6DL_CLK_I2C4>;
Shawn Guo7c1da582013-02-04 23:09:16 +080098 status = "disabled";
99 };
100 };
101 };
Philipp Zabel4520e692014-03-05 10:21:01 +0100102
103 display-subsystem {
104 compatible = "fsl,imx-display-subsystem";
105 ports = <&ipu1_di0>, <&ipu1_di1>;
106 };
107};
108
Shawn Guo4e415ed2015-06-03 15:27:39 +0800109&gpt {
110 compatible = "fsl,imx6dl-gpt", "fsl,imx6q-gpt";
111};
112
Philipp Zabel4520e692014-03-05 10:21:01 +0100113&hdmi {
114 compatible = "fsl,imx6dl-hdmi";
Shawn Guo7c1da582013-02-04 23:09:16 +0800115};
Philipp Zabel964c8472013-06-28 14:24:16 +0200116
117&ldb {
Shawn Guo8888f652014-06-15 20:36:50 +0800118 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
119 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
120 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
Philipp Zabel964c8472013-06-28 14:24:16 +0200121 clock-names = "di0_pll", "di1_pll",
122 "di0_sel", "di1_sel",
123 "di0", "di1";
Russell Kingcf83eb22013-10-30 20:10:31 +0000124};
Philipp Zabela04a0b62014-11-11 19:12:47 -0200125
126&vpu {
127 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
128};