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gerrit-public.fairphone.software / kernel / msm-4.9 / 361a4069727b1f43583314470e877e1187b35505 / . / arch / arm / boot / dts / omap3.dtsi
blob: 69a40cfc1f29dddbd515b4f821459442787d401a [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]15#include "skeleton.dtsi"
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]16
17/ {
18 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]19 interrupt-parent = <&intc>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]20
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]21 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]28 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]30 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]34 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]36 device_type = "cpu";
37 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]38
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]43 };
44 };
45
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]46 pmu {
47 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]48 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]49 interrupts = <3>;
50 ti,hwmods = "debugss";
51 };
52
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]53 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]54 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]55 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]59 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
63
Suman Anna4c051602014-04-22 17:23:37 -0500[diff] [blame]64 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]65 compatible = "ti,iva2.2";
66 ti,hwmods = "iva";
67
68 dsp {
69 compatible = "ti,omap3-c64";
70 };
71 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]72 };
73
74 /*
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]77 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]78 * the moment, just use a fake OCP bus entry to represent the whole bus
79 * hierarchy.
80 */
81 ocp {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -0800[diff] [blame]82 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]83 reg = <0x68000000 0x10000>;
84 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 ti,hwmods = "l3_main";
89
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
113 };
114
115 scm_conf: scm_conf@270 {
116 compatible = "syscon";
117 reg = <0x270 0x330>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120
121 scm_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 };
126
127 scm_clockdomains: clockdomains {
128 };
129
130 omap3_pmx_wkup: pinmux@a00 {
131 compatible = "ti,omap3-padconf",
132 "pinctrl-single";
133 reg = <0xa00 0x5c>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;
138 pinctrl-single,register-width = <16>;
139 pinctrl-single,function-mask = <0xff1f>;
140 };
141 };
142 };
143
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]144 aes: aes@480c5000 {
145 compatible = "ti,omap3-aes";
146 ti,hwmods = "aes";
147 reg = <0x480c5000 0x50>;
148 interrupts = <0>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]149 dmas = <&sdma 65 &sdma 66>;
150 dma-names = "tx", "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]151 };
152
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]153 prm: prm@48306000 {
154 compatible = "ti,omap3-prm";
155 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500[diff] [blame]156 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]157
158 prm_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 prm_clockdomains: clockdomains {
164 };
165 };
166
167 cm: cm@48004000 {
168 compatible = "ti,omap3-cm";
169 reg = <0x48004000 0x4000>;
170
171 cm_clocks: clocks {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
175
176 cm_clockdomains: clockdomains {
177 };
178 };
179
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]180 counter32k: counter@48320000 {
181 compatible = "ti,omap-counter32k";
182 reg = <0x48320000 0x20>;
183 ti,hwmods = "counter_32k";
184 };
185
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]186 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]187 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]188 interrupt-controller;
189 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]190 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]191 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]192
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]193 sdma: dma-controller@48056000 {
194 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
195 reg = <0x48056000 0x1000>;
196 interrupts = <12>,
197 <13>,
198 <14>,
199 <15>;
200 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200[diff] [blame]201 dma-channels = <32>;
202 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]203 };
204
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]205 pbias_regulator: pbias_regulator {
206 compatible = "ti,pbias-omap";
207 reg = <0x2b0 0x4>;
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]208 syscon = <&scm_conf>;
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]209 pbias_mmc_reg: pbias_mmc_omap2430 {
210 regulator-name = "pbias_mmc_omap2430";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <3000000>;
213 };
214 };
215
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]216 gpio1: gpio@48310000 {
217 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]218 reg = <0x48310000 0x200>;
219 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]220 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]221 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]222 gpio-controller;
223 #gpio-cells = <2>;
224 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]225 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]226 };
227
228 gpio2: gpio@49050000 {
229 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]230 reg = <0x49050000 0x200>;
231 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]232 ti,hwmods = "gpio2";
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]236 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]237 };
238
239 gpio3: gpio@49052000 {
240 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]241 reg = <0x49052000 0x200>;
242 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]243 ti,hwmods = "gpio3";
244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]247 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]248 };
249
250 gpio4: gpio@49054000 {
251 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]252 reg = <0x49054000 0x200>;
253 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]254 ti,hwmods = "gpio4";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]258 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]259 };
260
261 gpio5: gpio@49056000 {
262 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]263 reg = <0x49056000 0x200>;
264 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]265 ti,hwmods = "gpio5";
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]269 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]270 };
271
272 gpio6: gpio@49058000 {
273 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]274 reg = <0x49058000 0x200>;
275 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]276 ti,hwmods = "gpio6";
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]280 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]281 };
282
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]283 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]284 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]285 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]286 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]287 dmas = <&sdma 49 &sdma 50>;
288 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]289 ti,hwmods = "uart1";
290 clock-frequency = <48000000>;
291 };
292
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]293 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]294 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]295 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]296 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]297 dmas = <&sdma 51 &sdma 52>;
298 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]299 ti,hwmods = "uart2";
300 clock-frequency = <48000000>;
301 };
302
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]303 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]304 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]305 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]306 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]307 dmas = <&sdma 53 &sdma 54>;
308 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]309 ti,hwmods = "uart3";
310 clock-frequency = <48000000>;
311 };
312
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]313 i2c1: i2c@48070000 {
314 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]315 reg = <0x48070000 0x80>;
316 interrupts = <56>;
317 dmas = <&sdma 27 &sdma 28>;
318 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]319 #address-cells = <1>;
320 #size-cells = <0>;
321 ti,hwmods = "i2c1";
322 };
323
324 i2c2: i2c@48072000 {
325 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]326 reg = <0x48072000 0x80>;
327 interrupts = <57>;
328 dmas = <&sdma 29 &sdma 30>;
329 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]330 #address-cells = <1>;
331 #size-cells = <0>;
332 ti,hwmods = "i2c2";
333 };
334
335 i2c3: i2c@48060000 {
336 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]337 reg = <0x48060000 0x80>;
338 interrupts = <61>;
339 dmas = <&sdma 25 &sdma 26>;
340 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "i2c3";
344 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]345
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]346 mailbox: mailbox@48094000 {
347 compatible = "ti,omap3-mailbox";
348 ti,hwmods = "mailbox";
349 reg = <0x48094000 0x200>;
350 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]351 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]352 ti,mbox-num-users = <2>;
353 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]354 mbox_dsp: dsp {
355 ti,mbox-tx = <0 0 0>;
356 ti,mbox-rx = <1 0 0>;
357 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]358 };
359
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]360 mcspi1: spi@48098000 {
361 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]362 reg = <0x48098000 0x100>;
363 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]364 #address-cells = <1>;
365 #size-cells = <0>;
366 ti,hwmods = "mcspi1";
367 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]368 dmas = <&sdma 35>,
369 <&sdma 36>,
370 <&sdma 37>,
371 <&sdma 38>,
372 <&sdma 39>,
373 <&sdma 40>,
374 <&sdma 41>,
375 <&sdma 42>;
376 dma-names = "tx0", "rx0", "tx1", "rx1",
377 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]378 };
379
380 mcspi2: spi@4809a000 {
381 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]382 reg = <0x4809a000 0x100>;
383 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]384 #address-cells = <1>;
385 #size-cells = <0>;
386 ti,hwmods = "mcspi2";
387 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]388 dmas = <&sdma 43>,
389 <&sdma 44>,
390 <&sdma 45>,
391 <&sdma 46>;
392 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]393 };
394
395 mcspi3: spi@480b8000 {
396 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]397 reg = <0x480b8000 0x100>;
398 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]399 #address-cells = <1>;
400 #size-cells = <0>;
401 ti,hwmods = "mcspi3";
402 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]403 dmas = <&sdma 15>,
404 <&sdma 16>,
405 <&sdma 23>,
406 <&sdma 24>;
407 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]408 };
409
410 mcspi4: spi@480ba000 {
411 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]412 reg = <0x480ba000 0x100>;
413 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]414 #address-cells = <1>;
415 #size-cells = <0>;
416 ti,hwmods = "mcspi4";
417 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]418 dmas = <&sdma 70>, <&sdma 71>;
419 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]420 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]421
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]422 hdqw1w: 1w@480b2000 {
423 compatible = "ti,omap3-1w";
424 reg = <0x480b2000 0x1000>;
425 interrupts = <58>;
426 ti,hwmods = "hdq1w";
427 };
428
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]429 mmc1: mmc@4809c000 {
430 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]431 reg = <0x4809c000 0x200>;
432 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]433 ti,hwmods = "mmc1";
434 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]435 dmas = <&sdma 61>, <&sdma 62>;
436 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]437 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]438 };
439
440 mmc2: mmc@480b4000 {
441 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]442 reg = <0x480b4000 0x200>;
443 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]444 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]445 dmas = <&sdma 47>, <&sdma 48>;
446 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]447 };
448
449 mmc3: mmc@480ad000 {
450 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]451 reg = <0x480ad000 0x200>;
452 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]453 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]454 dmas = <&sdma 77>, <&sdma 78>;
455 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]456 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]457
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]458 mmu_isp: mmu@480bd400 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]459 #iommu-cells = <0>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]460 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]461 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]462 interrupts = <24>;
463 ti,hwmods = "mmu_isp";
464 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]465 };
466
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]467 mmu_iva: mmu@5d000000 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]468 #iommu-cells = <0>;
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]469 compatible = "ti,omap2-iommu";
470 reg = <0x5d000000 0x80>;
471 interrupts = <28>;
472 ti,hwmods = "mmu_iva";
473 status = "disabled";
474 };
475
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]476 wdt2: wdt@48314000 {
477 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]478 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]479 ti,hwmods = "wd_timer2";
480 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]481
482 mcbsp1: mcbsp@48074000 {
483 compatible = "ti,omap3-mcbsp";
484 reg = <0x48074000 0xff>;
485 reg-names = "mpu";
486 interrupts = <16>, /* OCP compliant interrupt */
487 <59>, /* TX interrupt */
488 <60>; /* RX interrupt */
489 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]490 ti,buffer-size = <128>;
491 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]492 dmas = <&sdma 31>,
493 <&sdma 32>;
494 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]495 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]496 };
497
498 mcbsp2: mcbsp@49022000 {
499 compatible = "ti,omap3-mcbsp";
500 reg = <0x49022000 0xff>,
501 <0x49028000 0xff>;
502 reg-names = "mpu", "sidetone";
503 interrupts = <17>, /* OCP compliant interrupt */
504 <62>, /* TX interrupt */
505 <63>, /* RX interrupt */
506 <4>; /* Sidetone */
507 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]508 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]509 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]510 dmas = <&sdma 33>,
511 <&sdma 34>;
512 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]513 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]514 };
515
516 mcbsp3: mcbsp@49024000 {
517 compatible = "ti,omap3-mcbsp";
518 reg = <0x49024000 0xff>,
519 <0x4902a000 0xff>;
520 reg-names = "mpu", "sidetone";
521 interrupts = <22>, /* OCP compliant interrupt */
522 <89>, /* TX interrupt */
523 <90>, /* RX interrupt */
524 <5>; /* Sidetone */
525 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]526 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]527 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]528 dmas = <&sdma 17>,
529 <&sdma 18>;
530 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]531 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]532 };
533
534 mcbsp4: mcbsp@49026000 {
535 compatible = "ti,omap3-mcbsp";
536 reg = <0x49026000 0xff>;
537 reg-names = "mpu";
538 interrupts = <23>, /* OCP compliant interrupt */
539 <54>, /* TX interrupt */
540 <55>; /* RX interrupt */
541 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]542 ti,buffer-size = <128>;
543 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]544 dmas = <&sdma 19>,
545 <&sdma 20>;
546 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]547 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]548 };
549
550 mcbsp5: mcbsp@48096000 {
551 compatible = "ti,omap3-mcbsp";
552 reg = <0x48096000 0xff>;
553 reg-names = "mpu";
554 interrupts = <27>, /* OCP compliant interrupt */
555 <81>, /* TX interrupt */
556 <82>; /* RX interrupt */
557 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]558 ti,buffer-size = <128>;
559 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]560 dmas = <&sdma 21>,
561 <&sdma 22>;
562 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]563 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]564 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]565
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]566 sham: sham@480c3000 {
567 compatible = "ti,omap3-sham";
568 ti,hwmods = "sham";
569 reg = <0x480c3000 0x64>;
570 interrupts = <49>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]571 dmas = <&sdma 69>;
572 dma-names = "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]573 };
574
575 smartreflex_core: smartreflex@480cb000 {
576 compatible = "ti,omap3-smartreflex-core";
577 ti,hwmods = "smartreflex_core";
578 reg = <0x480cb000 0x400>;
579 interrupts = <19>;
580 };
581
582 smartreflex_mpu_iva: smartreflex@480c9000 {
583 compatible = "ti,omap3-smartreflex-iva";
584 ti,hwmods = "smartreflex_mpu_iva";
585 reg = <0x480c9000 0x400>;
586 interrupts = <18>;
587 };
588
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]589 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]590 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]591 reg = <0x48318000 0x400>;
592 interrupts = <37>;
593 ti,hwmods = "timer1";
594 ti,timer-alwon;
595 };
596
597 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]598 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]599 reg = <0x49032000 0x400>;
600 interrupts = <38>;
601 ti,hwmods = "timer2";
602 };
603
604 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]605 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]606 reg = <0x49034000 0x400>;
607 interrupts = <39>;
608 ti,hwmods = "timer3";
609 };
610
611 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]612 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]613 reg = <0x49036000 0x400>;
614 interrupts = <40>;
615 ti,hwmods = "timer4";
616 };
617
618 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]619 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]620 reg = <0x49038000 0x400>;
621 interrupts = <41>;
622 ti,hwmods = "timer5";
623 ti,timer-dsp;
624 };
625
626 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]627 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]628 reg = <0x4903a000 0x400>;
629 interrupts = <42>;
630 ti,hwmods = "timer6";
631 ti,timer-dsp;
632 };
633
634 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]635 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]636 reg = <0x4903c000 0x400>;
637 interrupts = <43>;
638 ti,hwmods = "timer7";
639 ti,timer-dsp;
640 };
641
642 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]643 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]644 reg = <0x4903e000 0x400>;
645 interrupts = <44>;
646 ti,hwmods = "timer8";
647 ti,timer-pwm;
648 ti,timer-dsp;
649 };
650
651 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]652 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]653 reg = <0x49040000 0x400>;
654 interrupts = <45>;
655 ti,hwmods = "timer9";
656 ti,timer-pwm;
657 };
658
659 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]660 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]661 reg = <0x48086000 0x400>;
662 interrupts = <46>;
663 ti,hwmods = "timer10";
664 ti,timer-pwm;
665 };
666
667 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]668 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]669 reg = <0x48088000 0x400>;
670 interrupts = <47>;
671 ti,hwmods = "timer11";
672 ti,timer-pwm;
673 };
674
675 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]676 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]677 reg = <0x48304000 0x400>;
678 interrupts = <95>;
679 ti,hwmods = "timer12";
680 ti,timer-alwon;
681 ti,timer-secure;
682 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]683
684 usbhstll: usbhstll@48062000 {
685 compatible = "ti,usbhs-tll";
686 reg = <0x48062000 0x1000>;
687 interrupts = <78>;
688 ti,hwmods = "usb_tll_hs";
689 };
690
691 usbhshost: usbhshost@48064000 {
692 compatible = "ti,usbhs-host";
693 reg = <0x48064000 0x400>;
694 ti,hwmods = "usb_host_hs";
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges;
698
699 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]700 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]701 reg = <0x48064400 0x400>;
702 interrupt-parent = <&intc>;
703 interrupts = <76>;
704 };
705
706 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]707 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]708 reg = <0x48064800 0x400>;
709 interrupt-parent = <&intc>;
710 interrupts = <77>;
711 };
712 };
713
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]714 gpmc: gpmc@6e000000 {
715 compatible = "ti,omap3430-gpmc";
716 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]717 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]718 interrupts = <20>;
719 gpmc,num-cs = <8>;
720 gpmc,num-waitpins = <4>;
721 #address-cells = <2>;
722 #size-cells = <1>;
723 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]724
725 usb_otg_hs: usb_otg_hs@480ab000 {
726 compatible = "ti,omap3-musb";
727 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]728 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]729 interrupt-names = "mc", "dma";
730 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]731 multipoint = <1>;
732 num-eps = <16>;
733 ram-bits = <12>;
734 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200[diff] [blame]735
736 dss: dss@48050000 {
737 compatible = "ti,omap3-dss";
738 reg = <0x48050000 0x200>;
739 status = "disabled";
740 ti,hwmods = "dss_core";
741 clocks = <&dss1_alwon_fck>;
742 clock-names = "fck";
743 #address-cells = <1>;
744 #size-cells = <1>;
745 ranges;
746
747 dispc@48050400 {
748 compatible = "ti,omap3-dispc";
749 reg = <0x48050400 0x400>;
750 interrupts = <25>;
751 ti,hwmods = "dss_dispc";
752 clocks = <&dss1_alwon_fck>;
753 clock-names = "fck";
754 };
755
756 dsi: encoder@4804fc00 {
757 compatible = "ti,omap3-dsi";
758 reg = <0x4804fc00 0x200>,
759 <0x4804fe00 0x40>,
760 <0x4804ff00 0x20>;
761 reg-names = "proto", "phy", "pll";
762 interrupts = <25>;
763 status = "disabled";
764 ti,hwmods = "dss_dsi1";
765 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
766 clock-names = "fck", "sys_clk";
767 };
768
769 rfbi: encoder@48050800 {
770 compatible = "ti,omap3-rfbi";
771 reg = <0x48050800 0x100>;
772 status = "disabled";
773 ti,hwmods = "dss_rfbi";
774 clocks = <&dss1_alwon_fck>, <&dss_ick>;
775 clock-names = "fck", "ick";
776 };
777
778 venc: encoder@48050c00 {
779 compatible = "ti,omap3-venc";
780 reg = <0x48050c00 0x100>;
781 status = "disabled";
782 ti,hwmods = "dss_venc";
783 clocks = <&dss_tv_fck>;
784 clock-names = "fck";
785 };
786 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]787
788 ssi: ssi-controller@48058000 {
789 compatible = "ti,omap3-ssi";
790 ti,hwmods = "ssi";
791
792 status = "disabled";
793
794 reg = <0x48058000 0x1000>,
795 <0x48059000 0x1000>;
796 reg-names = "sys",
797 "gdd";
798
799 interrupts = <71>;
800 interrupt-names = "gdd_mpu";
801
802 #address-cells = <1>;
803 #size-cells = <1>;
804 ranges;
805
806 ssi_port1: ssi-port@4805a000 {
807 compatible = "ti,omap3-ssi-port";
808
809 reg = <0x4805a000 0x800>,
810 <0x4805a800 0x800>;
811 reg-names = "tx",
812 "rx";
813
814 interrupt-parent = <&intc>;
815 interrupts = <67>,
816 <68>;
817 };
818
819 ssi_port2: ssi-port@4805b000 {
820 compatible = "ti,omap3-ssi-port";
821
822 reg = <0x4805b000 0x800>,
823 <0x4805b800 0x800>;
824 reg-names = "tx",
825 "rx";
826
827 interrupt-parent = <&intc>;
828 interrupts = <69>,
829 <70>;
830 };
831 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]832 };
833};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]834
835/include/ "omap3xxx-clocks.dtsi"