Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7794 SoC |
| 3 | * |
| 4 | * Copyright (C) 2014 Renesas Electronics Corporation |
| 5 | * Copyright (C) 2014 Ulrich Hecht |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <dt-bindings/clock/r8a7794-clock.h> |
| 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
| 16 | / { |
| 17 | compatible = "renesas,r8a7794"; |
| 18 | interrupt-parent = <&gic>; |
| 19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; |
| 21 | |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | |
| 26 | cpu0: cpu@0 { |
| 27 | device_type = "cpu"; |
| 28 | compatible = "arm,cortex-a7"; |
| 29 | reg = <0>; |
| 30 | clock-frequency = <1000000000>; |
| 31 | }; |
| 32 | |
| 33 | cpu1: cpu@1 { |
| 34 | device_type = "cpu"; |
| 35 | compatible = "arm,cortex-a7"; |
| 36 | reg = <1>; |
| 37 | clock-frequency = <1000000000>; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | gic: interrupt-controller@f1001000 { |
| 42 | compatible = "arm,cortex-a7-gic"; |
| 43 | #interrupt-cells = <3>; |
| 44 | #address-cells = <0>; |
| 45 | interrupt-controller; |
| 46 | reg = <0 0xf1001000 0 0x1000>, |
| 47 | <0 0xf1002000 0 0x1000>, |
| 48 | <0 0xf1004000 0 0x2000>, |
| 49 | <0 0xf1006000 0 0x2000>; |
Geert Uytterhoeven | 00add86 | 2014-11-27 11:57:17 +0100 | [diff] [blame] | 50 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | cmt0: timer@ffca0000 { |
| 54 | compatible = "renesas,cmt-48-gen2"; |
| 55 | reg = <0 0xffca0000 0 0x1004>; |
| 56 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | <0 143 IRQ_TYPE_LEVEL_HIGH>; |
| 58 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; |
| 59 | clock-names = "fck"; |
| 60 | |
| 61 | renesas,channels-mask = <0x60>; |
| 62 | |
| 63 | status = "disabled"; |
| 64 | }; |
| 65 | |
| 66 | cmt1: timer@e6130000 { |
| 67 | compatible = "renesas,cmt-48-gen2"; |
| 68 | reg = <0 0xe6130000 0 0x1004>; |
| 69 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <0 121 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <0 122 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <0 123 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <0 124 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <0 125 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <0 126 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <0 127 IRQ_TYPE_LEVEL_HIGH>; |
| 77 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; |
| 78 | clock-names = "fck"; |
| 79 | |
| 80 | renesas,channels-mask = <0xff>; |
| 81 | |
| 82 | status = "disabled"; |
| 83 | }; |
| 84 | |
Hisashi Nakamura | da33648 | 2014-09-12 10:52:06 +0200 | [diff] [blame] | 85 | timer { |
| 86 | compatible = "arm,armv7-timer"; |
Geert Uytterhoeven | 00add86 | 2014-11-27 11:57:17 +0100 | [diff] [blame] | 87 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 88 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 89 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 90 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Hisashi Nakamura | da33648 | 2014-09-12 10:52:06 +0200 | [diff] [blame] | 91 | }; |
| 92 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 93 | irqc0: interrupt-controller@e61c0000 { |
| 94 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; |
| 95 | #interrupt-cells = <2>; |
| 96 | interrupt-controller; |
| 97 | reg = <0 0xe61c0000 0 0x200>; |
| 98 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <0 12 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <0 14 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <0 15 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <0 16 IRQ_TYPE_LEVEL_HIGH>, |
| 107 | <0 17 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 1c5ca5d | 2015-03-18 19:56:01 +0100 | [diff] [blame] | 108 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 109 | }; |
| 110 | |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 111 | dmac0: dma-controller@e6700000 { |
| 112 | compatible = "renesas,rcar-dmac"; |
| 113 | reg = <0 0xe6700000 0 0x20000>; |
| 114 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH |
| 115 | 0 200 IRQ_TYPE_LEVEL_HIGH |
| 116 | 0 201 IRQ_TYPE_LEVEL_HIGH |
| 117 | 0 202 IRQ_TYPE_LEVEL_HIGH |
| 118 | 0 203 IRQ_TYPE_LEVEL_HIGH |
| 119 | 0 204 IRQ_TYPE_LEVEL_HIGH |
| 120 | 0 205 IRQ_TYPE_LEVEL_HIGH |
| 121 | 0 206 IRQ_TYPE_LEVEL_HIGH |
| 122 | 0 207 IRQ_TYPE_LEVEL_HIGH |
| 123 | 0 208 IRQ_TYPE_LEVEL_HIGH |
| 124 | 0 209 IRQ_TYPE_LEVEL_HIGH |
| 125 | 0 210 IRQ_TYPE_LEVEL_HIGH |
| 126 | 0 211 IRQ_TYPE_LEVEL_HIGH |
| 127 | 0 212 IRQ_TYPE_LEVEL_HIGH |
| 128 | 0 213 IRQ_TYPE_LEVEL_HIGH |
| 129 | 0 214 IRQ_TYPE_LEVEL_HIGH>; |
| 130 | interrupt-names = "error", |
| 131 | "ch0", "ch1", "ch2", "ch3", |
| 132 | "ch4", "ch5", "ch6", "ch7", |
| 133 | "ch8", "ch9", "ch10", "ch11", |
| 134 | "ch12", "ch13", "ch14"; |
| 135 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; |
| 136 | clock-names = "fck"; |
| 137 | #dma-cells = <1>; |
| 138 | dma-channels = <15>; |
| 139 | }; |
| 140 | |
| 141 | dmac1: dma-controller@e6720000 { |
| 142 | compatible = "renesas,rcar-dmac"; |
| 143 | reg = <0 0xe6720000 0 0x20000>; |
| 144 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH |
| 145 | 0 216 IRQ_TYPE_LEVEL_HIGH |
| 146 | 0 217 IRQ_TYPE_LEVEL_HIGH |
| 147 | 0 218 IRQ_TYPE_LEVEL_HIGH |
| 148 | 0 219 IRQ_TYPE_LEVEL_HIGH |
| 149 | 0 308 IRQ_TYPE_LEVEL_HIGH |
| 150 | 0 309 IRQ_TYPE_LEVEL_HIGH |
| 151 | 0 310 IRQ_TYPE_LEVEL_HIGH |
| 152 | 0 311 IRQ_TYPE_LEVEL_HIGH |
| 153 | 0 312 IRQ_TYPE_LEVEL_HIGH |
| 154 | 0 313 IRQ_TYPE_LEVEL_HIGH |
| 155 | 0 314 IRQ_TYPE_LEVEL_HIGH |
| 156 | 0 315 IRQ_TYPE_LEVEL_HIGH |
| 157 | 0 316 IRQ_TYPE_LEVEL_HIGH |
| 158 | 0 317 IRQ_TYPE_LEVEL_HIGH |
| 159 | 0 318 IRQ_TYPE_LEVEL_HIGH>; |
| 160 | interrupt-names = "error", |
| 161 | "ch0", "ch1", "ch2", "ch3", |
| 162 | "ch4", "ch5", "ch6", "ch7", |
| 163 | "ch8", "ch9", "ch10", "ch11", |
| 164 | "ch12", "ch13", "ch14"; |
| 165 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; |
| 166 | clock-names = "fck"; |
| 167 | #dma-cells = <1>; |
| 168 | dma-channels = <15>; |
| 169 | }; |
| 170 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 171 | scifa0: serial@e6c40000 { |
| 172 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 173 | reg = <0 0xe6c40000 0 64>; |
| 174 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 175 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; |
| 176 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 177 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
| 178 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 179 | status = "disabled"; |
| 180 | }; |
| 181 | |
| 182 | scifa1: serial@e6c50000 { |
| 183 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 184 | reg = <0 0xe6c50000 0 64>; |
| 185 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
| 186 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; |
| 187 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 188 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
| 189 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 190 | status = "disabled"; |
| 191 | }; |
| 192 | |
| 193 | scifa2: serial@e6c60000 { |
| 194 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 195 | reg = <0 0xe6c60000 0 64>; |
| 196 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
| 197 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; |
| 198 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 199 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
| 200 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 201 | status = "disabled"; |
| 202 | }; |
| 203 | |
| 204 | scifa3: serial@e6c70000 { |
| 205 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 206 | reg = <0 0xe6c70000 0 64>; |
| 207 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 208 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; |
| 209 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 210 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
| 211 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 212 | status = "disabled"; |
| 213 | }; |
| 214 | |
| 215 | scifa4: serial@e6c78000 { |
| 216 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 217 | reg = <0 0xe6c78000 0 64>; |
| 218 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 219 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; |
| 220 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 221 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
| 222 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 223 | status = "disabled"; |
| 224 | }; |
| 225 | |
| 226 | scifa5: serial@e6c80000 { |
| 227 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; |
| 228 | reg = <0 0xe6c80000 0 64>; |
| 229 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 230 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; |
| 231 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 232 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
| 233 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 234 | status = "disabled"; |
| 235 | }; |
| 236 | |
| 237 | scifb0: serial@e6c20000 { |
| 238 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; |
| 239 | reg = <0 0xe6c20000 0 64>; |
| 240 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
| 241 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; |
| 242 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 243 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
| 244 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
| 248 | scifb1: serial@e6c30000 { |
| 249 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; |
| 250 | reg = <0 0xe6c30000 0 64>; |
| 251 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; |
| 253 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 254 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
| 255 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 256 | status = "disabled"; |
| 257 | }; |
| 258 | |
| 259 | scifb2: serial@e6ce0000 { |
| 260 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; |
| 261 | reg = <0 0xe6ce0000 0 64>; |
| 262 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
| 263 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; |
| 264 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 265 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
| 266 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 267 | status = "disabled"; |
| 268 | }; |
| 269 | |
| 270 | scif0: serial@e6e60000 { |
| 271 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 272 | reg = <0 0xe6e60000 0 64>; |
| 273 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
| 274 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; |
| 275 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 276 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
| 277 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | scif1: serial@e6e68000 { |
| 282 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 283 | reg = <0 0xe6e68000 0 64>; |
| 284 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
| 285 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; |
| 286 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 287 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
| 288 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 289 | status = "disabled"; |
| 290 | }; |
| 291 | |
| 292 | scif2: serial@e6e58000 { |
| 293 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 294 | reg = <0 0xe6e58000 0 64>; |
| 295 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 296 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; |
| 297 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 298 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
| 299 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 300 | status = "disabled"; |
| 301 | }; |
| 302 | |
| 303 | scif3: serial@e6ea8000 { |
| 304 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 305 | reg = <0 0xe6ea8000 0 64>; |
| 306 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 307 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; |
| 308 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 309 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
| 310 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 311 | status = "disabled"; |
| 312 | }; |
| 313 | |
| 314 | scif4: serial@e6ee0000 { |
| 315 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 316 | reg = <0 0xe6ee0000 0 64>; |
| 317 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 318 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; |
| 319 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 320 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
| 321 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 322 | status = "disabled"; |
| 323 | }; |
| 324 | |
| 325 | scif5: serial@e6ee8000 { |
| 326 | compatible = "renesas,scif-r8a7794", "renesas,scif"; |
| 327 | reg = <0 0xe6ee8000 0 64>; |
| 328 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 329 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; |
| 330 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 331 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
| 332 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 333 | status = "disabled"; |
| 334 | }; |
| 335 | |
| 336 | hscif0: serial@e62c0000 { |
| 337 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; |
| 338 | reg = <0 0xe62c0000 0 96>; |
| 339 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; |
| 341 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 342 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
| 343 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 344 | status = "disabled"; |
| 345 | }; |
| 346 | |
| 347 | hscif1: serial@e62c8000 { |
| 348 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; |
| 349 | reg = <0 0xe62c8000 0 96>; |
| 350 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
| 351 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; |
| 352 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 353 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
| 354 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 355 | status = "disabled"; |
| 356 | }; |
| 357 | |
| 358 | hscif2: serial@e62d0000 { |
| 359 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; |
| 360 | reg = <0 0xe62d0000 0 96>; |
| 361 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
| 362 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; |
| 363 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 8233a0d | 2015-05-20 19:46:27 +0200 | [diff] [blame] | 364 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
| 365 | dma-names = "tx", "rx"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 366 | status = "disabled"; |
| 367 | }; |
| 368 | |
Laurent Pinchart | 82818d3 | 2015-01-27 10:45:55 +0200 | [diff] [blame] | 369 | ether: ethernet@ee700000 { |
| 370 | compatible = "renesas,ether-r8a7794"; |
| 371 | reg = <0 0xee700000 0 0x400>; |
| 372 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; |
| 373 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; |
| 374 | phy-mode = "rmii"; |
| 375 | #address-cells = <1>; |
| 376 | #size-cells = <0>; |
| 377 | status = "disabled"; |
| 378 | }; |
| 379 | |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 380 | sdhi0: sd@ee100000 { |
| 381 | compatible = "renesas,sdhi-r8a7794"; |
| 382 | reg = <0 0xee100000 0 0x200>; |
| 383 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 384 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; |
| 385 | status = "disabled"; |
| 386 | }; |
| 387 | |
| 388 | sdhi1: sd@ee140000 { |
| 389 | compatible = "renesas,sdhi-r8a7794"; |
| 390 | reg = <0 0xee140000 0 0x100>; |
| 391 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 392 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; |
| 393 | status = "disabled"; |
| 394 | }; |
| 395 | |
| 396 | sdhi2: sd@ee160000 { |
| 397 | compatible = "renesas,sdhi-r8a7794"; |
| 398 | reg = <0 0xee160000 0 0x100>; |
| 399 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 400 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; |
| 401 | status = "disabled"; |
| 402 | }; |
| 403 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 404 | clocks { |
| 405 | #address-cells = <2>; |
| 406 | #size-cells = <2>; |
| 407 | ranges; |
| 408 | |
| 409 | /* External root clock */ |
| 410 | extal_clk: extal_clk { |
| 411 | compatible = "fixed-clock"; |
| 412 | #clock-cells = <0>; |
| 413 | /* This value must be overriden by the board. */ |
| 414 | clock-frequency = <0>; |
| 415 | clock-output-names = "extal"; |
| 416 | }; |
| 417 | |
| 418 | /* Special CPG clocks */ |
| 419 | cpg_clocks: cpg_clocks@e6150000 { |
| 420 | compatible = "renesas,r8a7794-cpg-clocks", |
| 421 | "renesas,rcar-gen2-cpg-clocks"; |
| 422 | reg = <0 0xe6150000 0 0x1000>; |
| 423 | clocks = <&extal_clk>; |
| 424 | #clock-cells = <1>; |
| 425 | clock-output-names = "main", "pll0", "pll1", "pll3", |
| 426 | "lb", "qspi", "sdh", "sd0", "z"; |
| 427 | }; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 428 | /* Variable factor clocks */ |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 429 | sd2_clk: sd2_clk@e6150078 { |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 430 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
| 431 | reg = <0 0xe6150078 0 4>; |
| 432 | clocks = <&pll1_div2_clk>; |
| 433 | #clock-cells = <0>; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 434 | clock-output-names = "sd2"; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 435 | }; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 436 | sd3_clk: sd3_clk@e615026c { |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 437 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 438 | reg = <0 0xe615026c 0 4>; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 439 | clocks = <&pll1_div2_clk>; |
| 440 | #clock-cells = <0>; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 441 | clock-output-names = "sd3"; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 442 | }; |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 443 | mmc0_clk: mmc0_clk@e6150240 { |
| 444 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
| 445 | reg = <0 0xe6150240 0 4>; |
| 446 | clocks = <&pll1_div2_clk>; |
| 447 | #clock-cells = <0>; |
| 448 | clock-output-names = "mmc0"; |
| 449 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 450 | |
| 451 | /* Fixed factor clocks */ |
| 452 | pll1_div2_clk: pll1_div2_clk { |
| 453 | compatible = "fixed-factor-clock"; |
| 454 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 455 | #clock-cells = <0>; |
| 456 | clock-div = <2>; |
| 457 | clock-mult = <1>; |
| 458 | clock-output-names = "pll1_div2"; |
| 459 | }; |
| 460 | zg_clk: zg_clk { |
| 461 | compatible = "fixed-factor-clock"; |
| 462 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 463 | #clock-cells = <0>; |
| 464 | clock-div = <6>; |
| 465 | clock-mult = <1>; |
| 466 | clock-output-names = "zg"; |
| 467 | }; |
| 468 | zx_clk: zx_clk { |
| 469 | compatible = "fixed-factor-clock"; |
| 470 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 471 | #clock-cells = <0>; |
| 472 | clock-div = <3>; |
| 473 | clock-mult = <1>; |
| 474 | clock-output-names = "zx"; |
| 475 | }; |
| 476 | zs_clk: zs_clk { |
| 477 | compatible = "fixed-factor-clock"; |
| 478 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 479 | #clock-cells = <0>; |
| 480 | clock-div = <6>; |
| 481 | clock-mult = <1>; |
| 482 | clock-output-names = "zs"; |
| 483 | }; |
| 484 | hp_clk: hp_clk { |
| 485 | compatible = "fixed-factor-clock"; |
| 486 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 487 | #clock-cells = <0>; |
| 488 | clock-div = <12>; |
| 489 | clock-mult = <1>; |
| 490 | clock-output-names = "hp"; |
| 491 | }; |
| 492 | i_clk: i_clk { |
| 493 | compatible = "fixed-factor-clock"; |
| 494 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 495 | #clock-cells = <0>; |
| 496 | clock-div = <2>; |
| 497 | clock-mult = <1>; |
| 498 | clock-output-names = "i"; |
| 499 | }; |
| 500 | b_clk: b_clk { |
| 501 | compatible = "fixed-factor-clock"; |
| 502 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 503 | #clock-cells = <0>; |
| 504 | clock-div = <12>; |
| 505 | clock-mult = <1>; |
| 506 | clock-output-names = "b"; |
| 507 | }; |
| 508 | p_clk: p_clk { |
| 509 | compatible = "fixed-factor-clock"; |
| 510 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 511 | #clock-cells = <0>; |
| 512 | clock-div = <24>; |
| 513 | clock-mult = <1>; |
| 514 | clock-output-names = "p"; |
| 515 | }; |
| 516 | cl_clk: cl_clk { |
| 517 | compatible = "fixed-factor-clock"; |
| 518 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 519 | #clock-cells = <0>; |
| 520 | clock-div = <48>; |
| 521 | clock-mult = <1>; |
| 522 | clock-output-names = "cl"; |
| 523 | }; |
| 524 | m2_clk: m2_clk { |
| 525 | compatible = "fixed-factor-clock"; |
| 526 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 527 | #clock-cells = <0>; |
| 528 | clock-div = <8>; |
| 529 | clock-mult = <1>; |
| 530 | clock-output-names = "m2"; |
| 531 | }; |
| 532 | imp_clk: imp_clk { |
| 533 | compatible = "fixed-factor-clock"; |
| 534 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 535 | #clock-cells = <0>; |
| 536 | clock-div = <4>; |
| 537 | clock-mult = <1>; |
| 538 | clock-output-names = "imp"; |
| 539 | }; |
| 540 | rclk_clk: rclk_clk { |
| 541 | compatible = "fixed-factor-clock"; |
| 542 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 543 | #clock-cells = <0>; |
| 544 | clock-div = <(48 * 1024)>; |
| 545 | clock-mult = <1>; |
| 546 | clock-output-names = "rclk"; |
| 547 | }; |
| 548 | oscclk_clk: oscclk_clk { |
| 549 | compatible = "fixed-factor-clock"; |
| 550 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 551 | #clock-cells = <0>; |
| 552 | clock-div = <(12 * 1024)>; |
| 553 | clock-mult = <1>; |
| 554 | clock-output-names = "oscclk"; |
| 555 | }; |
| 556 | zb3_clk: zb3_clk { |
| 557 | compatible = "fixed-factor-clock"; |
| 558 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 559 | #clock-cells = <0>; |
| 560 | clock-div = <4>; |
| 561 | clock-mult = <1>; |
| 562 | clock-output-names = "zb3"; |
| 563 | }; |
| 564 | zb3d2_clk: zb3d2_clk { |
| 565 | compatible = "fixed-factor-clock"; |
| 566 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 567 | #clock-cells = <0>; |
| 568 | clock-div = <8>; |
| 569 | clock-mult = <1>; |
| 570 | clock-output-names = "zb3d2"; |
| 571 | }; |
| 572 | ddr_clk: ddr_clk { |
| 573 | compatible = "fixed-factor-clock"; |
| 574 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 575 | #clock-cells = <0>; |
| 576 | clock-div = <8>; |
| 577 | clock-mult = <1>; |
| 578 | clock-output-names = "ddr"; |
| 579 | }; |
| 580 | mp_clk: mp_clk { |
| 581 | compatible = "fixed-factor-clock"; |
| 582 | clocks = <&pll1_div2_clk>; |
| 583 | #clock-cells = <0>; |
| 584 | clock-div = <15>; |
| 585 | clock-mult = <1>; |
| 586 | clock-output-names = "mp"; |
| 587 | }; |
| 588 | cp_clk: cp_clk { |
| 589 | compatible = "fixed-factor-clock"; |
| 590 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 591 | #clock-cells = <0>; |
| 592 | clock-div = <48>; |
| 593 | clock-mult = <1>; |
| 594 | clock-output-names = "cp"; |
| 595 | }; |
| 596 | |
| 597 | acp_clk: acp_clk { |
| 598 | compatible = "fixed-factor-clock"; |
| 599 | clocks = <&extal_clk>; |
| 600 | #clock-cells = <0>; |
| 601 | clock-div = <2>; |
| 602 | clock-mult = <1>; |
| 603 | clock-output-names = "acp"; |
| 604 | }; |
| 605 | |
| 606 | /* Gate clocks */ |
| 607 | mstp0_clks: mstp0_clks@e6150130 { |
| 608 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 609 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 610 | clocks = <&mp_clk>; |
| 611 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 612 | clock-indices = <R8A7794_CLK_MSIOF0>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 613 | clock-output-names = "msiof0"; |
| 614 | }; |
| 615 | mstp1_clks: mstp1_clks@e6150134 { |
| 616 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 617 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 618 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
| 619 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, |
| 620 | <&zs_clk>, <&zs_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 621 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 622 | clock-indices = < |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 623 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
| 624 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 |
| 625 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 |
| 626 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 627 | >; |
| 628 | clock-output-names = |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 629 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
| 630 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 631 | }; |
| 632 | mstp2_clks: mstp2_clks@e6150138 { |
| 633 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 634 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 635 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 636 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 637 | <&zs_clk>, <&zs_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 638 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 639 | clock-indices = < |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 640 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
| 641 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 |
| 642 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 643 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 644 | >; |
| 645 | clock-output-names = |
| 646 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 647 | "scifb1", "msiof1", "scifb2", |
| 648 | "sys-dmac1", "sys-dmac0"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 649 | }; |
| 650 | mstp3_clks: mstp3_clks@e615013c { |
| 651 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 652 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 653 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 654 | <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 655 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 656 | clock-indices = < |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 657 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 658 | R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 |
| 659 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 660 | >; |
| 661 | clock-output-names = |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 662 | "sdhi2", "sdhi1", "sdhi0", |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 663 | "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 664 | }; |
Geert Uytterhoeven | 1c5ca5d | 2015-03-18 19:56:01 +0100 | [diff] [blame] | 665 | mstp4_clks: mstp4_clks@e6150140 { |
| 666 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 667 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 668 | clocks = <&cp_clk>; |
| 669 | #clock-cells = <1>; |
| 670 | clock-indices = <R8A7794_CLK_IRQC>; |
| 671 | clock-output-names = "irqc"; |
| 672 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 673 | mstp7_clks: mstp7_clks@e615014c { |
| 674 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 675 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 676 | clocks = <&mp_clk>, <&mp_clk>, |
| 677 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 678 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; |
| 679 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 680 | clock-indices = < |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 681 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 682 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
| 683 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 |
| 684 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 |
| 685 | R8A7794_CLK_SCIF0 |
| 686 | >; |
| 687 | clock-output-names = |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 688 | "ehci", "hsusb", |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 689 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
| 690 | "scif3", "scif2", "scif1", "scif0"; |
| 691 | }; |
| 692 | mstp8_clks: mstp8_clks@e6150990 { |
| 693 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 694 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Koji Matsuoka | 148ebf4 | 2014-10-30 14:58:55 +0900 | [diff] [blame] | 695 | clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 696 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 697 | clock-indices = < |
Koji Matsuoka | 148ebf4 | 2014-10-30 14:58:55 +0900 | [diff] [blame] | 698 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 699 | >; |
| 700 | clock-output-names = |
Koji Matsuoka | 148ebf4 | 2014-10-30 14:58:55 +0900 | [diff] [blame] | 701 | "vin1", "vin0", "ether"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 702 | }; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 703 | mstp9_clks: mstp9_clks@e6150994 { |
| 704 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 705 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Koji Matsuoka | c5d82c9 | 2014-05-23 18:37:04 +0900 | [diff] [blame] | 706 | clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, |
| 707 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 708 | #clock-cells = <1>; |
Koji Matsuoka | c5d82c9 | 2014-05-23 18:37:04 +0900 | [diff] [blame] | 709 | clock-indices = < |
| 710 | R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 |
| 711 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1 |
| 712 | R8A7794_CLK_I2C0 |
| 713 | >; |
| 714 | clock-output-names = |
| 715 | "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 716 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 717 | mstp11_clks: mstp11_clks@e615099c { |
| 718 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 719 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; |
| 720 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; |
| 721 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 722 | clock-indices = < |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 723 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
| 724 | >; |
| 725 | clock-output-names = "scifa3", "scifa4", "scifa5"; |
| 726 | }; |
| 727 | }; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 728 | |
| 729 | ipmmu_sy0: mmu@e6280000 { |
| 730 | compatible = "renesas,ipmmu-vmsa"; |
| 731 | reg = <0 0xe6280000 0 0x1000>; |
| 732 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, |
| 733 | <0 224 IRQ_TYPE_LEVEL_HIGH>; |
| 734 | #iommu-cells = <1>; |
| 735 | status = "disabled"; |
| 736 | }; |
| 737 | |
| 738 | ipmmu_sy1: mmu@e6290000 { |
| 739 | compatible = "renesas,ipmmu-vmsa"; |
| 740 | reg = <0 0xe6290000 0 0x1000>; |
| 741 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; |
| 742 | #iommu-cells = <1>; |
| 743 | status = "disabled"; |
| 744 | }; |
| 745 | |
| 746 | ipmmu_ds: mmu@e6740000 { |
| 747 | compatible = "renesas,ipmmu-vmsa"; |
| 748 | reg = <0 0xe6740000 0 0x1000>; |
| 749 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, |
| 750 | <0 199 IRQ_TYPE_LEVEL_HIGH>; |
| 751 | #iommu-cells = <1>; |
| 752 | }; |
| 753 | |
| 754 | ipmmu_mp: mmu@ec680000 { |
| 755 | compatible = "renesas,ipmmu-vmsa"; |
| 756 | reg = <0 0xec680000 0 0x1000>; |
| 757 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; |
| 758 | #iommu-cells = <1>; |
| 759 | status = "disabled"; |
| 760 | }; |
| 761 | |
| 762 | ipmmu_mx: mmu@fe951000 { |
| 763 | compatible = "renesas,ipmmu-vmsa"; |
| 764 | reg = <0 0xfe951000 0 0x1000>; |
| 765 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, |
| 766 | <0 221 IRQ_TYPE_LEVEL_HIGH>; |
| 767 | #iommu-cells = <1>; |
| 768 | }; |
| 769 | |
| 770 | ipmmu_gp: mmu@e62a0000 { |
| 771 | compatible = "renesas,ipmmu-vmsa"; |
| 772 | reg = <0 0xe62a0000 0 0x1000>; |
| 773 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, |
| 774 | <0 261 IRQ_TYPE_LEVEL_HIGH>; |
| 775 | #iommu-cells = <1>; |
| 776 | status = "disabled"; |
| 777 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 778 | }; |