David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <linux/module.h> |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 22 | #include <linux/notifier.h> |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 23 | #include <linux/of.h> |
| 24 | #include <linux/of_device.h> |
| 25 | #include <linux/of_irq.h> |
| 26 | #include <linux/spmi.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/string.h> |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 29 | #include <linux/workqueue.h> |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 30 | #include <linux/regulator/driver.h> |
| 31 | #include <linux/regulator/machine.h> |
| 32 | #include <linux/regulator/of_regulator.h> |
| 33 | #include <linux/qpnp/qpnp-revid.h> |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 34 | #include <linux/regulator/qpnp-labibb-regulator.h> |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 35 | |
| 36 | #define QPNP_LABIBB_REGULATOR_DRIVER_NAME "qcom,qpnp-labibb-regulator" |
| 37 | |
| 38 | #define REG_REVISION_2 0x01 |
| 39 | #define REG_PERPH_TYPE 0x04 |
| 40 | |
| 41 | #define QPNP_LAB_TYPE 0x24 |
| 42 | #define QPNP_IBB_TYPE 0x20 |
| 43 | |
| 44 | /* Common register value for LAB/IBB */ |
| 45 | #define REG_LAB_IBB_LCD_MODE 0x0 |
| 46 | #define REG_LAB_IBB_AMOLED_MODE BIT(7) |
| 47 | #define REG_LAB_IBB_SEC_ACCESS 0xD0 |
| 48 | #define REG_LAB_IBB_SEC_UNLOCK_CODE 0xA5 |
| 49 | |
| 50 | /* LAB register offset definitions */ |
| 51 | #define REG_LAB_STATUS1 0x08 |
| 52 | #define REG_LAB_SWIRE_PGM_CTL 0x40 |
| 53 | #define REG_LAB_VOLTAGE 0x41 |
| 54 | #define REG_LAB_RING_SUPPRESSION_CTL 0x42 |
| 55 | #define REG_LAB_LCD_AMOLED_SEL 0x44 |
| 56 | #define REG_LAB_MODULE_RDY 0x45 |
| 57 | #define REG_LAB_ENABLE_CTL 0x46 |
| 58 | #define REG_LAB_PD_CTL 0x47 |
| 59 | #define REG_LAB_CLK_DIV 0x48 |
| 60 | #define REG_LAB_IBB_EN_RDY 0x49 |
| 61 | #define REG_LAB_CURRENT_LIMIT 0x4B |
| 62 | #define REG_LAB_CURRENT_SENSE 0x4C |
| 63 | #define REG_LAB_PS_CTL 0x50 |
| 64 | #define REG_LAB_RDSON_MNGMNT 0x53 |
| 65 | #define REG_LAB_PRECHARGE_CTL 0x5E |
| 66 | #define REG_LAB_SOFT_START_CTL 0x5F |
| 67 | #define REG_LAB_SPARE_CTL 0x60 |
| 68 | #define REG_LAB_PFM_CTL 0x62 |
| 69 | |
| 70 | /* LAB registers for PM660A */ |
| 71 | #define REG_LAB_VOUT_DEFAULT 0x44 |
| 72 | #define REG_LAB_SW_HIGH_PSRR_CTL 0x70 |
| 73 | #define REG_LAB_LDO_PD_CTL 0x78 |
| 74 | #define REG_LAB_VPH_ENVELOP_CTL 0x7E |
| 75 | |
| 76 | /* LAB register bits definitions */ |
| 77 | |
| 78 | /* REG_LAB_STATUS1 */ |
| 79 | #define LAB_STATUS1_VREG_OK_MASK BIT(7) |
| 80 | #define LAB_STATUS1_VREG_OK BIT(7) |
| 81 | |
| 82 | /* REG_LAB_SWIRE_PGM_CTL */ |
| 83 | #define LAB_EN_SWIRE_PGM_VOUT BIT(7) |
| 84 | #define LAB_EN_SWIRE_PGM_PD BIT(6) |
| 85 | |
| 86 | /* REG_LAB_VOLTAGE */ |
| 87 | #define LAB_VOLTAGE_OVERRIDE_EN BIT(7) |
| 88 | #define LAB_VOLTAGE_SET_MASK GENMASK(3, 0) |
| 89 | |
| 90 | /* REG_LAB_RING_SUPPRESSION_CTL */ |
| 91 | #define LAB_RING_SUPPRESSION_CTL_EN BIT(7) |
| 92 | |
| 93 | /* REG_LAB_MODULE_RDY */ |
| 94 | #define LAB_MODULE_RDY_EN BIT(7) |
| 95 | |
| 96 | /* REG_LAB_ENABLE_CTL */ |
| 97 | #define LAB_ENABLE_CTL_EN BIT(7) |
| 98 | |
| 99 | /* REG_LAB_PD_CTL */ |
| 100 | #define LAB_PD_CTL_STRONG_PULL BIT(0) |
| 101 | #define LAB_PD_CTL_STRENGTH_MASK BIT(0) |
| 102 | #define LAB_PD_CTL_DISABLE_PD BIT(1) |
| 103 | #define LAB_PD_CTL_EN_MASK BIT(1) |
| 104 | |
| 105 | /* REG_LAB_IBB_EN_RDY */ |
| 106 | #define LAB_IBB_EN_RDY_EN BIT(7) |
| 107 | |
| 108 | /* REG_LAB_CURRENT_LIMIT */ |
| 109 | #define LAB_CURRENT_LIMIT_MASK GENMASK(2, 0) |
| 110 | #define LAB_CURRENT_LIMIT_EN_BIT BIT(7) |
| 111 | #define LAB_OVERRIDE_CURRENT_MAX_BIT BIT(3) |
| 112 | |
| 113 | /* REG_LAB_CURRENT_SENSE */ |
| 114 | #define LAB_CURRENT_SENSE_GAIN_MASK GENMASK(1, 0) |
| 115 | |
| 116 | /* REG_LAB_PS_CTL */ |
| 117 | #define LAB_PS_THRESH_MASK GENMASK(1, 0) |
| 118 | #define LAB_PS_CTL_EN BIT(7) |
| 119 | |
| 120 | /* REG_LAB_RDSON_MNGMNT */ |
| 121 | #define LAB_RDSON_MNGMNT_NFET_SLEW_EN BIT(5) |
| 122 | #define LAB_RDSON_MNGMNT_PFET_SLEW_EN BIT(4) |
| 123 | #define LAB_RDSON_MNGMNT_NFET_MASK GENMASK(3, 2) |
| 124 | #define LAB_RDSON_MNGMNT_NFET_SHIFT 2 |
| 125 | #define LAB_RDSON_MNGMNT_PFET_MASK GENMASK(1, 0) |
| 126 | #define LAB_RDSON_NFET_SW_SIZE_QUARTER 0x0 |
| 127 | #define LAB_RDSON_PFET_SW_SIZE_QUARTER 0x0 |
| 128 | |
| 129 | /* REG_LAB_PRECHARGE_CTL */ |
| 130 | #define LAB_FAST_PRECHARGE_CTL_EN BIT(2) |
| 131 | #define LAB_MAX_PRECHARGE_TIME_MASK GENMASK(1, 0) |
| 132 | |
| 133 | /* REG_LAB_SOFT_START_CTL */ |
| 134 | #define LAB_SOFT_START_CTL_MASK GENMASK(1, 0) |
| 135 | |
| 136 | /* REG_LAB_SPARE_CTL */ |
| 137 | #define LAB_SPARE_TOUCH_WAKE_BIT BIT(3) |
| 138 | #define LAB_SPARE_DISABLE_SCP_BIT BIT(0) |
| 139 | |
| 140 | /* REG_LAB_PFM_CTL */ |
| 141 | #define LAB_PFM_EN_BIT BIT(7) |
| 142 | |
| 143 | /* REG_LAB_SW_HIGH_PSRR_CTL */ |
| 144 | #define LAB_EN_SW_HIGH_PSRR_MODE BIT(7) |
| 145 | #define LAB_SW_HIGH_PSRR_REQ BIT(0) |
| 146 | |
| 147 | /* REG_LAB_VPH_ENVELOP_CTL */ |
| 148 | #define LAB_VREF_HIGH_PSRR_SEL_MASK GENMASK(7, 6) |
| 149 | #define LAB_SEL_HW_HIGH_PSRR_SRC_MASK GENMASK(1, 0) |
| 150 | #define LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT 6 |
| 151 | |
| 152 | /* IBB register offset definitions */ |
| 153 | #define REG_IBB_REVISION4 0x03 |
| 154 | #define REG_IBB_STATUS1 0x08 |
| 155 | #define REG_IBB_VOLTAGE 0x41 |
| 156 | #define REG_IBB_RING_SUPPRESSION_CTL 0x42 |
| 157 | #define REG_IBB_LCD_AMOLED_SEL 0x44 |
| 158 | #define REG_IBB_MODULE_RDY 0x45 |
| 159 | #define REG_IBB_ENABLE_CTL 0x46 |
| 160 | #define REG_IBB_PD_CTL 0x47 |
| 161 | #define REG_IBB_CLK_DIV 0x48 |
| 162 | #define REG_IBB_CURRENT_LIMIT 0x4B |
| 163 | #define REG_IBB_PS_CTL 0x50 |
| 164 | #define REG_IBB_RDSON_MNGMNT 0x53 |
| 165 | #define REG_IBB_NONOVERLAP_TIME_1 0x56 |
| 166 | #define REG_IBB_NONOVERLAP_TIME_2 0x57 |
| 167 | #define REG_IBB_PWRUP_PWRDN_CTL_1 0x58 |
| 168 | #define REG_IBB_PWRUP_PWRDN_CTL_2 0x59 |
| 169 | #define REG_IBB_SOFT_START_CTL 0x5F |
| 170 | #define REG_IBB_SWIRE_CTL 0x5A |
| 171 | #define REG_IBB_OUTPUT_SLEW_CTL 0x5D |
| 172 | #define REG_IBB_SPARE_CTL 0x60 |
| 173 | #define REG_IBB_NLIMIT_DAC 0x61 |
| 174 | |
| 175 | /* IBB registers for PM660A */ |
| 176 | #define REG_IBB_DEFAULT_VOLTAGE 0x40 |
| 177 | #define REG_IBB_FLOAT_CTL 0x43 |
| 178 | #define REG_IBB_VREG_OK_CTL 0x55 |
| 179 | #define REG_IBB_VOUT_MIN_MAGNITUDE 0x5C |
| 180 | #define REG_IBB_PFM_CTL 0x62 |
| 181 | #define REG_IBB_SMART_PS_CTL 0x65 |
| 182 | #define REG_IBB_ADAPT_DEAD_TIME 0x67 |
| 183 | |
| 184 | /* IBB register bits definition */ |
| 185 | |
| 186 | /* REG_IBB_STATUS1 */ |
| 187 | #define IBB_STATUS1_VREG_OK_MASK BIT(7) |
| 188 | #define IBB_STATUS1_VREG_OK BIT(7) |
| 189 | |
| 190 | /* REG_IBB_VOLTAGE */ |
| 191 | #define IBB_VOLTAGE_OVERRIDE_EN BIT(7) |
| 192 | #define IBB_VOLTAGE_SET_MASK GENMASK(5, 0) |
| 193 | |
| 194 | /* REG_IBB_CLK_DIV */ |
| 195 | #define IBB_CLK_DIV_OVERRIDE_EN BIT(7) |
| 196 | #define IBB_CLK_DIV_MASK GENMASK(3, 0) |
| 197 | |
| 198 | /* REG_IBB_RING_SUPPRESSION_CTL */ |
| 199 | #define IBB_RING_SUPPRESSION_CTL_EN BIT(7) |
| 200 | |
| 201 | /* REG_IBB_FLOAT_CTL */ |
| 202 | #define IBB_FLOAT_EN BIT(0) |
| 203 | #define IBB_SMART_FLOAT_EN BIT(7) |
| 204 | |
| 205 | /* REG_IBB_MIN_MAGNITUDE */ |
| 206 | #define IBB_MIN_VOLTAGE_0P8_V BIT(3) |
| 207 | |
| 208 | /* REG_IBB_MODULE_RDY */ |
| 209 | #define IBB_MODULE_RDY_EN BIT(7) |
| 210 | |
| 211 | /* REG_IBB_ENABLE_CTL */ |
| 212 | #define IBB_ENABLE_CTL_MASK (BIT(7) | BIT(6)) |
| 213 | #define IBB_ENABLE_CTL_SWIRE_RDY BIT(6) |
| 214 | #define IBB_ENABLE_CTL_MODULE_EN BIT(7) |
| 215 | |
| 216 | /* REG_IBB_PD_CTL */ |
| 217 | #define IBB_PD_CTL_HALF_STRENGTH BIT(0) |
| 218 | #define IBB_PD_CTL_STRENGTH_MASK BIT(0) |
| 219 | #define IBB_PD_CTL_EN BIT(7) |
| 220 | #define IBB_SWIRE_PD_UPD BIT(1) |
| 221 | #define IBB_PD_CTL_EN_MASK BIT(7) |
| 222 | |
| 223 | /* REG_IBB_CURRENT_LIMIT */ |
| 224 | #define IBB_CURRENT_LIMIT_MASK GENMASK(4, 0) |
| 225 | #define IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT 5 |
| 226 | #define IBB_CURRENT_LIMIT_DEBOUNCE_MASK GENMASK(6, 5) |
| 227 | #define IBB_CURRENT_LIMIT_EN BIT(7) |
| 228 | #define IBB_ILIMIT_COUNT_CYC8 0 |
| 229 | #define IBB_CURRENT_MAX_500MA 0xA |
| 230 | |
| 231 | /* REG_IBB_PS_CTL */ |
| 232 | #define IBB_PS_CTL_EN 0x85 |
| 233 | |
| 234 | /* REG_IBB_SMART_PS_CTL */ |
| 235 | #define IBB_SMART_PS_CTL_EN BIT(7) |
| 236 | #define IBB_NUM_SWIRE_PULSE_WAIT 0x5 |
| 237 | |
| 238 | /* REG_IBB_OUTPUT_SLEW_CTL */ |
| 239 | #define IBB_SLEW_CTL_EN BIT(7) |
| 240 | #define IBB_SLEW_RATE_SPEED_FAST_EN BIT(6) |
| 241 | #define IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT 3 |
| 242 | #define IBB_SLEW_RATE_TRANS_TIME_FAST_MASK GENMASK(5, 3) |
| 243 | #define IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK GENMASK(2, 0) |
| 244 | |
| 245 | /* REG_IBB_VREG_OK_CTL */ |
| 246 | #define IBB_VREG_OK_EN_OVERLOAD_BLANK BIT(7) |
| 247 | #define IBB_VREG_OK_OVERLOAD_DEB_SHIFT 5 |
| 248 | #define IBB_VREG_OK_OVERLOAD_DEB_MASK GENMASK(6, 5) |
| 249 | |
| 250 | /* REG_IBB_RDSON_MNGMNT */ |
| 251 | #define IBB_NFET_SLEW_EN BIT(7) |
| 252 | #define IBB_PFET_SLEW_EN BIT(6) |
| 253 | #define IBB_OVERRIDE_NFET_SW_SIZE BIT(5) |
| 254 | #define IBB_OVERRIDE_PFET_SW_SIZE BIT(2) |
| 255 | #define IBB_NFET_SW_SIZE_MASK GENMASK(3, 2) |
| 256 | #define IBB_PFET_SW_SIZE_MASK GENMASK(1, 0) |
| 257 | |
| 258 | /* REG_IBB_NONOVERLAP_TIME_1 */ |
| 259 | #define IBB_OVERRIDE_NONOVERLAP BIT(6) |
| 260 | #define IBB_NONOVERLAP_NFET_MASK GENMASK(2, 0) |
| 261 | #define IBB_NFET_GATE_DELAY_2 0x3 |
| 262 | |
| 263 | /* REG_IBB_NONOVERLAP_TIME_2 */ |
| 264 | #define IBB_N2P_MUX_SEL BIT(0) |
| 265 | |
| 266 | /* REG_IBB_SOFT_START_CTL */ |
| 267 | #define IBB_SOFT_START_CHARGING_RESISTOR_16K 0x3 |
| 268 | |
| 269 | /* REG_IBB_SPARE_CTL */ |
| 270 | #define IBB_BYPASS_PWRDN_DLY2_BIT BIT(5) |
| 271 | #define IBB_POFF_CTL_MASK BIT(4) |
| 272 | #define IBB_FASTER_PFET_OFF BIT(4) |
| 273 | #define IBB_FAST_STARTUP BIT(3) |
| 274 | |
| 275 | /* REG_IBB_SWIRE_CTL */ |
| 276 | #define IBB_SWIRE_VOUT_UPD_EN BIT(6) |
| 277 | #define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK GENMASK(5, 0) |
| 278 | #define MAX_OUTPUT_EDGE_VOLTAGE_MV 6300 |
| 279 | #define MAX_OUTPUT_PULSE_VOLTAGE_MV 7700 |
| 280 | #define MIN_OUTPUT_PULSE_VOLTAGE_MV 1400 |
| 281 | #define OUTPUT_VOLTAGE_STEP_MV 100 |
| 282 | |
| 283 | /* REG_IBB_NLIMIT_DAC */ |
| 284 | #define IBB_DEFAULT_NLIMIT_DAC 0x5 |
| 285 | |
| 286 | /* REG_IBB_PFM_CTL */ |
| 287 | #define IBB_PFM_ENABLE BIT(7) |
| 288 | #define IBB_PFM_PEAK_CURRENT_BIT_SHIFT 1 |
| 289 | #define IBB_PFM_PEAK_CURRENT_MASK GENMASK(3, 1) |
| 290 | #define IBB_PFM_HYSTERESIS_BIT_SHIFT 4 |
| 291 | #define IBB_PFM_HYSTERESIS_MASK GENMASK(5, 4) |
| 292 | |
| 293 | /* REG_IBB_PWRUP_PWRDN_CTL_1 */ |
| 294 | #define IBB_PWRUP_PWRDN_CTL_1_DLY1_BITS 2 |
| 295 | #define IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK GENMASK(5, 4) |
| 296 | #define IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT 4 |
| 297 | #define IBB_PWRUP_PWRDN_CTL_1_EN_DLY2 BIT(3) |
| 298 | #define IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK GENMASK(1, 0) |
| 299 | #define IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK BIT(7) |
| 300 | #define IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 BIT(6) |
| 301 | #define PWRUP_PWRDN_CTL_1_DISCHARGE_EN BIT(2) |
| 302 | |
| 303 | /* REG_IBB_PWRUP_PWRDN_CTL_2 */ |
| 304 | #define IBB_DIS_DLY_MASK GENMASK(1, 0) |
| 305 | #define IBB_WAIT_MBG_OK BIT(2) |
| 306 | |
| 307 | /* Constants */ |
| 308 | #define SWIRE_DEFAULT_2ND_CMD_DLY_MS 20 |
| 309 | #define SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS 200 |
| 310 | #define IBB_HW_DEFAULT_SLEW_RATE 12000 |
| 311 | |
| 312 | /** |
| 313 | * enum qpnp_labibb_mode - working mode of LAB/IBB regulators |
| 314 | * %QPNP_LABIBB_LCD_MODE: configure LAB and IBB regulators |
| 315 | * together to provide power supply for LCD |
| 316 | * %QPNP_LABIBB_AMOLED_MODE: configure LAB and IBB regulators |
| 317 | * together to provide power supply for AMOLED |
| 318 | * %QPNP_LABIBB_MAX_MODE max number of configureable modes |
| 319 | * supported by qpnp_labibb_regulator |
| 320 | */ |
| 321 | enum qpnp_labibb_mode { |
| 322 | QPNP_LABIBB_LCD_MODE, |
| 323 | QPNP_LABIBB_AMOLED_MODE, |
| 324 | QPNP_LABIBB_MAX_MODE, |
| 325 | }; |
| 326 | |
| 327 | /** |
| 328 | * IBB_SW_CONTROL_EN: Specifies IBB is enabled through software. |
| 329 | * IBB_SW_CONTROL_DIS: Specifies IBB is disabled through software. |
| 330 | * IBB_HW_CONTROL: Specifies IBB is controlled through SWIRE (hardware). |
| 331 | */ |
| 332 | enum ibb_mode { |
| 333 | IBB_SW_CONTROL_EN, |
| 334 | IBB_SW_CONTROL_DIS, |
| 335 | IBB_HW_CONTROL, |
| 336 | IBB_HW_SW_CONTROL, |
| 337 | }; |
| 338 | |
| 339 | static const int ibb_dischg_res_table[] = { |
| 340 | 300, |
| 341 | 64, |
| 342 | 32, |
| 343 | 16, |
| 344 | }; |
| 345 | |
| 346 | static const int ibb_pwrup_dly_table[] = { |
| 347 | 1000, |
| 348 | 2000, |
| 349 | 4000, |
| 350 | 8000, |
| 351 | }; |
| 352 | |
| 353 | static const int ibb_pwrdn_dly_table[] = { |
| 354 | 1000, |
| 355 | 2000, |
| 356 | 4000, |
| 357 | 8000, |
| 358 | }; |
| 359 | |
| 360 | static const int lab_clk_div_table[] = { |
| 361 | 3200, |
| 362 | 2740, |
| 363 | 2400, |
| 364 | 2130, |
| 365 | 1920, |
| 366 | 1750, |
| 367 | 1600, |
| 368 | 1480, |
| 369 | 1370, |
| 370 | 1280, |
| 371 | 1200, |
| 372 | 1130, |
| 373 | 1070, |
| 374 | 1010, |
| 375 | 960, |
| 376 | 910, |
| 377 | }; |
| 378 | |
| 379 | static const int ibb_clk_div_table[] = { |
| 380 | 3200, |
| 381 | 2740, |
| 382 | 2400, |
| 383 | 2130, |
| 384 | 1920, |
| 385 | 1750, |
| 386 | 1600, |
| 387 | 1480, |
| 388 | 1370, |
| 389 | 1280, |
| 390 | 1200, |
| 391 | 1130, |
| 392 | 1070, |
| 393 | 1010, |
| 394 | 960, |
| 395 | 910, |
| 396 | }; |
| 397 | |
| 398 | static const int lab_current_limit_table[] = { |
| 399 | 200, |
| 400 | 400, |
| 401 | 600, |
| 402 | 800, |
| 403 | 1000, |
| 404 | 1200, |
| 405 | 1400, |
| 406 | 1600, |
| 407 | }; |
| 408 | |
| 409 | static const char * const lab_current_sense_table[] = { |
| 410 | "0.5x", |
| 411 | "1x", |
| 412 | "1.5x", |
| 413 | "2x" |
| 414 | }; |
| 415 | |
| 416 | static const int ibb_current_limit_table[] = { |
| 417 | 0, |
| 418 | 50, |
| 419 | 100, |
| 420 | 150, |
| 421 | 200, |
| 422 | 250, |
| 423 | 300, |
| 424 | 350, |
| 425 | 400, |
| 426 | 450, |
| 427 | 500, |
| 428 | 550, |
| 429 | 600, |
| 430 | 650, |
| 431 | 700, |
| 432 | 750, |
| 433 | 800, |
| 434 | 850, |
| 435 | 900, |
| 436 | 950, |
| 437 | 1000, |
| 438 | 1050, |
| 439 | 1100, |
| 440 | 1150, |
| 441 | 1200, |
| 442 | 1250, |
| 443 | 1300, |
| 444 | 1350, |
| 445 | 1400, |
| 446 | 1450, |
| 447 | 1500, |
| 448 | 1550, |
| 449 | }; |
| 450 | |
| 451 | static const int ibb_output_slew_ctl_table[] = { |
| 452 | 100, |
| 453 | 200, |
| 454 | 500, |
| 455 | 1000, |
| 456 | 2000, |
| 457 | 10000, |
| 458 | 12000, |
| 459 | 15000 |
| 460 | }; |
| 461 | |
| 462 | static const int ibb_debounce_table[] = { |
| 463 | 8, |
| 464 | 16, |
| 465 | 32, |
| 466 | 64, |
| 467 | }; |
| 468 | |
| 469 | static const int ibb_overload_debounce_table[] = { |
| 470 | 1, |
| 471 | 2, |
| 472 | 4, |
| 473 | 8 |
| 474 | }; |
| 475 | |
| 476 | static const int ibb_vreg_ok_deb_table[] = { |
| 477 | 4, |
| 478 | 8, |
| 479 | 16, |
| 480 | 32 |
| 481 | }; |
| 482 | |
| 483 | static const int lab_ps_thresh_table_v1[] = { |
| 484 | 20, |
| 485 | 30, |
| 486 | 40, |
| 487 | 50, |
| 488 | }; |
| 489 | |
| 490 | static const int lab_ps_thresh_table_v2[] = { |
| 491 | 50, |
| 492 | 60, |
| 493 | 70, |
| 494 | 80, |
| 495 | }; |
| 496 | |
| 497 | static const int lab_soft_start_table[] = { |
| 498 | 200, |
| 499 | 400, |
| 500 | 600, |
| 501 | 800, |
| 502 | }; |
| 503 | |
| 504 | static const int lab_rdson_nfet_table[] = { |
| 505 | 25, |
| 506 | 50, |
| 507 | 75, |
| 508 | 100, |
| 509 | }; |
| 510 | |
| 511 | static const int lab_rdson_pfet_table[] = { |
| 512 | 25, |
| 513 | 50, |
| 514 | 75, |
| 515 | 100, |
| 516 | }; |
| 517 | |
| 518 | static const int lab_max_precharge_table[] = { |
| 519 | 200, |
| 520 | 300, |
| 521 | 400, |
| 522 | 500, |
| 523 | }; |
| 524 | |
| 525 | static const int ibb_pfm_peak_curr_table[] = { |
| 526 | 150, |
| 527 | 200, |
| 528 | 250, |
| 529 | 300, |
| 530 | 350, |
| 531 | 400, |
| 532 | 450, |
| 533 | 500 |
| 534 | }; |
| 535 | |
| 536 | static const int ibb_pfm_hysteresis_table[] = { |
| 537 | 0, |
| 538 | 25, |
| 539 | 50, |
| 540 | 0 |
| 541 | }; |
| 542 | |
| 543 | static const int lab_vref_high_psrr_table[] = { |
| 544 | 350, |
| 545 | 400, |
| 546 | 450, |
| 547 | 500 |
| 548 | }; |
| 549 | |
| 550 | struct lab_regulator { |
| 551 | struct regulator_desc rdesc; |
| 552 | struct regulator_dev *rdev; |
| 553 | struct mutex lab_mutex; |
| 554 | |
| 555 | int lab_vreg_ok_irq; |
| 556 | int curr_volt; |
| 557 | int min_volt; |
| 558 | |
| 559 | int step_size; |
| 560 | int slew_rate; |
| 561 | int soft_start; |
| 562 | |
| 563 | int vreg_enabled; |
| 564 | }; |
| 565 | |
| 566 | struct ibb_regulator { |
| 567 | struct regulator_desc rdesc; |
| 568 | struct regulator_dev *rdev; |
| 569 | struct mutex ibb_mutex; |
| 570 | |
| 571 | int curr_volt; |
| 572 | int min_volt; |
| 573 | |
| 574 | int step_size; |
| 575 | int slew_rate; |
| 576 | int soft_start; |
| 577 | |
| 578 | u32 pwrup_dly; |
| 579 | u32 pwrdn_dly; |
| 580 | |
| 581 | int vreg_enabled; |
| 582 | int num_swire_trans; |
| 583 | }; |
| 584 | |
| 585 | struct qpnp_labibb { |
| 586 | struct device *dev; |
| 587 | struct platform_device *pdev; |
| 588 | struct regmap *regmap; |
| 589 | struct pmic_revid_data *pmic_rev_id; |
| 590 | u16 lab_base; |
| 591 | u16 ibb_base; |
| 592 | u8 lab_dig_major; |
| 593 | u8 ibb_dig_major; |
| 594 | struct lab_regulator lab_vreg; |
| 595 | struct ibb_regulator ibb_vreg; |
| 596 | const struct ibb_ver_ops *ibb_ver_ops; |
| 597 | const struct lab_ver_ops *lab_ver_ops; |
| 598 | struct mutex bus_mutex; |
| 599 | enum qpnp_labibb_mode mode; |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 600 | struct work_struct lab_vreg_ok_work; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 601 | bool standalone; |
| 602 | bool ttw_en; |
| 603 | bool in_ttw_mode; |
| 604 | bool ibb_settings_saved; |
| 605 | bool swire_control; |
| 606 | bool pbs_control; |
| 607 | bool ttw_force_lab_on; |
| 608 | bool skip_2nd_swire_cmd; |
| 609 | bool pfm_enable; |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 610 | bool notify_lab_vreg_ok_sts; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 611 | u32 swire_2nd_cmd_delay; |
| 612 | u32 swire_ibb_ps_enable_delay; |
| 613 | }; |
| 614 | |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 615 | static RAW_NOTIFIER_HEAD(labibb_notifier); |
| 616 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 617 | struct ibb_ver_ops { |
| 618 | int (*set_default_voltage)(struct qpnp_labibb *labibb, |
| 619 | bool use_default); |
| 620 | int (*set_voltage)(struct qpnp_labibb *labibb, int min_uV, int max_uV); |
| 621 | int (*sel_mode)(struct qpnp_labibb *labibb, bool is_ibb); |
| 622 | int (*get_mode)(struct qpnp_labibb *labibb); |
| 623 | int (*set_clk_div)(struct qpnp_labibb *labibb, u8 val); |
| 624 | int (*smart_ps_config)(struct qpnp_labibb *labibb, bool enable, |
| 625 | int num_swire_trans, int neg_curr_limit); |
| 626 | int (*soft_start_ctl)(struct qpnp_labibb *labibb, |
| 627 | struct device_node *of_node); |
| 628 | int (*voltage_at_one_pulse)(struct qpnp_labibb *labibb, u32 volt); |
| 629 | }; |
| 630 | |
| 631 | struct lab_ver_ops { |
| 632 | const char *ver_str; |
| 633 | int (*set_default_voltage)(struct qpnp_labibb *labibb, |
| 634 | bool default_pres); |
| 635 | int (*ps_ctl)(struct qpnp_labibb *labibb, |
| 636 | u32 thresh, bool enable); |
| 637 | }; |
| 638 | |
| 639 | enum ibb_settings_index { |
| 640 | IBB_PD_CTL = 0, |
| 641 | IBB_CURRENT_LIMIT, |
| 642 | IBB_RDSON_MNGMNT, |
| 643 | IBB_PWRUP_PWRDN_CTL_1, |
| 644 | IBB_PWRUP_PWRDN_CTL_2, |
| 645 | IBB_NLIMIT_DAC, |
| 646 | IBB_PS_CTL, |
| 647 | IBB_SOFT_START_CTL, |
| 648 | IBB_SETTINGS_MAX, |
| 649 | }; |
| 650 | |
| 651 | enum lab_settings_index { |
| 652 | LAB_SOFT_START_CTL = 0, |
| 653 | LAB_PS_CTL, |
| 654 | LAB_RDSON_MNGMNT, |
| 655 | LAB_SETTINGS_MAX, |
| 656 | }; |
| 657 | |
| 658 | struct settings { |
| 659 | u16 address; |
| 660 | u8 value; |
| 661 | bool sec_access; |
| 662 | }; |
| 663 | |
| 664 | #define SETTING(_id, _sec_access) \ |
| 665 | [_id] = { \ |
| 666 | .address = REG_##_id, \ |
| 667 | .sec_access = _sec_access, \ |
| 668 | } |
| 669 | |
| 670 | static struct settings ibb_settings[IBB_SETTINGS_MAX] = { |
| 671 | SETTING(IBB_PD_CTL, false), |
| 672 | SETTING(IBB_CURRENT_LIMIT, true), |
| 673 | SETTING(IBB_RDSON_MNGMNT, false), |
| 674 | SETTING(IBB_PWRUP_PWRDN_CTL_1, true), |
| 675 | SETTING(IBB_PWRUP_PWRDN_CTL_2, true), |
| 676 | SETTING(IBB_NLIMIT_DAC, false), |
| 677 | SETTING(IBB_PS_CTL, false), |
| 678 | SETTING(IBB_SOFT_START_CTL, false), |
| 679 | }; |
| 680 | |
| 681 | static struct settings lab_settings[LAB_SETTINGS_MAX] = { |
| 682 | SETTING(LAB_SOFT_START_CTL, false), |
| 683 | SETTING(LAB_PS_CTL, false), |
| 684 | SETTING(LAB_RDSON_MNGMNT, false), |
| 685 | }; |
| 686 | |
| 687 | static int |
| 688 | qpnp_labibb_read(struct qpnp_labibb *labibb, u16 address, |
| 689 | u8 *val, int count) |
| 690 | { |
| 691 | int rc = 0; |
| 692 | struct platform_device *pdev = labibb->pdev; |
| 693 | |
| 694 | mutex_lock(&(labibb->bus_mutex)); |
| 695 | rc = regmap_bulk_read(labibb->regmap, address, val, count); |
| 696 | if (rc < 0) |
| 697 | pr_err("SPMI read failed address=0x%02x sid=0x%02x rc=%d\n", |
| 698 | address, to_spmi_device(pdev->dev.parent)->usid, rc); |
| 699 | |
| 700 | mutex_unlock(&(labibb->bus_mutex)); |
| 701 | return rc; |
| 702 | } |
| 703 | |
| 704 | static int |
| 705 | qpnp_labibb_write(struct qpnp_labibb *labibb, u16 address, |
| 706 | u8 *val, int count) |
| 707 | { |
| 708 | int rc = 0; |
| 709 | struct platform_device *pdev = labibb->pdev; |
| 710 | |
| 711 | mutex_lock(&(labibb->bus_mutex)); |
| 712 | if (address == 0) { |
| 713 | pr_err("address cannot be zero address=0x%02x sid=0x%02x rc=%d\n", |
| 714 | address, to_spmi_device(pdev->dev.parent)->usid, rc); |
| 715 | rc = -EINVAL; |
| 716 | goto error; |
| 717 | } |
| 718 | |
| 719 | rc = regmap_bulk_write(labibb->regmap, address, val, count); |
| 720 | if (rc < 0) |
| 721 | pr_err("write failed address=0x%02x sid=0x%02x rc=%d\n", |
| 722 | address, to_spmi_device(pdev->dev.parent)->usid, rc); |
| 723 | |
| 724 | error: |
| 725 | mutex_unlock(&(labibb->bus_mutex)); |
| 726 | return rc; |
| 727 | } |
| 728 | |
| 729 | static int |
| 730 | qpnp_labibb_masked_write(struct qpnp_labibb *labibb, u16 address, |
| 731 | u8 mask, u8 val) |
| 732 | { |
| 733 | int rc = 0; |
| 734 | struct platform_device *pdev = labibb->pdev; |
| 735 | |
| 736 | mutex_lock(&(labibb->bus_mutex)); |
| 737 | if (address == 0) { |
| 738 | pr_err("address cannot be zero address=0x%02x sid=0x%02x\n", |
| 739 | address, to_spmi_device(pdev->dev.parent)->usid); |
| 740 | rc = -EINVAL; |
| 741 | goto error; |
| 742 | } |
| 743 | |
| 744 | rc = regmap_update_bits(labibb->regmap, address, mask, val); |
| 745 | if (rc < 0) |
| 746 | pr_err("spmi write failed: addr=%03X, rc=%d\n", address, rc); |
| 747 | |
| 748 | error: |
| 749 | mutex_unlock(&(labibb->bus_mutex)); |
| 750 | return rc; |
| 751 | } |
| 752 | |
| 753 | static int qpnp_labibb_sec_write(struct qpnp_labibb *labibb, u16 base, |
| 754 | u8 offset, u8 val) |
| 755 | { |
| 756 | int rc = 0; |
| 757 | u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE; |
| 758 | struct platform_device *pdev = labibb->pdev; |
| 759 | |
| 760 | mutex_lock(&(labibb->bus_mutex)); |
| 761 | if (base == 0) { |
| 762 | pr_err("base cannot be zero base=0x%02x sid=0x%02x\n", |
| 763 | base, to_spmi_device(pdev->dev.parent)->usid); |
| 764 | rc = -EINVAL; |
| 765 | goto error; |
| 766 | } |
| 767 | |
| 768 | rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS, |
| 769 | sec_val); |
| 770 | if (rc < 0) { |
| 771 | pr_err("register %x failed rc = %d\n", |
| 772 | base + REG_LAB_IBB_SEC_ACCESS, rc); |
| 773 | goto error; |
| 774 | } |
| 775 | |
| 776 | rc = regmap_write(labibb->regmap, base + offset, val); |
| 777 | if (rc < 0) |
| 778 | pr_err("failed: addr=%03X, rc=%d\n", |
| 779 | base + offset, rc); |
| 780 | |
| 781 | error: |
| 782 | mutex_unlock(&(labibb->bus_mutex)); |
| 783 | return rc; |
| 784 | } |
| 785 | |
| 786 | static int qpnp_labibb_sec_masked_write(struct qpnp_labibb *labibb, u16 base, |
| 787 | u8 offset, u8 mask, u8 val) |
| 788 | { |
| 789 | int rc = 0; |
| 790 | u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE; |
| 791 | struct platform_device *pdev = labibb->pdev; |
| 792 | |
| 793 | mutex_lock(&(labibb->bus_mutex)); |
| 794 | if (base == 0) { |
| 795 | pr_err("base cannot be zero base=0x%02x sid=0x%02x\n", |
| 796 | base, to_spmi_device(pdev->dev.parent)->usid); |
| 797 | rc = -EINVAL; |
| 798 | goto error; |
| 799 | } |
| 800 | |
| 801 | rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS, |
| 802 | sec_val); |
| 803 | if (rc < 0) { |
| 804 | pr_err("register %x failed rc = %d\n", |
| 805 | base + REG_LAB_IBB_SEC_ACCESS, rc); |
| 806 | goto error; |
| 807 | } |
| 808 | |
| 809 | rc = regmap_update_bits(labibb->regmap, base + offset, mask, val); |
| 810 | if (rc < 0) |
| 811 | pr_err("spmi write failed: addr=%03X, rc=%d\n", base, rc); |
| 812 | |
| 813 | error: |
| 814 | mutex_unlock(&(labibb->bus_mutex)); |
| 815 | return rc; |
| 816 | } |
| 817 | |
| 818 | static int qpnp_ibb_smart_ps_config_v1(struct qpnp_labibb *labibb, bool enable, |
| 819 | int num_swire_trans, int neg_curr_limit) |
| 820 | { |
| 821 | return 0; |
| 822 | } |
| 823 | |
| 824 | static int qpnp_ibb_smart_ps_config_v2(struct qpnp_labibb *labibb, bool enable, |
| 825 | int num_swire_trans, int neg_curr_limit) |
| 826 | { |
| 827 | u8 val; |
| 828 | int rc = 0; |
| 829 | |
| 830 | if (enable) { |
| 831 | val = IBB_NUM_SWIRE_PULSE_WAIT; |
| 832 | rc = qpnp_labibb_write(labibb, |
| 833 | labibb->ibb_base + REG_IBB_PS_CTL, &val, 1); |
| 834 | if (rc < 0) { |
| 835 | pr_err("write register %x failed rc = %d\n", |
| 836 | REG_IBB_PS_CTL, rc); |
| 837 | return rc; |
| 838 | } |
| 839 | } |
| 840 | |
| 841 | val = enable ? IBB_SMART_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT; |
| 842 | if (num_swire_trans) |
| 843 | val |= num_swire_trans; |
| 844 | else |
| 845 | val |= IBB_NUM_SWIRE_PULSE_WAIT; |
| 846 | |
| 847 | rc = qpnp_labibb_write(labibb, |
| 848 | labibb->ibb_base + REG_IBB_SMART_PS_CTL, &val, 1); |
| 849 | if (rc < 0) { |
| 850 | pr_err("write register %x failed rc = %d\n", |
| 851 | REG_IBB_SMART_PS_CTL, rc); |
| 852 | return rc; |
| 853 | } |
| 854 | |
| 855 | val = enable ? (neg_curr_limit ? neg_curr_limit : |
| 856 | IBB_DEFAULT_NLIMIT_DAC) : IBB_DEFAULT_NLIMIT_DAC; |
| 857 | |
| 858 | rc = qpnp_labibb_write(labibb, |
| 859 | labibb->ibb_base + REG_IBB_NLIMIT_DAC, &val, 1); |
| 860 | if (rc < 0) |
| 861 | pr_err("write register %x failed rc = %d\n", |
| 862 | REG_IBB_NLIMIT_DAC, rc); |
| 863 | |
| 864 | return rc; |
| 865 | } |
| 866 | |
| 867 | static int qpnp_labibb_sel_mode_v1(struct qpnp_labibb *labibb, bool is_ibb) |
| 868 | { |
| 869 | int rc = 0; |
| 870 | u8 val; |
| 871 | u16 base; |
| 872 | |
| 873 | val = (labibb->mode == QPNP_LABIBB_LCD_MODE) ? REG_LAB_IBB_LCD_MODE : |
| 874 | REG_LAB_IBB_AMOLED_MODE; |
| 875 | |
| 876 | base = is_ibb ? labibb->ibb_base : labibb->lab_base; |
| 877 | |
| 878 | rc = qpnp_labibb_sec_write(labibb, base, REG_LAB_LCD_AMOLED_SEL, |
| 879 | val); |
| 880 | if (rc < 0) |
| 881 | pr_err("register %x failed rc = %d\n", |
| 882 | REG_LAB_LCD_AMOLED_SEL, rc); |
| 883 | |
| 884 | return rc; |
| 885 | } |
| 886 | |
| 887 | static int qpnp_labibb_sel_mode_v2(struct qpnp_labibb *labibb, bool is_ibb) |
| 888 | { |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | static int qpnp_ibb_get_mode_v1(struct qpnp_labibb *labibb) |
| 893 | { |
| 894 | int rc = 0; |
| 895 | u8 val; |
| 896 | |
| 897 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL, |
| 898 | &val, 1); |
| 899 | if (rc < 0) |
| 900 | return rc; |
| 901 | |
| 902 | if (val == REG_LAB_IBB_AMOLED_MODE) |
| 903 | labibb->mode = QPNP_LABIBB_AMOLED_MODE; |
| 904 | else |
| 905 | labibb->mode = QPNP_LABIBB_LCD_MODE; |
| 906 | |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static int qpnp_ibb_get_mode_v2(struct qpnp_labibb *labibb) |
| 911 | { |
| 912 | labibb->mode = QPNP_LABIBB_AMOLED_MODE; |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | static int qpnp_ibb_set_clk_div_v1(struct qpnp_labibb *labibb, u8 val) |
| 918 | { |
| 919 | int rc = 0; |
| 920 | |
| 921 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_CLK_DIV, |
| 922 | &val, 1); |
| 923 | |
| 924 | return rc; |
| 925 | } |
| 926 | |
| 927 | static int qpnp_ibb_set_clk_div_v2(struct qpnp_labibb *labibb, u8 val) |
| 928 | { |
| 929 | int rc = 0; |
| 930 | |
| 931 | val |= IBB_CLK_DIV_OVERRIDE_EN; |
| 932 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 933 | REG_IBB_CLK_DIV, IBB_CLK_DIV_MASK | |
| 934 | IBB_CLK_DIV_OVERRIDE_EN, val); |
| 935 | |
| 936 | return rc; |
| 937 | } |
| 938 | |
| 939 | static int qpnp_ibb_soft_start_ctl_v1(struct qpnp_labibb *labibb, |
| 940 | struct device_node *of_node) |
| 941 | { |
| 942 | int rc = 0; |
| 943 | u8 val; |
| 944 | u32 tmp; |
| 945 | |
| 946 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-soft-start", |
| 947 | &(labibb->ibb_vreg.soft_start)); |
| 948 | if (rc < 0) { |
| 949 | pr_err("qcom,qpnp-ibb-soft-start is missing, rc = %d\n", |
| 950 | rc); |
| 951 | return rc; |
| 952 | } |
| 953 | |
| 954 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-discharge-resistor", |
| 955 | &tmp); |
| 956 | if (!rc) { |
| 957 | for (val = 0; val < ARRAY_SIZE(ibb_dischg_res_table); val++) { |
| 958 | if (ibb_dischg_res_table[val] == tmp) |
| 959 | break; |
| 960 | } |
| 961 | |
| 962 | if (val == ARRAY_SIZE(ibb_dischg_res_table)) { |
| 963 | pr_err("Invalid value in qcom,qpnp-ibb-discharge-resistor\n"); |
| 964 | return -EINVAL; |
| 965 | } |
| 966 | |
| 967 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 968 | REG_IBB_SOFT_START_CTL, &val, 1); |
| 969 | if (rc < 0) { |
| 970 | pr_err("write to register %x failed rc = %d\n", |
| 971 | REG_IBB_SOFT_START_CTL, rc); |
| 972 | return rc; |
| 973 | } |
| 974 | } |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
| 979 | static int qpnp_ibb_soft_start_ctl_v2(struct qpnp_labibb *labibb, |
| 980 | struct device_node *of_node) |
| 981 | { |
| 982 | return 0; |
| 983 | } |
| 984 | |
| 985 | static int qpnp_ibb_vreg_ok_ctl(struct qpnp_labibb *labibb, |
| 986 | struct device_node *of_node) |
| 987 | { |
| 988 | u8 val = 0; |
| 989 | int rc = 0, i = 0; |
| 990 | u32 tmp; |
| 991 | |
| 992 | if (labibb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) |
| 993 | return rc; |
| 994 | |
| 995 | val |= IBB_VREG_OK_EN_OVERLOAD_BLANK; |
| 996 | |
| 997 | rc = of_property_read_u32(of_node, |
| 998 | "qcom,qpnp-ibb-overload-debounce", &tmp); |
| 999 | if (rc < 0) { |
| 1000 | pr_err("failed to read qcom,qpnp-ibb-overload-debounce rc=%d\n", |
| 1001 | rc); |
| 1002 | return rc; |
| 1003 | } |
| 1004 | |
| 1005 | for (i = 0; i < ARRAY_SIZE(ibb_overload_debounce_table); i++) |
| 1006 | if (ibb_overload_debounce_table[i] == tmp) |
| 1007 | break; |
| 1008 | |
| 1009 | if (i == ARRAY_SIZE(ibb_overload_debounce_table)) { |
| 1010 | pr_err("Invalid value in qcom,qpnp-ibb-overload-debounce\n"); |
| 1011 | return -EINVAL; |
| 1012 | } |
| 1013 | val |= i << IBB_VREG_OK_OVERLOAD_DEB_SHIFT; |
| 1014 | |
| 1015 | rc = of_property_read_u32(of_node, |
| 1016 | "qcom,qpnp-ibb-vreg-ok-debounce", &tmp); |
| 1017 | if (rc < 0) { |
| 1018 | pr_err("failed to read qcom,qpnp-ibb-vreg-ok-debounce rc=%d\n", |
| 1019 | rc); |
| 1020 | return rc; |
| 1021 | } |
| 1022 | |
| 1023 | for (i = 0; i < ARRAY_SIZE(ibb_vreg_ok_deb_table); i++) |
| 1024 | if (ibb_vreg_ok_deb_table[i] == tmp) |
| 1025 | break; |
| 1026 | |
| 1027 | if (i == ARRAY_SIZE(ibb_vreg_ok_deb_table)) { |
| 1028 | pr_err("Invalid value in qcom,qpnp-ibb-vreg-ok-debounce\n"); |
| 1029 | return -EINVAL; |
| 1030 | } |
| 1031 | val |= i; |
| 1032 | |
| 1033 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 1034 | REG_IBB_VREG_OK_CTL, |
| 1035 | &val, 1); |
| 1036 | if (rc < 0) |
| 1037 | pr_err("write to register %x failed rc = %d\n", |
| 1038 | REG_IBB_VREG_OK_CTL, rc); |
| 1039 | |
| 1040 | return rc; |
| 1041 | } |
| 1042 | |
| 1043 | static int qpnp_ibb_set_default_voltage_v1(struct qpnp_labibb *labibb, |
| 1044 | bool use_default) |
| 1045 | { |
| 1046 | u8 val; |
| 1047 | int rc = 0; |
| 1048 | |
| 1049 | if (!use_default) { |
| 1050 | if (labibb->ibb_vreg.curr_volt < labibb->ibb_vreg.min_volt) { |
| 1051 | pr_err("qcom,qpnp-ibb-init-voltage %d is less than the the minimum voltage %d", |
| 1052 | labibb->ibb_vreg.curr_volt, labibb->ibb_vreg.min_volt); |
| 1053 | return -EINVAL; |
| 1054 | } |
| 1055 | |
| 1056 | val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt - |
| 1057 | labibb->ibb_vreg.min_volt, |
| 1058 | labibb->ibb_vreg.step_size); |
| 1059 | if (val > IBB_VOLTAGE_SET_MASK) { |
| 1060 | pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld", |
| 1061 | labibb->ibb_vreg.curr_volt, |
| 1062 | labibb->ibb_vreg.min_volt + |
| 1063 | labibb->ibb_vreg.step_size * |
| 1064 | IBB_VOLTAGE_SET_MASK); |
| 1065 | return -EINVAL; |
| 1066 | } |
| 1067 | |
| 1068 | labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size + |
| 1069 | labibb->ibb_vreg.min_volt; |
| 1070 | val |= IBB_VOLTAGE_OVERRIDE_EN; |
| 1071 | } else { |
| 1072 | val = 0; |
| 1073 | } |
| 1074 | |
| 1075 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 1076 | REG_IBB_VOLTAGE, IBB_VOLTAGE_SET_MASK | |
| 1077 | IBB_VOLTAGE_OVERRIDE_EN, val); |
| 1078 | if (rc < 0) |
| 1079 | pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, |
| 1080 | rc); |
| 1081 | |
| 1082 | return rc; |
| 1083 | } |
| 1084 | |
| 1085 | static int qpnp_ibb_set_default_voltage_v2(struct qpnp_labibb *labibb, |
| 1086 | bool use_default) |
| 1087 | { |
| 1088 | int rc = 0; |
| 1089 | u8 val; |
| 1090 | |
| 1091 | val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt, |
| 1092 | labibb->ibb_vreg.step_size); |
| 1093 | if (val > IBB_VOLTAGE_SET_MASK) { |
| 1094 | pr_err("Invalid qcom,qpnp-ibb-init-voltage property %d", |
| 1095 | labibb->ibb_vreg.curr_volt); |
| 1096 | return -EINVAL; |
| 1097 | } |
| 1098 | |
| 1099 | labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size; |
| 1100 | |
| 1101 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 1102 | REG_IBB_DEFAULT_VOLTAGE, &val, 1); |
| 1103 | if (rc < 0) |
| 1104 | pr_err("write to register %x failed rc = %d\n", |
| 1105 | REG_IBB_DEFAULT_VOLTAGE, rc); |
| 1106 | |
| 1107 | return rc; |
| 1108 | } |
| 1109 | |
| 1110 | static int qpnp_ibb_set_voltage_v1(struct qpnp_labibb *labibb, |
| 1111 | int min_uV, int max_uV) |
| 1112 | { |
| 1113 | int rc, new_uV; |
| 1114 | u8 val; |
| 1115 | |
| 1116 | if (min_uV < labibb->ibb_vreg.min_volt) { |
| 1117 | pr_err("min_uV %d is less than min_volt %d", min_uV, |
| 1118 | labibb->ibb_vreg.min_volt); |
| 1119 | return -EINVAL; |
| 1120 | } |
| 1121 | |
| 1122 | val = DIV_ROUND_UP(min_uV - labibb->ibb_vreg.min_volt, |
| 1123 | labibb->ibb_vreg.step_size); |
| 1124 | new_uV = val * labibb->ibb_vreg.step_size + labibb->ibb_vreg.min_volt; |
| 1125 | |
| 1126 | if (new_uV > max_uV) { |
| 1127 | pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, |
| 1128 | min_uV, max_uV); |
| 1129 | return -EINVAL; |
| 1130 | } |
| 1131 | |
| 1132 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 1133 | REG_IBB_VOLTAGE, |
| 1134 | IBB_VOLTAGE_SET_MASK | |
| 1135 | IBB_VOLTAGE_OVERRIDE_EN, |
| 1136 | val | IBB_VOLTAGE_OVERRIDE_EN); |
| 1137 | |
| 1138 | if (rc < 0) { |
| 1139 | pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, |
| 1140 | rc); |
| 1141 | return rc; |
| 1142 | } |
| 1143 | |
| 1144 | if (new_uV > labibb->ibb_vreg.curr_volt) { |
| 1145 | val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt, |
| 1146 | labibb->ibb_vreg.step_size); |
| 1147 | udelay(val * labibb->ibb_vreg.slew_rate); |
| 1148 | } |
| 1149 | labibb->ibb_vreg.curr_volt = new_uV; |
| 1150 | |
| 1151 | return 0; |
| 1152 | } |
| 1153 | |
| 1154 | static int qpnp_ibb_set_voltage_v2(struct qpnp_labibb *labibb, |
| 1155 | int min_uV, int max_uV) |
| 1156 | { |
| 1157 | int rc, new_uV; |
| 1158 | u8 val; |
| 1159 | |
| 1160 | val = DIV_ROUND_UP(min_uV, labibb->ibb_vreg.step_size); |
| 1161 | new_uV = val * labibb->ibb_vreg.step_size; |
| 1162 | |
| 1163 | if (new_uV > max_uV) { |
| 1164 | pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, |
| 1165 | min_uV, max_uV); |
| 1166 | return -EINVAL; |
| 1167 | } |
| 1168 | |
| 1169 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 1170 | REG_IBB_VOLTAGE, &val, 1); |
| 1171 | if (rc < 0) { |
| 1172 | pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, |
| 1173 | rc); |
| 1174 | return rc; |
| 1175 | } |
| 1176 | |
| 1177 | if (new_uV > labibb->ibb_vreg.curr_volt) { |
| 1178 | val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt, |
| 1179 | labibb->ibb_vreg.step_size); |
| 1180 | udelay(val * labibb->ibb_vreg.slew_rate); |
| 1181 | } |
| 1182 | labibb->ibb_vreg.curr_volt = new_uV; |
| 1183 | |
| 1184 | return 0; |
| 1185 | } |
| 1186 | |
| 1187 | static int qpnp_ibb_output_voltage_at_one_pulse_v1(struct qpnp_labibb *labibb, |
| 1188 | u32 volt) |
| 1189 | { |
| 1190 | int rc = 0; |
| 1191 | u8 val; |
| 1192 | |
| 1193 | /* |
| 1194 | * Set the output voltage 100mV lower as the IBB HW module |
| 1195 | * counts one pulse less in SWIRE mode. |
| 1196 | */ |
| 1197 | val = DIV_ROUND_UP((volt - MIN_OUTPUT_PULSE_VOLTAGE_MV), |
| 1198 | OUTPUT_VOLTAGE_STEP_MV) - 1; |
| 1199 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 1200 | REG_IBB_SWIRE_CTL, |
| 1201 | IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, |
| 1202 | val); |
| 1203 | if (rc < 0) |
| 1204 | pr_err("write register %x failed rc = %d\n", |
| 1205 | REG_IBB_SWIRE_CTL, rc); |
| 1206 | |
| 1207 | return rc; |
| 1208 | } |
| 1209 | |
| 1210 | static int qpnp_ibb_output_voltage_at_one_pulse_v2(struct qpnp_labibb *labibb, |
| 1211 | u32 volt) |
| 1212 | { |
| 1213 | int rc = 0; |
| 1214 | u8 val; |
| 1215 | |
| 1216 | val = DIV_ROUND_UP(volt, OUTPUT_VOLTAGE_STEP_MV); |
| 1217 | |
| 1218 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 1219 | REG_IBB_SWIRE_CTL, |
| 1220 | IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, |
| 1221 | val); |
| 1222 | if (rc < 0) |
| 1223 | pr_err("qpnp_labiibb_write register %x failed rc = %d\n", |
| 1224 | REG_IBB_SWIRE_CTL, rc); |
| 1225 | |
| 1226 | return rc; |
| 1227 | } |
| 1228 | |
| 1229 | static const struct ibb_ver_ops ibb_ops_v1 = { |
| 1230 | .set_default_voltage = qpnp_ibb_set_default_voltage_v1, |
| 1231 | .set_voltage = qpnp_ibb_set_voltage_v1, |
| 1232 | .sel_mode = qpnp_labibb_sel_mode_v1, |
| 1233 | .get_mode = qpnp_ibb_get_mode_v1, |
| 1234 | .set_clk_div = qpnp_ibb_set_clk_div_v1, |
| 1235 | .smart_ps_config = qpnp_ibb_smart_ps_config_v1, |
| 1236 | .soft_start_ctl = qpnp_ibb_soft_start_ctl_v1, |
| 1237 | .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v1, |
| 1238 | }; |
| 1239 | |
| 1240 | static const struct ibb_ver_ops ibb_ops_v2 = { |
| 1241 | .set_default_voltage = qpnp_ibb_set_default_voltage_v2, |
| 1242 | .set_voltage = qpnp_ibb_set_voltage_v2, |
| 1243 | .sel_mode = qpnp_labibb_sel_mode_v2, |
| 1244 | .get_mode = qpnp_ibb_get_mode_v2, |
| 1245 | .set_clk_div = qpnp_ibb_set_clk_div_v2, |
| 1246 | .smart_ps_config = qpnp_ibb_smart_ps_config_v2, |
| 1247 | .soft_start_ctl = qpnp_ibb_soft_start_ctl_v2, |
| 1248 | .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v2, |
| 1249 | }; |
| 1250 | |
| 1251 | static int qpnp_lab_set_default_voltage_v1(struct qpnp_labibb *labibb, |
| 1252 | bool default_pres) |
| 1253 | { |
| 1254 | u8 val; |
| 1255 | int rc = 0; |
| 1256 | |
| 1257 | if (!default_pres) { |
| 1258 | if (labibb->lab_vreg.curr_volt < labibb->lab_vreg.min_volt) { |
| 1259 | pr_err("qcom,qpnp-lab-init-voltage %d is less than the the minimum voltage %d", |
| 1260 | labibb->lab_vreg.curr_volt, |
| 1261 | labibb->lab_vreg.min_volt); |
| 1262 | return -EINVAL; |
| 1263 | } |
| 1264 | |
| 1265 | val = DIV_ROUND_UP(labibb->lab_vreg.curr_volt - |
| 1266 | labibb->lab_vreg.min_volt, |
| 1267 | labibb->lab_vreg.step_size); |
| 1268 | if (val > LAB_VOLTAGE_SET_MASK) { |
| 1269 | pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld", |
| 1270 | labibb->lab_vreg.curr_volt, |
| 1271 | labibb->lab_vreg.min_volt + |
| 1272 | labibb->lab_vreg.step_size * |
| 1273 | LAB_VOLTAGE_SET_MASK); |
| 1274 | return -EINVAL; |
| 1275 | } |
| 1276 | |
| 1277 | labibb->lab_vreg.curr_volt = val * labibb->lab_vreg.step_size + |
| 1278 | labibb->lab_vreg.min_volt; |
| 1279 | val |= LAB_VOLTAGE_OVERRIDE_EN; |
| 1280 | |
| 1281 | } else { |
| 1282 | val = 0; |
| 1283 | } |
| 1284 | |
| 1285 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1286 | REG_LAB_VOLTAGE, LAB_VOLTAGE_SET_MASK | |
| 1287 | LAB_VOLTAGE_OVERRIDE_EN, val); |
| 1288 | |
| 1289 | if (rc < 0) |
| 1290 | pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE, |
| 1291 | rc); |
| 1292 | |
| 1293 | return rc; |
| 1294 | } |
| 1295 | |
| 1296 | static int qpnp_lab_set_default_voltage_v2(struct qpnp_labibb *labibb, |
| 1297 | bool default_pres) |
| 1298 | { |
| 1299 | int rc = 0; |
| 1300 | u8 val; |
| 1301 | |
| 1302 | val = DIV_ROUND_UP((labibb->lab_vreg.curr_volt |
| 1303 | - labibb->lab_vreg.min_volt), labibb->lab_vreg.step_size); |
| 1304 | |
| 1305 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1306 | REG_LAB_VOUT_DEFAULT, &val, 1); |
| 1307 | if (rc < 0) |
| 1308 | pr_err("write to register %x failed rc = %d\n", |
| 1309 | REG_LAB_VOUT_DEFAULT, rc); |
| 1310 | |
| 1311 | return rc; |
| 1312 | } |
| 1313 | |
| 1314 | static int qpnp_lab_ps_ctl_v1(struct qpnp_labibb *labibb, |
| 1315 | u32 thresh, bool enable) |
| 1316 | { |
| 1317 | int rc = 0; |
| 1318 | u8 val; |
| 1319 | |
| 1320 | if (enable) { |
| 1321 | for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v1); val++) |
| 1322 | if (lab_ps_thresh_table_v1[val] == thresh) |
| 1323 | break; |
| 1324 | |
| 1325 | if (val == ARRAY_SIZE(lab_ps_thresh_table_v1)) { |
| 1326 | pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n"); |
| 1327 | return -EINVAL; |
| 1328 | } |
| 1329 | |
| 1330 | val |= LAB_PS_CTL_EN; |
| 1331 | } else { |
| 1332 | val = 0; |
| 1333 | } |
| 1334 | |
| 1335 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1336 | REG_LAB_PS_CTL, &val, 1); |
| 1337 | |
| 1338 | if (rc < 0) |
| 1339 | pr_err("write register %x failed rc = %d\n", |
| 1340 | REG_LAB_PS_CTL, rc); |
| 1341 | |
| 1342 | return rc; |
| 1343 | } |
| 1344 | |
| 1345 | static int qpnp_lab_ps_ctl_v2(struct qpnp_labibb *labibb, |
| 1346 | u32 thresh, bool enable) |
| 1347 | { |
| 1348 | int rc = 0; |
| 1349 | u8 val; |
| 1350 | |
| 1351 | if (enable) { |
| 1352 | for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v2); val++) |
| 1353 | if (lab_ps_thresh_table_v2[val] == thresh) |
| 1354 | break; |
| 1355 | |
| 1356 | if (val == ARRAY_SIZE(lab_ps_thresh_table_v2)) { |
| 1357 | pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n"); |
| 1358 | return -EINVAL; |
| 1359 | } |
| 1360 | |
| 1361 | val |= LAB_PS_CTL_EN; |
| 1362 | } else { |
| 1363 | val = 0; |
| 1364 | } |
| 1365 | |
| 1366 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1367 | REG_LAB_PS_CTL, &val, 1); |
| 1368 | |
| 1369 | if (rc < 0) |
| 1370 | pr_err("write register %x failed rc = %d\n", |
| 1371 | REG_LAB_PS_CTL, rc); |
| 1372 | |
| 1373 | return rc; |
| 1374 | } |
| 1375 | |
| 1376 | static const struct lab_ver_ops lab_ops_v1 = { |
| 1377 | .set_default_voltage = qpnp_lab_set_default_voltage_v1, |
| 1378 | .ps_ctl = qpnp_lab_ps_ctl_v1, |
| 1379 | }; |
| 1380 | |
| 1381 | static const struct lab_ver_ops lab_ops_v2 = { |
| 1382 | .set_default_voltage = qpnp_lab_set_default_voltage_v2, |
| 1383 | .ps_ctl = qpnp_lab_ps_ctl_v2, |
| 1384 | }; |
| 1385 | |
| 1386 | static int qpnp_labibb_get_matching_idx(const char *val) |
| 1387 | { |
| 1388 | int i; |
| 1389 | |
| 1390 | for (i = 0; i < ARRAY_SIZE(lab_current_sense_table); i++) |
| 1391 | if (!strcmp(lab_current_sense_table[i], val)) |
| 1392 | return i; |
| 1393 | |
| 1394 | return -EINVAL; |
| 1395 | } |
| 1396 | |
| 1397 | static int qpnp_ibb_set_mode(struct qpnp_labibb *labibb, enum ibb_mode mode) |
| 1398 | { |
| 1399 | int rc; |
| 1400 | u8 val; |
| 1401 | |
| 1402 | if (mode == IBB_SW_CONTROL_EN) |
| 1403 | val = IBB_ENABLE_CTL_MODULE_EN; |
| 1404 | else if (mode == IBB_HW_CONTROL) |
| 1405 | val = IBB_ENABLE_CTL_SWIRE_RDY; |
| 1406 | else if (mode == IBB_HW_SW_CONTROL) |
| 1407 | val = IBB_ENABLE_CTL_MODULE_EN | IBB_ENABLE_CTL_SWIRE_RDY; |
| 1408 | else if (mode == IBB_SW_CONTROL_DIS) |
| 1409 | val = 0; |
| 1410 | else |
| 1411 | return -EINVAL; |
| 1412 | |
| 1413 | rc = qpnp_labibb_masked_write(labibb, |
| 1414 | labibb->ibb_base + REG_IBB_ENABLE_CTL, |
| 1415 | IBB_ENABLE_CTL_MASK, val); |
| 1416 | if (rc < 0) |
| 1417 | pr_err("Unable to configure IBB_ENABLE_CTL rc=%d\n", rc); |
| 1418 | |
| 1419 | return rc; |
| 1420 | } |
| 1421 | |
| 1422 | static int qpnp_ibb_ps_config(struct qpnp_labibb *labibb, bool enable) |
| 1423 | { |
| 1424 | u8 val; |
| 1425 | int rc; |
| 1426 | |
| 1427 | val = enable ? IBB_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT; |
| 1428 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PS_CTL, |
| 1429 | &val, 1); |
| 1430 | if (rc < 0) { |
| 1431 | pr_err("write register %x failed rc = %d\n", |
| 1432 | REG_IBB_PS_CTL, rc); |
| 1433 | return rc; |
| 1434 | } |
| 1435 | |
| 1436 | val = enable ? 0 : IBB_DEFAULT_NLIMIT_DAC; |
| 1437 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_NLIMIT_DAC, |
| 1438 | &val, 1); |
| 1439 | if (rc < 0) |
| 1440 | pr_err("write register %x failed rc = %d\n", |
| 1441 | REG_IBB_NLIMIT_DAC, rc); |
| 1442 | return rc; |
| 1443 | } |
| 1444 | |
| 1445 | static int qpnp_lab_dt_init(struct qpnp_labibb *labibb, |
| 1446 | struct device_node *of_node) |
| 1447 | { |
| 1448 | int rc = 0; |
| 1449 | u8 i, val, mask; |
| 1450 | u32 tmp; |
| 1451 | |
| 1452 | /* |
| 1453 | * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by |
| 1454 | * GPIO selector. |
| 1455 | */ |
| 1456 | if (labibb->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE) { |
| 1457 | rc = labibb->ibb_ver_ops->sel_mode(labibb, 0); |
| 1458 | if (rc < 0) |
| 1459 | return rc; |
| 1460 | } |
| 1461 | |
| 1462 | val = 0; |
| 1463 | if (of_property_read_bool(of_node, "qcom,qpnp-lab-full-pull-down")) |
| 1464 | val |= LAB_PD_CTL_STRONG_PULL; |
| 1465 | |
| 1466 | if (!of_property_read_bool(of_node, "qcom,qpnp-lab-pull-down-enable")) |
| 1467 | val |= LAB_PD_CTL_DISABLE_PD; |
| 1468 | |
| 1469 | mask = LAB_PD_CTL_EN_MASK | LAB_PD_CTL_STRENGTH_MASK; |
| 1470 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + REG_LAB_PD_CTL, |
| 1471 | mask, val); |
| 1472 | |
| 1473 | if (rc < 0) { |
| 1474 | pr_err("write to register %x failed rc = %d\n", |
| 1475 | REG_LAB_PD_CTL, rc); |
| 1476 | return rc; |
| 1477 | } |
| 1478 | |
| 1479 | rc = of_property_read_u32(of_node, |
| 1480 | "qcom,qpnp-lab-switching-clock-frequency", &tmp); |
| 1481 | if (!rc) { |
| 1482 | for (val = 0; val < ARRAY_SIZE(lab_clk_div_table); val++) |
| 1483 | if (lab_clk_div_table[val] == tmp) |
| 1484 | break; |
| 1485 | |
| 1486 | if (val == ARRAY_SIZE(lab_clk_div_table)) { |
| 1487 | pr_err("Invalid value in qpnp-lab-switching-clock-frequency\n"); |
| 1488 | return -EINVAL; |
| 1489 | } |
| 1490 | |
| 1491 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1492 | REG_LAB_CLK_DIV, &val, 1); |
| 1493 | if (rc < 0) { |
| 1494 | pr_err("write to register %x failed rc = %d\n", |
| 1495 | REG_LAB_CLK_DIV, rc); |
| 1496 | return rc; |
| 1497 | } |
| 1498 | } |
| 1499 | |
| 1500 | if (of_property_read_bool(of_node, |
| 1501 | "qcom,qpnp-lab-limit-max-current-enable")) { |
| 1502 | val = LAB_CURRENT_LIMIT_EN_BIT; |
| 1503 | |
| 1504 | rc = of_property_read_u32(of_node, |
| 1505 | "qcom,qpnp-lab-limit-maximum-current", &tmp); |
| 1506 | |
| 1507 | if (rc < 0) { |
| 1508 | pr_err("get qcom,qpnp-lab-limit-maximum-current failed rc = %d\n", |
| 1509 | rc); |
| 1510 | return rc; |
| 1511 | } |
| 1512 | |
| 1513 | for (i = 0; i < ARRAY_SIZE(lab_current_limit_table); i++) |
| 1514 | if (lab_current_limit_table[i] == tmp) |
| 1515 | break; |
| 1516 | |
| 1517 | if (i == ARRAY_SIZE(lab_current_limit_table)) { |
| 1518 | pr_err("Invalid value in qcom,qpnp-lab-limit-maximum-current\n"); |
| 1519 | return -EINVAL; |
| 1520 | } |
| 1521 | |
| 1522 | val |= i; |
| 1523 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1524 | REG_LAB_CURRENT_LIMIT, &val, 1); |
| 1525 | if (rc < 0) { |
| 1526 | pr_err("write to register %x failed rc = %d\n", |
| 1527 | REG_LAB_CURRENT_LIMIT, rc); |
| 1528 | return rc; |
| 1529 | } |
| 1530 | } |
| 1531 | |
| 1532 | if (of_property_read_bool(of_node, |
| 1533 | "qcom,qpnp-lab-ring-suppression-enable")) { |
| 1534 | val = LAB_RING_SUPPRESSION_CTL_EN; |
| 1535 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1536 | REG_LAB_RING_SUPPRESSION_CTL, &val, 1); |
| 1537 | if (rc < 0) { |
| 1538 | pr_err("write to register %x failed rc = %d\n", |
| 1539 | REG_LAB_RING_SUPPRESSION_CTL, rc); |
| 1540 | return rc; |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | if (of_property_read_bool(of_node, "qcom,qpnp-lab-ps-enable")) { |
| 1545 | |
| 1546 | rc = of_property_read_u32(of_node, |
| 1547 | "qcom,qpnp-lab-ps-threshold", &tmp); |
| 1548 | |
| 1549 | if (rc < 0) { |
| 1550 | pr_err("get qcom,qpnp-lab-ps-threshold failed rc = %d\n", |
| 1551 | rc); |
| 1552 | return rc; |
| 1553 | } |
| 1554 | rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, true); |
| 1555 | if (rc < 0) |
| 1556 | return rc; |
| 1557 | } else { |
| 1558 | rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, false); |
| 1559 | if (rc < 0) |
| 1560 | return rc; |
| 1561 | } |
| 1562 | |
| 1563 | val = 0; |
| 1564 | mask = 0; |
| 1565 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-pfet-size", &tmp); |
| 1566 | if (!rc) { |
| 1567 | for (val = 0; val < ARRAY_SIZE(lab_rdson_pfet_table); val++) |
| 1568 | if (tmp == lab_rdson_pfet_table[val]) |
| 1569 | break; |
| 1570 | |
| 1571 | if (val == ARRAY_SIZE(lab_rdson_pfet_table)) { |
| 1572 | pr_err("Invalid value in qcom,qpnp-lab-pfet-size\n"); |
| 1573 | return -EINVAL; |
| 1574 | } |
| 1575 | val |= LAB_RDSON_MNGMNT_PFET_SLEW_EN; |
| 1576 | mask |= LAB_RDSON_MNGMNT_PFET_MASK | |
| 1577 | LAB_RDSON_MNGMNT_PFET_SLEW_EN; |
| 1578 | } |
| 1579 | |
| 1580 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-nfet-size", |
| 1581 | &tmp); |
| 1582 | if (!rc) { |
| 1583 | for (i = 0; i < ARRAY_SIZE(lab_rdson_nfet_table); i++) |
| 1584 | if (tmp == lab_rdson_nfet_table[i]) |
| 1585 | break; |
| 1586 | |
| 1587 | if (i == ARRAY_SIZE(lab_rdson_nfet_table)) { |
| 1588 | pr_err("Invalid value in qcom,qpnp-lab-nfet-size\n"); |
| 1589 | return -EINVAL; |
| 1590 | } |
| 1591 | |
| 1592 | val |= i << LAB_RDSON_MNGMNT_NFET_SHIFT; |
| 1593 | val |= LAB_RDSON_MNGMNT_NFET_SLEW_EN; |
| 1594 | mask |= LAB_RDSON_MNGMNT_NFET_MASK | |
| 1595 | LAB_RDSON_MNGMNT_NFET_SLEW_EN; |
| 1596 | } |
| 1597 | |
| 1598 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1599 | REG_LAB_RDSON_MNGMNT, mask, val); |
| 1600 | if (rc < 0) { |
| 1601 | pr_err("write to register %x failed rc = %d\n", |
| 1602 | REG_LAB_RDSON_MNGMNT, rc); |
| 1603 | return rc; |
| 1604 | } |
| 1605 | |
| 1606 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-voltage", |
| 1607 | &(labibb->lab_vreg.curr_volt)); |
| 1608 | if (rc < 0) { |
| 1609 | pr_err("get qcom,qpnp-lab-init-voltage failed, rc = %d\n", |
| 1610 | rc); |
| 1611 | return rc; |
| 1612 | } |
| 1613 | |
| 1614 | if (of_property_read_bool(of_node, |
| 1615 | "qcom,qpnp-lab-use-default-voltage")) |
| 1616 | rc = labibb->lab_ver_ops->set_default_voltage(labibb, true); |
| 1617 | else |
| 1618 | rc = labibb->lab_ver_ops->set_default_voltage(labibb, false); |
| 1619 | |
| 1620 | if (rc < 0) |
| 1621 | return rc; |
| 1622 | |
| 1623 | if (of_property_read_bool(of_node, |
| 1624 | "qcom,qpnp-lab-enable-sw-high-psrr")) { |
| 1625 | val = LAB_EN_SW_HIGH_PSRR_MODE; |
| 1626 | |
| 1627 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1628 | REG_LAB_SW_HIGH_PSRR_CTL, &val, 1); |
| 1629 | if (rc < 0) { |
| 1630 | pr_err("write to register %x failed rc = %d\n", |
| 1631 | REG_LAB_SW_HIGH_PSRR_CTL, rc); |
| 1632 | return rc; |
| 1633 | } |
| 1634 | } |
| 1635 | |
| 1636 | rc = of_property_read_u32(of_node, |
| 1637 | "qcom,qpnp-lab-ldo-pulldown-enable", (u32 *)&val); |
| 1638 | if (!rc) { |
| 1639 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1640 | REG_LAB_LDO_PD_CTL, &val, 1); |
| 1641 | if (rc < 0) { |
| 1642 | pr_err("write to register %x failed rc = %d\n", |
| 1643 | REG_LAB_LDO_PD_CTL, rc); |
| 1644 | return rc; |
| 1645 | } |
| 1646 | } |
| 1647 | |
| 1648 | rc = of_property_read_u32(of_node, |
| 1649 | "qcom,qpnp-lab-high-psrr-src-select", &tmp); |
| 1650 | if (!rc) { |
| 1651 | val = tmp; |
| 1652 | |
| 1653 | rc = of_property_read_u32(of_node, |
| 1654 | "qcom,qpnp-lab-vref-high-psrr-select", &tmp); |
| 1655 | if (rc < 0) { |
| 1656 | pr_err("get qcom,qpnp-lab-vref-high-psrr-select failed rc = %d\n", |
| 1657 | rc); |
| 1658 | return rc; |
| 1659 | } |
| 1660 | |
| 1661 | for (i = 0; i < ARRAY_SIZE(lab_vref_high_psrr_table); i++) |
| 1662 | if (lab_vref_high_psrr_table[i] == tmp) |
| 1663 | break; |
| 1664 | |
| 1665 | if (i == ARRAY_SIZE(lab_vref_high_psrr_table)) { |
| 1666 | pr_err("Invalid value in qpnp-lab-vref-high-psrr-selct\n"); |
| 1667 | return -EINVAL; |
| 1668 | } |
| 1669 | val |= (i << LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT); |
| 1670 | |
| 1671 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1672 | REG_LAB_VPH_ENVELOP_CTL, |
| 1673 | LAB_VREF_HIGH_PSRR_SEL_MASK | |
| 1674 | LAB_SEL_HW_HIGH_PSRR_SRC_MASK, |
| 1675 | val); |
| 1676 | |
| 1677 | if (rc < 0) { |
| 1678 | pr_err("write to register %x failed rc = %d\n", |
| 1679 | REG_LAB_VPH_ENVELOP_CTL, rc); |
| 1680 | return rc; |
| 1681 | } |
| 1682 | } |
| 1683 | |
| 1684 | if (labibb->swire_control) { |
| 1685 | rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); |
| 1686 | if (rc < 0) { |
| 1687 | pr_err("Unable to set SWIRE_RDY rc=%d\n", rc); |
| 1688 | return rc; |
| 1689 | } |
| 1690 | } |
| 1691 | |
| 1692 | return 0; |
| 1693 | } |
| 1694 | |
| 1695 | #define LAB_CURRENT_MAX_1600MA 0x7 |
| 1696 | #define LAB_CURRENT_MAX_400MA 0x1 |
| 1697 | static int qpnp_lab_pfm_disable(struct qpnp_labibb *labibb) |
| 1698 | { |
| 1699 | int rc = 0; |
| 1700 | u8 val, mask; |
| 1701 | |
| 1702 | mutex_lock(&(labibb->lab_vreg.lab_mutex)); |
| 1703 | if (!labibb->pfm_enable) { |
| 1704 | pr_debug("PFM already disabled\n"); |
| 1705 | goto out; |
| 1706 | } |
| 1707 | |
| 1708 | val = 0; |
| 1709 | mask = LAB_PFM_EN_BIT; |
| 1710 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1711 | REG_LAB_PFM_CTL, mask, val); |
| 1712 | if (rc < 0) { |
| 1713 | pr_err("Write register %x failed rc = %d\n", |
| 1714 | REG_LAB_PFM_CTL, rc); |
| 1715 | goto out; |
| 1716 | } |
| 1717 | |
| 1718 | val = LAB_CURRENT_MAX_1600MA; |
| 1719 | mask = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_LIMIT_MASK; |
| 1720 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1721 | REG_LAB_CURRENT_LIMIT, mask, val); |
| 1722 | if (rc < 0) { |
| 1723 | pr_err("Write register %x failed rc = %d\n", |
| 1724 | REG_LAB_CURRENT_LIMIT, rc); |
| 1725 | goto out; |
| 1726 | } |
| 1727 | |
| 1728 | labibb->pfm_enable = false; |
| 1729 | out: |
| 1730 | mutex_unlock(&(labibb->lab_vreg.lab_mutex)); |
| 1731 | return rc; |
| 1732 | } |
| 1733 | |
| 1734 | static int qpnp_lab_pfm_enable(struct qpnp_labibb *labibb) |
| 1735 | { |
| 1736 | int rc = 0; |
| 1737 | u8 val, mask; |
| 1738 | |
| 1739 | mutex_lock(&(labibb->lab_vreg.lab_mutex)); |
| 1740 | if (labibb->pfm_enable) { |
| 1741 | pr_debug("PFM already enabled\n"); |
| 1742 | goto out; |
| 1743 | } |
| 1744 | |
| 1745 | /* Wait for ~100uS */ |
| 1746 | usleep_range(100, 105); |
| 1747 | |
| 1748 | val = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_MAX_400MA; |
| 1749 | mask = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_LIMIT_MASK; |
| 1750 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1751 | REG_LAB_CURRENT_LIMIT, mask, val); |
| 1752 | if (rc < 0) { |
| 1753 | pr_err("Write register %x failed rc = %d\n", |
| 1754 | REG_LAB_CURRENT_LIMIT, rc); |
| 1755 | goto out; |
| 1756 | } |
| 1757 | |
| 1758 | /* Wait for ~100uS */ |
| 1759 | usleep_range(100, 105); |
| 1760 | |
| 1761 | val = LAB_PFM_EN_BIT; |
| 1762 | mask = LAB_PFM_EN_BIT; |
| 1763 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1764 | REG_LAB_PFM_CTL, mask, val); |
| 1765 | if (rc < 0) { |
| 1766 | pr_err("Write register %x failed rc = %d\n", |
| 1767 | REG_LAB_PFM_CTL, rc); |
| 1768 | goto out; |
| 1769 | } |
| 1770 | |
| 1771 | labibb->pfm_enable = true; |
| 1772 | out: |
| 1773 | mutex_unlock(&(labibb->lab_vreg.lab_mutex)); |
| 1774 | return rc; |
| 1775 | } |
| 1776 | |
| 1777 | static int qpnp_labibb_restore_settings(struct qpnp_labibb *labibb) |
| 1778 | { |
| 1779 | int rc, i; |
| 1780 | |
| 1781 | for (i = 0; i < ARRAY_SIZE(ibb_settings); i++) { |
| 1782 | if (ibb_settings[i].sec_access) |
| 1783 | rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, |
| 1784 | ibb_settings[i].address, |
| 1785 | ibb_settings[i].value); |
| 1786 | else |
| 1787 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 1788 | ibb_settings[i].address, |
| 1789 | &ibb_settings[i].value, 1); |
| 1790 | |
| 1791 | if (rc < 0) { |
| 1792 | pr_err("write to register %x failed rc = %d\n", |
| 1793 | ibb_settings[i].address, rc); |
| 1794 | return rc; |
| 1795 | } |
| 1796 | } |
| 1797 | |
| 1798 | for (i = 0; i < ARRAY_SIZE(lab_settings); i++) { |
| 1799 | if (lab_settings[i].sec_access) |
| 1800 | rc = qpnp_labibb_sec_write(labibb, labibb->lab_base, |
| 1801 | lab_settings[i].address, |
| 1802 | lab_settings[i].value); |
| 1803 | else |
| 1804 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1805 | lab_settings[i].address, |
| 1806 | &lab_settings[i].value, 1); |
| 1807 | |
| 1808 | if (rc < 0) { |
| 1809 | pr_err("write to register %x failed rc = %d\n", |
| 1810 | lab_settings[i].address, rc); |
| 1811 | return rc; |
| 1812 | } |
| 1813 | } |
| 1814 | |
| 1815 | return 0; |
| 1816 | } |
| 1817 | |
| 1818 | static int qpnp_labibb_save_settings(struct qpnp_labibb *labibb) |
| 1819 | { |
| 1820 | int rc, i; |
| 1821 | |
| 1822 | for (i = 0; i < ARRAY_SIZE(ibb_settings); i++) { |
| 1823 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 1824 | ibb_settings[i].address, &ibb_settings[i].value, 1); |
| 1825 | if (rc < 0) { |
| 1826 | pr_err("read register %x failed rc = %d\n", |
| 1827 | ibb_settings[i].address, rc); |
| 1828 | return rc; |
| 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | for (i = 0; i < ARRAY_SIZE(lab_settings); i++) { |
| 1833 | rc = qpnp_labibb_read(labibb, labibb->lab_base + |
| 1834 | lab_settings[i].address, &lab_settings[i].value, 1); |
| 1835 | if (rc < 0) { |
| 1836 | pr_err("read register %x failed rc = %d\n", |
| 1837 | lab_settings[i].address, rc); |
| 1838 | return rc; |
| 1839 | } |
| 1840 | } |
| 1841 | |
| 1842 | return 0; |
| 1843 | } |
| 1844 | |
| 1845 | static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) |
| 1846 | { |
| 1847 | int rc = 0; |
| 1848 | u8 val; |
| 1849 | |
| 1850 | val = 0; |
| 1851 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL, |
| 1852 | &val, 1); |
| 1853 | if (rc < 0) { |
| 1854 | pr_err("read register %x failed rc = %d\n", |
| 1855 | REG_IBB_PD_CTL, rc); |
| 1856 | return rc; |
| 1857 | } |
| 1858 | |
| 1859 | val = 0; |
| 1860 | rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, |
| 1861 | REG_IBB_PWRUP_PWRDN_CTL_1, val); |
| 1862 | if (rc < 0) { |
| 1863 | pr_err("write to register %x failed rc = %d\n", |
| 1864 | REG_IBB_PWRUP_PWRDN_CTL_1, rc); |
| 1865 | return rc; |
| 1866 | } |
| 1867 | |
| 1868 | val = IBB_WAIT_MBG_OK; |
| 1869 | rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, |
| 1870 | REG_IBB_PWRUP_PWRDN_CTL_2, |
| 1871 | IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK, val); |
| 1872 | if (rc < 0) { |
| 1873 | pr_err("write to register %x failed rc = %d\n", |
| 1874 | REG_IBB_PWRUP_PWRDN_CTL_2, rc); |
| 1875 | return rc; |
| 1876 | } |
| 1877 | |
| 1878 | val = IBB_NFET_SLEW_EN | IBB_PFET_SLEW_EN | IBB_OVERRIDE_NFET_SW_SIZE | |
| 1879 | IBB_OVERRIDE_PFET_SW_SIZE; |
| 1880 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 1881 | REG_IBB_RDSON_MNGMNT, 0xFF, val); |
| 1882 | if (rc < 0) { |
| 1883 | pr_err("write to register %x failed rc = %d\n", |
| 1884 | REG_IBB_RDSON_MNGMNT, rc); |
| 1885 | return rc; |
| 1886 | } |
| 1887 | |
| 1888 | val = IBB_CURRENT_LIMIT_EN | IBB_CURRENT_MAX_500MA | |
| 1889 | (IBB_ILIMIT_COUNT_CYC8 << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT); |
| 1890 | rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, |
| 1891 | REG_IBB_CURRENT_LIMIT, val); |
| 1892 | if (rc < 0) |
| 1893 | pr_err("write to register %x failed rc = %d\n", |
| 1894 | REG_IBB_CURRENT_LIMIT, rc); |
| 1895 | |
| 1896 | return rc; |
| 1897 | } |
| 1898 | |
| 1899 | static int qpnp_labibb_ttw_enter_ibb_pmi8996(struct qpnp_labibb *labibb) |
| 1900 | { |
| 1901 | int rc; |
| 1902 | u8 val; |
| 1903 | |
| 1904 | val = IBB_BYPASS_PWRDN_DLY2_BIT | IBB_FAST_STARTUP; |
| 1905 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL, |
| 1906 | &val, 1); |
| 1907 | if (rc < 0) |
| 1908 | pr_err("write to register %x failed rc = %d\n", |
| 1909 | REG_IBB_SPARE_CTL, rc); |
| 1910 | |
| 1911 | return rc; |
| 1912 | } |
| 1913 | |
| 1914 | static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) |
| 1915 | { |
| 1916 | int rc; |
| 1917 | u8 val; |
| 1918 | |
| 1919 | rc = qpnp_ibb_ps_config(labibb, true); |
| 1920 | if (rc < 0) { |
| 1921 | pr_err("Failed to enable ibb_ps_config rc=%d\n", rc); |
| 1922 | return rc; |
| 1923 | } |
| 1924 | |
| 1925 | val = IBB_SOFT_START_CHARGING_RESISTOR_16K; |
| 1926 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 1927 | REG_IBB_SOFT_START_CTL, &val, 1); |
| 1928 | if (rc < 0) { |
| 1929 | pr_err("write to register %x failed rc = %d\n", |
| 1930 | REG_IBB_SOFT_START_CTL, rc); |
| 1931 | return rc; |
| 1932 | } |
| 1933 | |
| 1934 | val = IBB_MODULE_RDY_EN; |
| 1935 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1936 | REG_IBB_MODULE_RDY, &val, 1); |
| 1937 | if (rc < 0) |
| 1938 | pr_err("write to register %x failed rc = %d\n", |
| 1939 | REG_IBB_MODULE_RDY, rc); |
| 1940 | |
| 1941 | return rc; |
| 1942 | } |
| 1943 | |
| 1944 | static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) |
| 1945 | { |
| 1946 | int rc = 0; |
| 1947 | u8 val; |
| 1948 | |
| 1949 | /* Save the IBB settings before they get modified for TTW mode */ |
| 1950 | if (!labibb->ibb_settings_saved) { |
| 1951 | rc = qpnp_labibb_save_settings(labibb); |
| 1952 | if (rc) { |
| 1953 | pr_err("Error in storing IBB setttings, rc=%d\n", rc); |
| 1954 | return rc; |
| 1955 | } |
| 1956 | labibb->ibb_settings_saved = true; |
| 1957 | } |
| 1958 | |
| 1959 | if (labibb->ttw_force_lab_on) { |
| 1960 | val = LAB_MODULE_RDY_EN; |
| 1961 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1962 | REG_LAB_MODULE_RDY, &val, 1); |
| 1963 | if (rc < 0) { |
| 1964 | pr_err("write to register %x failed rc = %d\n", |
| 1965 | REG_LAB_MODULE_RDY, rc); |
| 1966 | return rc; |
| 1967 | } |
| 1968 | |
| 1969 | /* Prevents LAB being turned off by IBB */ |
| 1970 | val = LAB_ENABLE_CTL_EN; |
| 1971 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1972 | REG_LAB_ENABLE_CTL, &val, 1); |
| 1973 | if (rc < 0) { |
| 1974 | pr_err("write to register %x failed rc = %d\n", |
| 1975 | REG_LAB_ENABLE_CTL, rc); |
| 1976 | return rc; |
| 1977 | } |
| 1978 | |
| 1979 | val = LAB_RDSON_MNGMNT_NFET_SLEW_EN | |
| 1980 | LAB_RDSON_MNGMNT_PFET_SLEW_EN | |
| 1981 | LAB_RDSON_NFET_SW_SIZE_QUARTER | |
| 1982 | LAB_RDSON_PFET_SW_SIZE_QUARTER; |
| 1983 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 1984 | REG_LAB_RDSON_MNGMNT, &val, 1); |
| 1985 | if (rc < 0) { |
| 1986 | pr_err("write to register %x failed rc = %d\n", |
| 1987 | REG_LAB_RDSON_MNGMNT, rc); |
| 1988 | return rc; |
| 1989 | } |
| 1990 | |
| 1991 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 1992 | REG_LAB_PS_CTL, LAB_PS_CTL_EN, LAB_PS_CTL_EN); |
| 1993 | if (rc < 0) { |
| 1994 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 1995 | REG_LAB_PS_CTL, rc); |
| 1996 | return rc; |
| 1997 | } |
| 1998 | } else { |
| 1999 | val = LAB_PD_CTL_DISABLE_PD; |
| 2000 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2001 | REG_LAB_PD_CTL, &val, 1); |
| 2002 | if (rc < 0) { |
| 2003 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2004 | REG_LAB_PD_CTL, rc); |
| 2005 | return rc; |
| 2006 | } |
| 2007 | |
| 2008 | val = LAB_SPARE_DISABLE_SCP_BIT; |
| 2009 | if (labibb->pmic_rev_id->pmic_subtype != PMI8950_SUBTYPE) |
| 2010 | val |= LAB_SPARE_TOUCH_WAKE_BIT; |
| 2011 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2012 | REG_LAB_SPARE_CTL, &val, 1); |
| 2013 | if (rc < 0) { |
| 2014 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2015 | REG_LAB_SPARE_CTL, rc); |
| 2016 | return rc; |
| 2017 | } |
| 2018 | |
| 2019 | val = 0; |
| 2020 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2021 | REG_LAB_SOFT_START_CTL, &val, 1); |
| 2022 | if (rc < 0) { |
| 2023 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2024 | REG_LAB_SOFT_START_CTL, rc); |
| 2025 | return rc; |
| 2026 | } |
| 2027 | } |
| 2028 | |
| 2029 | rc = qpnp_labibb_ttw_enter_ibb_common(labibb); |
| 2030 | if (rc) { |
| 2031 | pr_err("Failed to apply TTW ibb common settings rc=%d\n", rc); |
| 2032 | return rc; |
| 2033 | } |
| 2034 | |
| 2035 | switch (labibb->pmic_rev_id->pmic_subtype) { |
| 2036 | case PMI8996_SUBTYPE: |
| 2037 | rc = qpnp_labibb_ttw_enter_ibb_pmi8996(labibb); |
| 2038 | break; |
| 2039 | case PMI8950_SUBTYPE: |
| 2040 | rc = qpnp_labibb_ttw_enter_ibb_pmi8950(labibb); |
| 2041 | break; |
| 2042 | } |
| 2043 | if (rc < 0) { |
| 2044 | pr_err("Failed to configure TTW-enter for IBB rc=%d\n", rc); |
| 2045 | return rc; |
| 2046 | } |
| 2047 | |
| 2048 | rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); |
| 2049 | if (rc < 0) { |
| 2050 | pr_err("Unable to set SWIRE_RDY rc = %d\n", rc); |
| 2051 | return rc; |
| 2052 | } |
| 2053 | labibb->in_ttw_mode = true; |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
| 2057 | static int qpnp_labibb_ttw_exit_ibb_common(struct qpnp_labibb *labibb) |
| 2058 | { |
| 2059 | int rc; |
| 2060 | u8 val; |
| 2061 | |
| 2062 | val = IBB_FASTER_PFET_OFF; |
| 2063 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL, |
| 2064 | &val, 1); |
| 2065 | if (rc < 0) |
| 2066 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2067 | REG_IBB_SPARE_CTL, rc); |
| 2068 | |
| 2069 | return rc; |
| 2070 | } |
| 2071 | |
| 2072 | static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) |
| 2073 | { |
| 2074 | int rc = 0; |
| 2075 | u8 val; |
| 2076 | |
| 2077 | if (!labibb->ibb_settings_saved) { |
| 2078 | pr_err("IBB settings are not saved!\n"); |
| 2079 | return -EINVAL; |
| 2080 | } |
| 2081 | |
| 2082 | /* Restore the IBB settings back to switch back to normal mode */ |
| 2083 | rc = qpnp_labibb_restore_settings(labibb); |
| 2084 | if (rc < 0) { |
| 2085 | pr_err("Error in restoring IBB setttings, rc=%d\n", rc); |
| 2086 | return rc; |
| 2087 | } |
| 2088 | |
| 2089 | if (labibb->ttw_force_lab_on) { |
| 2090 | val = 0; |
| 2091 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2092 | REG_LAB_ENABLE_CTL, &val, 1); |
| 2093 | if (rc < 0) { |
| 2094 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2095 | REG_LAB_ENABLE_CTL, rc); |
| 2096 | return rc; |
| 2097 | } |
| 2098 | } else { |
| 2099 | val = LAB_PD_CTL_STRONG_PULL; |
| 2100 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2101 | REG_LAB_PD_CTL, &val, 1); |
| 2102 | if (rc < 0) { |
| 2103 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2104 | REG_LAB_PD_CTL, rc); |
| 2105 | return rc; |
| 2106 | } |
| 2107 | |
| 2108 | val = 0; |
| 2109 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2110 | REG_LAB_SPARE_CTL, &val, 1); |
| 2111 | if (rc < 0) { |
| 2112 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2113 | REG_LAB_SPARE_CTL, rc); |
| 2114 | return rc; |
| 2115 | } |
| 2116 | } |
| 2117 | |
| 2118 | switch (labibb->pmic_rev_id->pmic_subtype) { |
| 2119 | case PMI8996_SUBTYPE: |
| 2120 | case PMI8994_SUBTYPE: |
| 2121 | case PMI8950_SUBTYPE: |
| 2122 | rc = qpnp_labibb_ttw_exit_ibb_common(labibb); |
| 2123 | break; |
| 2124 | } |
| 2125 | if (rc < 0) { |
| 2126 | pr_err("Failed to configure TTW-exit for IBB rc=%d\n", rc); |
| 2127 | return rc; |
| 2128 | } |
| 2129 | |
| 2130 | labibb->in_ttw_mode = false; |
| 2131 | return rc; |
| 2132 | } |
| 2133 | |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 2134 | static void qpnp_lab_vreg_notifier_work(struct work_struct *work) |
| 2135 | { |
| 2136 | int rc = 0; |
| 2137 | u16 retries = 1000, dly = 5000; |
| 2138 | u8 val; |
| 2139 | struct qpnp_labibb *labibb = container_of(work, struct qpnp_labibb, |
| 2140 | lab_vreg_ok_work); |
| 2141 | |
| 2142 | while (retries--) { |
| 2143 | rc = qpnp_labibb_read(labibb, labibb->lab_base + |
| 2144 | REG_LAB_STATUS1, &val, 1); |
| 2145 | if (rc < 0) { |
| 2146 | pr_err("read register %x failed rc = %d\n", |
| 2147 | REG_LAB_STATUS1, rc); |
| 2148 | return; |
| 2149 | } |
| 2150 | |
| 2151 | if (val & LAB_STATUS1_VREG_OK) { |
| 2152 | raw_notifier_call_chain(&labibb_notifier, |
| 2153 | LAB_VREG_OK, NULL); |
| 2154 | break; |
| 2155 | } |
| 2156 | |
| 2157 | usleep_range(dly, dly + 100); |
| 2158 | } |
| 2159 | |
| 2160 | if (!retries) |
| 2161 | pr_err("LAB_VREG_OK not set, failed to notify\n"); |
| 2162 | } |
| 2163 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2164 | static int qpnp_labibb_regulator_enable(struct qpnp_labibb *labibb) |
| 2165 | { |
| 2166 | int rc; |
| 2167 | u8 val; |
| 2168 | int dly; |
| 2169 | int retries; |
| 2170 | bool enabled = false; |
| 2171 | |
| 2172 | if (labibb->ttw_en && !labibb->ibb_vreg.vreg_enabled && |
| 2173 | labibb->in_ttw_mode) { |
| 2174 | rc = qpnp_labibb_regulator_ttw_mode_exit(labibb); |
| 2175 | if (rc) { |
| 2176 | pr_err("Error in exiting TTW mode rc = %d\n", rc); |
| 2177 | return rc; |
| 2178 | } |
| 2179 | } |
| 2180 | |
| 2181 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN); |
| 2182 | if (rc) { |
| 2183 | pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); |
| 2184 | return rc; |
| 2185 | } |
| 2186 | |
| 2187 | /* total delay time */ |
| 2188 | dly = labibb->lab_vreg.soft_start + labibb->ibb_vreg.soft_start |
| 2189 | + labibb->ibb_vreg.pwrup_dly; |
| 2190 | usleep_range(dly, dly + 100); |
| 2191 | |
| 2192 | /* after this delay, lab should be enabled */ |
| 2193 | rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_STATUS1, |
| 2194 | &val, 1); |
| 2195 | if (rc < 0) { |
| 2196 | pr_err("read register %x failed rc = %d\n", |
| 2197 | REG_LAB_STATUS1, rc); |
| 2198 | goto err_out; |
| 2199 | } |
| 2200 | |
| 2201 | pr_debug("soft=%d %d up=%d dly=%d\n", |
| 2202 | labibb->lab_vreg.soft_start, labibb->ibb_vreg.soft_start, |
| 2203 | labibb->ibb_vreg.pwrup_dly, dly); |
| 2204 | |
| 2205 | if (!(val & LAB_STATUS1_VREG_OK)) { |
| 2206 | pr_err("failed for LAB %x\n", val); |
| 2207 | goto err_out; |
| 2208 | } |
| 2209 | |
| 2210 | /* poll IBB_STATUS to make sure ibb had been enabled */ |
| 2211 | dly = labibb->ibb_vreg.soft_start + labibb->ibb_vreg.pwrup_dly; |
| 2212 | retries = 10; |
| 2213 | while (retries--) { |
| 2214 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 2215 | REG_IBB_STATUS1, &val, 1); |
| 2216 | if (rc < 0) { |
| 2217 | pr_err("read register %x failed rc = %d\n", |
| 2218 | REG_IBB_STATUS1, rc); |
| 2219 | goto err_out; |
| 2220 | } |
| 2221 | |
| 2222 | if (val & IBB_STATUS1_VREG_OK) { |
| 2223 | enabled = true; |
| 2224 | break; |
| 2225 | } |
| 2226 | usleep_range(dly, dly + 100); |
| 2227 | } |
| 2228 | |
| 2229 | if (!enabled) { |
| 2230 | pr_err("failed for IBB %x\n", val); |
| 2231 | goto err_out; |
| 2232 | } |
| 2233 | |
| 2234 | labibb->lab_vreg.vreg_enabled = 1; |
| 2235 | labibb->ibb_vreg.vreg_enabled = 1; |
| 2236 | |
| 2237 | return 0; |
| 2238 | err_out: |
| 2239 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); |
| 2240 | if (rc < 0) { |
| 2241 | pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); |
| 2242 | return rc; |
| 2243 | } |
| 2244 | return -EINVAL; |
| 2245 | } |
| 2246 | |
| 2247 | static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb) |
| 2248 | { |
| 2249 | int rc; |
| 2250 | u8 val; |
| 2251 | int dly; |
| 2252 | int retries; |
| 2253 | bool disabled = false; |
| 2254 | |
| 2255 | /* |
| 2256 | * When TTW mode is enabled and LABIBB regulators are disabled, it is |
| 2257 | * recommended not to disable IBB through IBB_ENABLE_CTL when switching |
| 2258 | * to SWIRE control on entering TTW mode. Hence, just enter TTW mode |
| 2259 | * and mark the regulators disabled. When we exit TTW mode, normal |
| 2260 | * mode settings will be restored anyways and regulators will be |
| 2261 | * enabled as before. |
| 2262 | */ |
| 2263 | if (labibb->ttw_en && !labibb->in_ttw_mode) { |
| 2264 | rc = qpnp_labibb_regulator_ttw_mode_enter(labibb); |
| 2265 | if (rc < 0) { |
| 2266 | pr_err("Error in entering TTW mode rc = %d\n", rc); |
| 2267 | return rc; |
| 2268 | } |
| 2269 | labibb->lab_vreg.vreg_enabled = 0; |
| 2270 | labibb->ibb_vreg.vreg_enabled = 0; |
| 2271 | return 0; |
| 2272 | } |
| 2273 | |
| 2274 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); |
| 2275 | if (rc < 0) { |
| 2276 | pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); |
| 2277 | return rc; |
| 2278 | } |
| 2279 | |
| 2280 | /* poll IBB_STATUS to make sure ibb had been disabled */ |
| 2281 | dly = labibb->ibb_vreg.pwrdn_dly; |
| 2282 | retries = 2; |
| 2283 | while (retries--) { |
| 2284 | usleep_range(dly, dly + 100); |
| 2285 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 2286 | REG_IBB_STATUS1, &val, 1); |
| 2287 | if (rc < 0) { |
| 2288 | pr_err("read register %x failed rc = %d\n", |
| 2289 | REG_IBB_STATUS1, rc); |
| 2290 | return rc; |
| 2291 | } |
| 2292 | |
| 2293 | if (!(val & IBB_STATUS1_VREG_OK)) { |
| 2294 | disabled = true; |
| 2295 | break; |
| 2296 | } |
| 2297 | } |
| 2298 | |
| 2299 | if (!disabled) { |
| 2300 | pr_err("failed for IBB %x\n", val); |
| 2301 | return -EINVAL; |
| 2302 | } |
| 2303 | |
| 2304 | if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && |
| 2305 | labibb->mode == QPNP_LABIBB_LCD_MODE) { |
| 2306 | rc = qpnp_lab_pfm_disable(labibb); |
| 2307 | if (rc < 0) { |
| 2308 | pr_err("Error in disabling PFM, rc=%d\n", rc); |
| 2309 | return rc; |
| 2310 | } |
| 2311 | } |
| 2312 | |
| 2313 | labibb->lab_vreg.vreg_enabled = 0; |
| 2314 | labibb->ibb_vreg.vreg_enabled = 0; |
| 2315 | |
| 2316 | return 0; |
| 2317 | } |
| 2318 | |
| 2319 | static int qpnp_lab_regulator_enable(struct regulator_dev *rdev) |
| 2320 | { |
| 2321 | int rc; |
| 2322 | u8 val; |
| 2323 | |
| 2324 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 2325 | |
| 2326 | if (labibb->skip_2nd_swire_cmd) { |
| 2327 | rc = qpnp_ibb_ps_config(labibb, false); |
| 2328 | if (rc < 0) { |
| 2329 | pr_err("Failed to disable IBB PS rc=%d\n", rc); |
| 2330 | return rc; |
| 2331 | } |
| 2332 | } |
| 2333 | |
| 2334 | if (!labibb->lab_vreg.vreg_enabled && !labibb->swire_control) { |
| 2335 | |
| 2336 | if (!labibb->standalone) |
| 2337 | return qpnp_labibb_regulator_enable(labibb); |
| 2338 | |
| 2339 | val = LAB_ENABLE_CTL_EN; |
| 2340 | rc = qpnp_labibb_write(labibb, |
| 2341 | labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); |
| 2342 | if (rc < 0) { |
| 2343 | pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n", |
| 2344 | REG_LAB_ENABLE_CTL, rc); |
| 2345 | return rc; |
| 2346 | } |
| 2347 | |
| 2348 | udelay(labibb->lab_vreg.soft_start); |
| 2349 | |
| 2350 | rc = qpnp_labibb_read(labibb, labibb->lab_base + |
| 2351 | REG_LAB_STATUS1, &val, 1); |
| 2352 | if (rc < 0) { |
| 2353 | pr_err("qpnp_lab_regulator_enable read register %x failed rc = %d\n", |
| 2354 | REG_LAB_STATUS1, rc); |
| 2355 | return rc; |
| 2356 | } |
| 2357 | |
| 2358 | if ((val & LAB_STATUS1_VREG_OK_MASK) != LAB_STATUS1_VREG_OK) { |
| 2359 | pr_err("qpnp_lab_regulator_enable failed\n"); |
| 2360 | return -EINVAL; |
| 2361 | } |
| 2362 | |
| 2363 | labibb->lab_vreg.vreg_enabled = 1; |
| 2364 | } |
| 2365 | |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 2366 | if (labibb->notify_lab_vreg_ok_sts) |
| 2367 | schedule_work(&labibb->lab_vreg_ok_work); |
| 2368 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2369 | return 0; |
| 2370 | } |
| 2371 | |
| 2372 | static int qpnp_lab_regulator_disable(struct regulator_dev *rdev) |
| 2373 | { |
| 2374 | int rc; |
| 2375 | u8 val; |
| 2376 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 2377 | |
| 2378 | if (labibb->lab_vreg.vreg_enabled && !labibb->swire_control) { |
| 2379 | |
| 2380 | if (!labibb->standalone) |
| 2381 | return qpnp_labibb_regulator_disable(labibb); |
| 2382 | |
| 2383 | val = 0; |
| 2384 | rc = qpnp_labibb_write(labibb, |
| 2385 | labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); |
| 2386 | if (rc < 0) { |
| 2387 | pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n", |
| 2388 | REG_LAB_ENABLE_CTL, rc); |
| 2389 | return rc; |
| 2390 | } |
| 2391 | |
| 2392 | labibb->lab_vreg.vreg_enabled = 0; |
| 2393 | } |
| 2394 | return 0; |
| 2395 | } |
| 2396 | |
| 2397 | static int qpnp_lab_regulator_is_enabled(struct regulator_dev *rdev) |
| 2398 | { |
| 2399 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 2400 | |
| 2401 | if (labibb->swire_control) |
| 2402 | return 0; |
| 2403 | |
| 2404 | return labibb->lab_vreg.vreg_enabled; |
| 2405 | } |
| 2406 | |
| 2407 | static int qpnp_lab_regulator_set_voltage(struct regulator_dev *rdev, |
| 2408 | int min_uV, int max_uV, unsigned int *selector) |
| 2409 | { |
| 2410 | int rc, new_uV; |
| 2411 | u8 val; |
| 2412 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 2413 | |
| 2414 | if (labibb->swire_control) |
| 2415 | return 0; |
| 2416 | |
| 2417 | if (min_uV < labibb->lab_vreg.min_volt) { |
| 2418 | pr_err("min_uV %d is less than min_volt %d", min_uV, |
| 2419 | labibb->lab_vreg.min_volt); |
| 2420 | return -EINVAL; |
| 2421 | } |
| 2422 | |
| 2423 | val = DIV_ROUND_UP(min_uV - labibb->lab_vreg.min_volt, |
| 2424 | labibb->lab_vreg.step_size); |
| 2425 | new_uV = val * labibb->lab_vreg.step_size + labibb->lab_vreg.min_volt; |
| 2426 | |
| 2427 | if (new_uV > max_uV) { |
| 2428 | pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, |
| 2429 | min_uV, max_uV); |
| 2430 | return -EINVAL; |
| 2431 | } |
| 2432 | |
| 2433 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 2434 | REG_LAB_VOLTAGE, |
| 2435 | LAB_VOLTAGE_SET_MASK | |
| 2436 | LAB_VOLTAGE_OVERRIDE_EN, |
| 2437 | val | LAB_VOLTAGE_OVERRIDE_EN); |
| 2438 | |
| 2439 | if (rc < 0) { |
| 2440 | pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE, |
| 2441 | rc); |
| 2442 | return rc; |
| 2443 | } |
| 2444 | |
| 2445 | if (new_uV > labibb->lab_vreg.curr_volt) { |
| 2446 | val = DIV_ROUND_UP(new_uV - labibb->lab_vreg.curr_volt, |
| 2447 | labibb->lab_vreg.step_size); |
| 2448 | udelay(val * labibb->lab_vreg.slew_rate); |
| 2449 | } |
| 2450 | labibb->lab_vreg.curr_volt = new_uV; |
| 2451 | |
| 2452 | return 0; |
| 2453 | } |
| 2454 | |
| 2455 | static int qpnp_skip_swire_command(struct qpnp_labibb *labibb) |
| 2456 | { |
| 2457 | int rc = 0, retry = 50, dly; |
| 2458 | u8 reg; |
| 2459 | |
| 2460 | do { |
| 2461 | /* poll for ibb vreg_ok */ |
| 2462 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 2463 | REG_IBB_STATUS1, ®, 1); |
| 2464 | if (rc < 0) { |
| 2465 | pr_err("Failed to read ibb_status1 reg rc=%d\n", rc); |
| 2466 | return rc; |
| 2467 | } |
| 2468 | if ((reg & IBB_STATUS1_VREG_OK_MASK) == IBB_STATUS1_VREG_OK) |
| 2469 | break; |
| 2470 | |
| 2471 | /* poll delay */ |
| 2472 | usleep_range(500, 600); |
| 2473 | |
| 2474 | } while (--retry); |
| 2475 | |
| 2476 | if (!retry) { |
| 2477 | pr_err("ibb vreg_ok failed to turn-on\n"); |
| 2478 | return -EBUSY; |
| 2479 | } |
| 2480 | |
| 2481 | /* move to SW control */ |
| 2482 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN); |
| 2483 | if (rc < 0) { |
| 2484 | pr_err("Failed switch to IBB_SW_CONTROL rc=%d\n", rc); |
| 2485 | return rc; |
| 2486 | } |
| 2487 | |
| 2488 | /* delay to skip the second swire command */ |
| 2489 | dly = labibb->swire_2nd_cmd_delay * 1000; |
| 2490 | while (dly / 20000) { |
| 2491 | usleep_range(20000, 20010); |
| 2492 | dly -= 20000; |
| 2493 | } |
| 2494 | if (dly) |
| 2495 | usleep_range(dly, dly + 10); |
| 2496 | |
| 2497 | rc = qpnp_ibb_set_mode(labibb, IBB_HW_SW_CONTROL); |
| 2498 | if (rc < 0) { |
| 2499 | pr_err("Failed switch to IBB_HW_SW_CONTROL rc=%d\n", rc); |
| 2500 | return rc; |
| 2501 | } |
| 2502 | |
| 2503 | /* delay for SPMI to SWIRE transition */ |
| 2504 | usleep_range(1000, 1100); |
| 2505 | |
| 2506 | /* Move back to SWIRE control */ |
| 2507 | rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); |
| 2508 | if (rc < 0) |
| 2509 | pr_err("Failed switch to IBB_HW_CONTROL rc=%d\n", rc); |
| 2510 | |
| 2511 | /* delay before enabling the PS mode */ |
| 2512 | msleep(labibb->swire_ibb_ps_enable_delay); |
| 2513 | rc = qpnp_ibb_ps_config(labibb, true); |
| 2514 | if (rc < 0) |
| 2515 | pr_err("Unable to enable IBB PS rc=%d\n", rc); |
| 2516 | |
| 2517 | return rc; |
| 2518 | } |
| 2519 | |
| 2520 | static irqreturn_t lab_vreg_ok_handler(int irq, void *_labibb) |
| 2521 | { |
| 2522 | struct qpnp_labibb *labibb = _labibb; |
| 2523 | int rc; |
| 2524 | |
| 2525 | if (labibb->skip_2nd_swire_cmd && labibb->lab_dig_major < 2) { |
| 2526 | rc = qpnp_skip_swire_command(labibb); |
| 2527 | if (rc < 0) |
| 2528 | pr_err("Failed in 'qpnp_skip_swire_command' rc=%d\n", |
| 2529 | rc); |
| 2530 | } else if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && |
| 2531 | labibb->mode == QPNP_LABIBB_LCD_MODE) { |
| 2532 | rc = qpnp_lab_pfm_enable(labibb); |
| 2533 | if (rc < 0) |
| 2534 | pr_err("Failed to config PFM, rc=%d\n", rc); |
| 2535 | } |
| 2536 | |
| 2537 | return IRQ_HANDLED; |
| 2538 | } |
| 2539 | |
| 2540 | static int qpnp_lab_regulator_get_voltage(struct regulator_dev *rdev) |
| 2541 | { |
| 2542 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 2543 | |
| 2544 | if (labibb->swire_control) |
| 2545 | return 0; |
| 2546 | |
| 2547 | return labibb->lab_vreg.curr_volt; |
| 2548 | } |
| 2549 | |
| 2550 | static bool is_lab_vreg_ok_irq_available(struct qpnp_labibb *labibb) |
| 2551 | { |
| 2552 | /* |
| 2553 | * LAB VREG_OK interrupt is used only to skip 2nd SWIRE command in |
| 2554 | * dig_major < 2 targets. For pmi8998, it is used to enable PFM in |
| 2555 | * LCD mode. |
| 2556 | */ |
| 2557 | if (labibb->skip_2nd_swire_cmd && labibb->lab_dig_major < 2) |
| 2558 | return true; |
| 2559 | |
| 2560 | if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && |
| 2561 | labibb->mode == QPNP_LABIBB_LCD_MODE) |
| 2562 | return true; |
| 2563 | |
| 2564 | return false; |
| 2565 | } |
| 2566 | |
| 2567 | static struct regulator_ops qpnp_lab_ops = { |
| 2568 | .enable = qpnp_lab_regulator_enable, |
| 2569 | .disable = qpnp_lab_regulator_disable, |
| 2570 | .is_enabled = qpnp_lab_regulator_is_enabled, |
| 2571 | .set_voltage = qpnp_lab_regulator_set_voltage, |
| 2572 | .get_voltage = qpnp_lab_regulator_get_voltage, |
| 2573 | }; |
| 2574 | |
| 2575 | static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, |
| 2576 | struct device_node *of_node) |
| 2577 | { |
| 2578 | int rc = 0; |
| 2579 | struct regulator_init_data *init_data; |
| 2580 | struct regulator_desc *rdesc = &labibb->lab_vreg.rdesc; |
| 2581 | struct regulator_config cfg = {}; |
| 2582 | u8 val, mask; |
| 2583 | const char *current_sense_str; |
| 2584 | bool config_current_sense = false; |
| 2585 | u32 tmp; |
| 2586 | |
| 2587 | if (!of_node) { |
| 2588 | dev_err(labibb->dev, "qpnp lab regulator device tree node is missing\n"); |
| 2589 | return -EINVAL; |
| 2590 | } |
| 2591 | |
| 2592 | init_data = of_get_regulator_init_data(labibb->dev, of_node, rdesc); |
| 2593 | if (!init_data) { |
| 2594 | pr_err("unable to get regulator init data for qpnp lab regulator\n"); |
| 2595 | return -ENOMEM; |
| 2596 | } |
| 2597 | |
| 2598 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-min-voltage", |
| 2599 | &(labibb->lab_vreg.min_volt)); |
| 2600 | if (rc < 0) { |
| 2601 | pr_err("qcom,qpnp-lab-min-voltage is missing, rc = %d\n", |
| 2602 | rc); |
| 2603 | return rc; |
| 2604 | } |
| 2605 | |
| 2606 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-step-size", |
| 2607 | &(labibb->lab_vreg.step_size)); |
| 2608 | if (rc < 0) { |
| 2609 | pr_err("qcom,qpnp-lab-step-size is missing, rc = %d\n", rc); |
| 2610 | return rc; |
| 2611 | } |
| 2612 | |
| 2613 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-slew-rate", |
| 2614 | &(labibb->lab_vreg.slew_rate)); |
| 2615 | if (rc < 0) { |
| 2616 | pr_err("qcom,qpnp-lab-slew-rate is missing, rc = %d\n", |
| 2617 | rc); |
| 2618 | return rc; |
| 2619 | } |
| 2620 | |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 2621 | labibb->notify_lab_vreg_ok_sts = of_property_read_bool(of_node, |
| 2622 | "qcom,notify-lab-vreg-ok-sts"); |
| 2623 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2624 | rc = of_property_read_u32(of_node, "qcom,qpnp-lab-soft-start", |
| 2625 | &(labibb->lab_vreg.soft_start)); |
| 2626 | if (!rc) { |
| 2627 | for (val = 0; val < ARRAY_SIZE(lab_soft_start_table); val++) |
| 2628 | if (lab_soft_start_table[val] == |
| 2629 | labibb->lab_vreg.soft_start) |
| 2630 | break; |
| 2631 | |
| 2632 | if (val == ARRAY_SIZE(lab_soft_start_table)) |
| 2633 | val = ARRAY_SIZE(lab_soft_start_table) - 1; |
| 2634 | |
| 2635 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2636 | REG_LAB_SOFT_START_CTL, &val, 1); |
| 2637 | if (rc < 0) { |
| 2638 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2639 | REG_LAB_SOFT_START_CTL, rc); |
| 2640 | return rc; |
| 2641 | } |
| 2642 | |
| 2643 | labibb->lab_vreg.soft_start = lab_soft_start_table |
| 2644 | [val & LAB_SOFT_START_CTL_MASK]; |
| 2645 | } |
| 2646 | |
| 2647 | val = 0; |
| 2648 | mask = 0; |
| 2649 | rc = of_property_read_u32(of_node, |
| 2650 | "qcom,qpnp-lab-max-precharge-time", &tmp); |
| 2651 | if (!rc) { |
| 2652 | for (val = 0; val < ARRAY_SIZE(lab_max_precharge_table); val++) |
| 2653 | if (lab_max_precharge_table[val] == tmp) |
| 2654 | break; |
| 2655 | |
| 2656 | if (val == ARRAY_SIZE(lab_max_precharge_table)) { |
| 2657 | pr_err("Invalid value in qcom,qpnp-lab-max-precharge-time\n"); |
| 2658 | return -EINVAL; |
| 2659 | } |
| 2660 | |
| 2661 | mask = LAB_MAX_PRECHARGE_TIME_MASK; |
| 2662 | } |
| 2663 | |
| 2664 | if (of_property_read_bool(of_node, |
| 2665 | "qcom,qpnp-lab-max-precharge-enable")) { |
| 2666 | val |= LAB_FAST_PRECHARGE_CTL_EN; |
| 2667 | mask |= LAB_FAST_PRECHARGE_CTL_EN; |
| 2668 | } |
| 2669 | |
| 2670 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 2671 | REG_LAB_PRECHARGE_CTL, mask, val); |
| 2672 | if (rc < 0) { |
| 2673 | pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", |
| 2674 | REG_LAB_PRECHARGE_CTL, rc); |
| 2675 | return rc; |
| 2676 | } |
| 2677 | |
| 2678 | if (labibb->mode == QPNP_LABIBB_AMOLED_MODE && |
| 2679 | labibb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) { |
| 2680 | /* |
| 2681 | * default to 1.5 times current gain if |
| 2682 | * user doesn't specify the current-sense |
| 2683 | * dt parameter |
| 2684 | */ |
| 2685 | current_sense_str = "1.5x"; |
| 2686 | val = qpnp_labibb_get_matching_idx(current_sense_str); |
| 2687 | config_current_sense = true; |
| 2688 | } |
| 2689 | |
| 2690 | if (of_find_property(of_node, |
| 2691 | "qcom,qpnp-lab-current-sense", NULL)) { |
| 2692 | config_current_sense = true; |
| 2693 | rc = of_property_read_string(of_node, |
| 2694 | "qcom,qpnp-lab-current-sense", |
| 2695 | ¤t_sense_str); |
| 2696 | if (!rc) { |
| 2697 | val = qpnp_labibb_get_matching_idx( |
| 2698 | current_sense_str); |
| 2699 | } else { |
| 2700 | pr_err("qcom,qpnp-lab-current-sense configured incorrectly rc = %d\n", |
| 2701 | rc); |
| 2702 | return rc; |
| 2703 | } |
| 2704 | } |
| 2705 | |
| 2706 | if (config_current_sense) { |
| 2707 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 2708 | REG_LAB_CURRENT_SENSE, |
| 2709 | LAB_CURRENT_SENSE_GAIN_MASK, |
| 2710 | val); |
| 2711 | if (rc < 0) { |
| 2712 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2713 | REG_LAB_CURRENT_SENSE, rc); |
| 2714 | return rc; |
| 2715 | } |
| 2716 | } |
| 2717 | |
| 2718 | val = (labibb->standalone) ? 0 : LAB_IBB_EN_RDY_EN; |
| 2719 | rc = qpnp_labibb_sec_write(labibb, labibb->lab_base, |
| 2720 | REG_LAB_IBB_EN_RDY, val); |
| 2721 | |
| 2722 | if (rc < 0) { |
| 2723 | pr_err("qpnp_lab_sec_write register %x failed rc = %d\n", |
| 2724 | REG_LAB_IBB_EN_RDY, rc); |
| 2725 | return rc; |
| 2726 | } |
| 2727 | |
| 2728 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL, |
| 2729 | &val, 1); |
| 2730 | if (rc < 0) { |
| 2731 | pr_err("qpnp_labibb_read register %x failed rc = %d\n", |
| 2732 | REG_IBB_ENABLE_CTL, rc); |
| 2733 | return rc; |
| 2734 | } |
| 2735 | |
| 2736 | if (!(val & (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN))) { |
| 2737 | /* SWIRE_RDY and IBB_MODULE_EN not enabled */ |
| 2738 | rc = qpnp_lab_dt_init(labibb, of_node); |
| 2739 | if (rc < 0) { |
| 2740 | pr_err("qpnp-lab: wrong DT parameter specified: rc = %d\n", |
| 2741 | rc); |
| 2742 | return rc; |
| 2743 | } |
| 2744 | } else { |
| 2745 | rc = labibb->ibb_ver_ops->get_mode(labibb); |
| 2746 | |
| 2747 | rc = qpnp_labibb_read(labibb, labibb->lab_base + |
| 2748 | REG_LAB_VOLTAGE, &val, 1); |
| 2749 | if (rc < 0) { |
| 2750 | pr_err("qpnp_lab_read read register %x failed rc = %d\n", |
| 2751 | REG_LAB_VOLTAGE, rc); |
| 2752 | return rc; |
| 2753 | } |
| 2754 | |
| 2755 | labibb->lab_vreg.curr_volt = |
| 2756 | (val & |
| 2757 | LAB_VOLTAGE_SET_MASK) * |
| 2758 | labibb->lab_vreg.step_size + |
| 2759 | labibb->lab_vreg.min_volt; |
| 2760 | if (labibb->mode == QPNP_LABIBB_LCD_MODE) { |
| 2761 | rc = of_property_read_u32(of_node, |
| 2762 | "qcom,qpnp-lab-init-lcd-voltage", |
| 2763 | &(labibb->lab_vreg.curr_volt)); |
| 2764 | if (rc < 0) { |
| 2765 | pr_err("get qcom,qpnp-lab-init-lcd-voltage failed, rc = %d\n", |
| 2766 | rc); |
| 2767 | return rc; |
| 2768 | } |
| 2769 | } else if (!(val & LAB_VOLTAGE_OVERRIDE_EN)) { |
| 2770 | rc = of_property_read_u32(of_node, |
| 2771 | "qcom,qpnp-lab-init-amoled-voltage", |
| 2772 | &(labibb->lab_vreg.curr_volt)); |
| 2773 | if (rc < 0) { |
| 2774 | pr_err("get qcom,qpnp-lab-init-amoled-voltage failed, rc = %d\n", |
| 2775 | rc); |
| 2776 | return rc; |
| 2777 | } |
| 2778 | } |
| 2779 | |
| 2780 | labibb->lab_vreg.vreg_enabled = 1; |
| 2781 | } |
| 2782 | |
| 2783 | if (is_lab_vreg_ok_irq_available(labibb)) { |
| 2784 | rc = devm_request_threaded_irq(labibb->dev, |
| 2785 | labibb->lab_vreg.lab_vreg_ok_irq, NULL, |
| 2786 | lab_vreg_ok_handler, |
| 2787 | IRQF_ONESHOT | IRQF_TRIGGER_RISING, |
| 2788 | "lab-vreg-ok", labibb); |
| 2789 | if (rc) { |
| 2790 | pr_err("Failed to register 'lab-vreg-ok' irq rc=%d\n", |
| 2791 | rc); |
| 2792 | return rc; |
| 2793 | } |
| 2794 | } |
| 2795 | |
| 2796 | rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_MODULE_RDY, |
| 2797 | &val, 1); |
| 2798 | if (rc < 0) { |
| 2799 | pr_err("qpnp_lab_read read register %x failed rc = %d\n", |
| 2800 | REG_LAB_MODULE_RDY, rc); |
| 2801 | return rc; |
| 2802 | } |
| 2803 | |
| 2804 | if (!(val & LAB_MODULE_RDY_EN)) { |
| 2805 | val = LAB_MODULE_RDY_EN; |
| 2806 | |
| 2807 | rc = qpnp_labibb_write(labibb, labibb->lab_base + |
| 2808 | REG_LAB_MODULE_RDY, &val, 1); |
| 2809 | |
| 2810 | if (rc < 0) { |
| 2811 | pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", |
| 2812 | REG_LAB_MODULE_RDY, rc); |
| 2813 | return rc; |
| 2814 | } |
| 2815 | } |
| 2816 | |
| 2817 | if (init_data->constraints.name) { |
| 2818 | rdesc->owner = THIS_MODULE; |
| 2819 | rdesc->type = REGULATOR_VOLTAGE; |
| 2820 | rdesc->ops = &qpnp_lab_ops; |
| 2821 | rdesc->name = init_data->constraints.name; |
| 2822 | |
| 2823 | cfg.dev = labibb->dev; |
| 2824 | cfg.init_data = init_data; |
| 2825 | cfg.driver_data = labibb; |
| 2826 | cfg.of_node = of_node; |
| 2827 | |
| 2828 | if (of_get_property(labibb->dev->of_node, "parent-supply", |
| 2829 | NULL)) |
| 2830 | init_data->supply_regulator = "parent"; |
| 2831 | |
| 2832 | init_data->constraints.valid_ops_mask |
| 2833 | |= REGULATOR_CHANGE_VOLTAGE | |
| 2834 | REGULATOR_CHANGE_STATUS; |
| 2835 | |
| 2836 | labibb->lab_vreg.rdev = regulator_register(rdesc, &cfg); |
| 2837 | if (IS_ERR(labibb->lab_vreg.rdev)) { |
| 2838 | rc = PTR_ERR(labibb->lab_vreg.rdev); |
| 2839 | labibb->lab_vreg.rdev = NULL; |
| 2840 | pr_err("unable to get regulator init data for qpnp lab regulator, rc = %d\n", |
| 2841 | rc); |
| 2842 | |
| 2843 | return rc; |
| 2844 | } |
| 2845 | } else { |
| 2846 | dev_err(labibb->dev, "qpnp lab regulator name missing\n"); |
| 2847 | return -EINVAL; |
| 2848 | } |
| 2849 | |
| 2850 | return 0; |
| 2851 | } |
| 2852 | |
| 2853 | static int qpnp_ibb_pfm_mode_enable(struct qpnp_labibb *labibb, |
| 2854 | struct device_node *of_node) |
| 2855 | { |
| 2856 | int rc = 0; |
| 2857 | u32 i, tmp = 0; |
| 2858 | u8 val = IBB_PFM_ENABLE; |
| 2859 | |
| 2860 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-peak-curr", |
| 2861 | &tmp); |
| 2862 | if (rc < 0) { |
| 2863 | pr_err("qcom,qpnp-ibb-pfm-peak-curr is missing, rc = %d\n", |
| 2864 | rc); |
| 2865 | return rc; |
| 2866 | } |
| 2867 | for (i = 0; i < ARRAY_SIZE(ibb_pfm_peak_curr_table); i++) |
| 2868 | if (ibb_pfm_peak_curr_table[i] == tmp) |
| 2869 | break; |
| 2870 | |
| 2871 | if (i == ARRAY_SIZE(ibb_pfm_peak_curr_table)) { |
| 2872 | pr_err("Invalid value in qcom,qpnp-ibb-pfm-peak-curr\n"); |
| 2873 | return -EINVAL; |
| 2874 | } |
| 2875 | |
| 2876 | val |= (i << IBB_PFM_PEAK_CURRENT_BIT_SHIFT); |
| 2877 | |
| 2878 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-hysteresis", |
| 2879 | &tmp); |
| 2880 | if (rc < 0) { |
| 2881 | pr_err("qcom,qpnp-ibb-pfm-hysteresis is missing, rc = %d\n", |
| 2882 | rc); |
| 2883 | return rc; |
| 2884 | } |
| 2885 | |
| 2886 | for (i = 0; i < ARRAY_SIZE(ibb_pfm_hysteresis_table); i++) |
| 2887 | if (ibb_pfm_hysteresis_table[i] == tmp) |
| 2888 | break; |
| 2889 | |
| 2890 | if (i == ARRAY_SIZE(ibb_pfm_hysteresis_table)) { |
| 2891 | pr_err("Invalid value in qcom,qpnp-ibb-pfm-hysteresis\n"); |
| 2892 | return -EINVAL; |
| 2893 | } |
| 2894 | |
| 2895 | val |= (i << IBB_PFM_HYSTERESIS_BIT_SHIFT); |
| 2896 | |
| 2897 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 2898 | REG_IBB_PFM_CTL, &val, 1); |
| 2899 | if (rc < 0) |
| 2900 | pr_err("qpnp_ibb_pfm_ctl write register %x failed rc = %d\n", |
| 2901 | REG_IBB_PFM_CTL, rc); |
| 2902 | |
| 2903 | return rc; |
| 2904 | } |
| 2905 | |
| 2906 | static int qpnp_labibb_pbs_mode_enable(struct qpnp_labibb *labibb, |
| 2907 | struct device_node *of_node) |
| 2908 | { |
| 2909 | int rc = 0; |
| 2910 | |
| 2911 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 2912 | REG_IBB_SWIRE_CTL, |
| 2913 | IBB_SWIRE_VOUT_UPD_EN, 0); |
| 2914 | if (rc < 0) { |
| 2915 | pr_err("qpnp_ibb_swire_ctl write register %x failed rc = %d\n", |
| 2916 | REG_IBB_SWIRE_CTL, rc); |
| 2917 | return rc; |
| 2918 | } |
| 2919 | |
| 2920 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 2921 | REG_IBB_PD_CTL, IBB_SWIRE_PD_UPD, 0); |
| 2922 | if (rc < 0) { |
| 2923 | pr_err("qpnp_ibb_pd_ctl write register %x failed rc = %d\n", |
| 2924 | REG_IBB_PD_CTL, rc); |
| 2925 | return rc; |
| 2926 | } |
| 2927 | |
| 2928 | rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + |
| 2929 | REG_LAB_SWIRE_PGM_CTL, LAB_EN_SWIRE_PGM_VOUT | |
| 2930 | LAB_EN_SWIRE_PGM_PD, 0); |
| 2931 | if (rc < 0) |
| 2932 | pr_err("qpnp_lab_swire_pgm_ctl write register %x failed rc = %d\n", |
| 2933 | REG_LAB_SWIRE_PGM_CTL, rc); |
| 2934 | |
| 2935 | return rc; |
| 2936 | } |
| 2937 | |
| 2938 | static int qpnp_ibb_slew_rate_config(struct qpnp_labibb *labibb, |
| 2939 | struct device_node *of_node) |
| 2940 | { |
| 2941 | int rc = 0; |
| 2942 | u32 i, tmp = 0; |
| 2943 | u8 val = 0, mask = 0; |
| 2944 | |
| 2945 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-fast-slew-rate", |
| 2946 | &tmp); |
| 2947 | if (!rc) { |
| 2948 | for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++) |
| 2949 | if (ibb_output_slew_ctl_table[i] == tmp) |
| 2950 | break; |
| 2951 | |
| 2952 | if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) { |
| 2953 | pr_err("Invalid value in qcom,qpnp-ibb-fast-slew-rate\n"); |
| 2954 | return -EINVAL; |
| 2955 | } |
| 2956 | |
| 2957 | labibb->ibb_vreg.slew_rate = tmp; |
| 2958 | val |= (i << IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT) | |
| 2959 | IBB_SLEW_RATE_SPEED_FAST_EN | IBB_SLEW_CTL_EN; |
| 2960 | |
| 2961 | mask = IBB_SLEW_RATE_SPEED_FAST_EN | |
| 2962 | IBB_SLEW_RATE_TRANS_TIME_FAST_MASK | IBB_SLEW_CTL_EN; |
| 2963 | } |
| 2964 | |
| 2965 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slow-slew-rate", |
| 2966 | &tmp); |
| 2967 | if (!rc) { |
| 2968 | for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++) |
| 2969 | if (ibb_output_slew_ctl_table[i] == tmp) |
| 2970 | break; |
| 2971 | |
| 2972 | if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) { |
| 2973 | pr_err("Invalid value in qcom,qpnp-ibb-slow-slew-rate\n"); |
| 2974 | return -EINVAL; |
| 2975 | } |
| 2976 | |
| 2977 | labibb->ibb_vreg.slew_rate = tmp; |
| 2978 | val |= (i | IBB_SLEW_CTL_EN); |
| 2979 | |
| 2980 | mask |= IBB_SLEW_RATE_SPEED_FAST_EN | |
| 2981 | IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK | IBB_SLEW_CTL_EN; |
| 2982 | } |
| 2983 | |
| 2984 | rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + |
| 2985 | REG_IBB_OUTPUT_SLEW_CTL, |
| 2986 | mask, val); |
| 2987 | if (rc < 0) |
| 2988 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 2989 | REG_IBB_OUTPUT_SLEW_CTL, rc); |
| 2990 | |
| 2991 | return rc; |
| 2992 | } |
| 2993 | |
| 2994 | static bool qpnp_ibb_poff_ctl_required(struct qpnp_labibb *labibb) |
| 2995 | { |
| 2996 | if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) |
| 2997 | return false; |
| 2998 | |
| 2999 | return true; |
| 3000 | } |
| 3001 | |
| 3002 | static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, |
| 3003 | struct device_node *of_node) |
| 3004 | { |
| 3005 | int rc = 0; |
| 3006 | u32 i, tmp = 0; |
| 3007 | u8 val, mask; |
| 3008 | |
| 3009 | /* |
| 3010 | * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by |
| 3011 | * GPIO selector. Override the labibb->mode with what was configured |
| 3012 | * by the bootloader. |
| 3013 | */ |
| 3014 | if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { |
| 3015 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 3016 | REG_IBB_LCD_AMOLED_SEL, &val, 1); |
| 3017 | if (rc) { |
| 3018 | pr_err("qpnp_labibb_read register %x failed rc = %d\n", |
| 3019 | REG_IBB_LCD_AMOLED_SEL, rc); |
| 3020 | return rc; |
| 3021 | } |
| 3022 | if (val == REG_LAB_IBB_AMOLED_MODE) |
| 3023 | labibb->mode = QPNP_LABIBB_AMOLED_MODE; |
| 3024 | else |
| 3025 | labibb->mode = QPNP_LABIBB_LCD_MODE; |
| 3026 | } else { |
| 3027 | rc = labibb->ibb_ver_ops->sel_mode(labibb, 1); |
| 3028 | if (rc < 0) { |
| 3029 | pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", |
| 3030 | REG_IBB_LCD_AMOLED_SEL, rc); |
| 3031 | return rc; |
| 3032 | } |
| 3033 | } |
| 3034 | |
| 3035 | val = 0; |
| 3036 | mask = 0; |
| 3037 | rc = of_property_read_u32(of_node, |
| 3038 | "qcom,qpnp-ibb-lab-pwrdn-delay", &tmp); |
| 3039 | if (!rc) { |
| 3040 | for (val = 0; val < ARRAY_SIZE(ibb_pwrdn_dly_table); val++) |
| 3041 | if (ibb_pwrdn_dly_table[val] == tmp) |
| 3042 | break; |
| 3043 | |
| 3044 | if (val == ARRAY_SIZE(ibb_pwrdn_dly_table)) { |
| 3045 | pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrdn-delay\n"); |
| 3046 | return -EINVAL; |
| 3047 | } |
| 3048 | |
| 3049 | labibb->ibb_vreg.pwrdn_dly = tmp; |
| 3050 | val |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2; |
| 3051 | mask |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2; |
| 3052 | } |
| 3053 | |
| 3054 | rc = of_property_read_u32(of_node, |
| 3055 | "qcom,qpnp-ibb-lab-pwrup-delay", &tmp); |
| 3056 | if (!rc) { |
| 3057 | for (i = 0; i < ARRAY_SIZE(ibb_pwrup_dly_table); i++) |
| 3058 | if (ibb_pwrup_dly_table[i] == tmp) |
| 3059 | break; |
| 3060 | |
| 3061 | if (i == ARRAY_SIZE(ibb_pwrup_dly_table)) { |
| 3062 | pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrup-delay\n"); |
| 3063 | return -EINVAL; |
| 3064 | } |
| 3065 | |
| 3066 | labibb->ibb_vreg.pwrup_dly = tmp; |
| 3067 | |
| 3068 | val |= (i << IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT); |
| 3069 | val |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 | |
| 3070 | IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK); |
| 3071 | mask |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 | |
| 3072 | IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK | |
| 3073 | IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK); |
| 3074 | } |
| 3075 | |
| 3076 | if (of_property_read_bool(of_node, |
| 3077 | "qcom,qpnp-ibb-en-discharge")) { |
| 3078 | val |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN; |
| 3079 | mask |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN; |
| 3080 | } |
| 3081 | |
| 3082 | rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, |
| 3083 | REG_IBB_PWRUP_PWRDN_CTL_1, mask, val); |
| 3084 | if (rc < 0) { |
| 3085 | pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", |
| 3086 | REG_IBB_PWRUP_PWRDN_CTL_1, rc); |
| 3087 | return rc; |
| 3088 | } |
| 3089 | |
| 3090 | if (of_property_read_bool(of_node, "qcom,qpnp-ibb-slew-rate-config")) { |
| 3091 | |
| 3092 | rc = qpnp_ibb_slew_rate_config(labibb, of_node); |
| 3093 | if (rc < 0) |
| 3094 | return rc; |
| 3095 | } |
| 3096 | |
| 3097 | val = 0; |
| 3098 | if (!of_property_read_bool(of_node, "qcom,qpnp-ibb-full-pull-down")) |
| 3099 | val = IBB_PD_CTL_HALF_STRENGTH; |
| 3100 | |
| 3101 | if (of_property_read_bool(of_node, "qcom,qpnp-ibb-pull-down-enable")) |
| 3102 | val |= IBB_PD_CTL_EN; |
| 3103 | |
| 3104 | mask = IBB_PD_CTL_STRENGTH_MASK | IBB_PD_CTL_EN; |
| 3105 | rc = qpnp_labibb_masked_write(labibb, |
| 3106 | labibb->ibb_base + REG_IBB_PD_CTL, mask, val); |
| 3107 | |
| 3108 | if (rc < 0) { |
| 3109 | pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", |
| 3110 | REG_IBB_PD_CTL, rc); |
| 3111 | return rc; |
| 3112 | } |
| 3113 | |
| 3114 | rc = of_property_read_u32(of_node, |
| 3115 | "qcom,qpnp-ibb-switching-clock-frequency", &tmp); |
| 3116 | if (!rc) { |
| 3117 | for (val = 0; val < ARRAY_SIZE(ibb_clk_div_table); val++) |
| 3118 | if (ibb_clk_div_table[val] == tmp) |
| 3119 | break; |
| 3120 | |
| 3121 | if (val == ARRAY_SIZE(ibb_clk_div_table)) { |
| 3122 | pr_err("Invalid value in qpnp-ibb-switching-clock-frequency\n"); |
| 3123 | return -EINVAL; |
| 3124 | } |
| 3125 | rc = labibb->ibb_ver_ops->set_clk_div(labibb, val); |
| 3126 | if (rc < 0) { |
| 3127 | pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", |
| 3128 | REG_IBB_CLK_DIV, rc); |
| 3129 | return rc; |
| 3130 | } |
| 3131 | } |
| 3132 | |
| 3133 | val = 0; |
| 3134 | mask = 0; |
| 3135 | rc = of_property_read_u32(of_node, |
| 3136 | "qcom,qpnp-ibb-limit-maximum-current", &tmp); |
| 3137 | if (!rc) { |
| 3138 | for (val = 0; val < ARRAY_SIZE(ibb_current_limit_table); val++) |
| 3139 | if (ibb_current_limit_table[val] == tmp) |
| 3140 | break; |
| 3141 | |
| 3142 | if (val == ARRAY_SIZE(ibb_current_limit_table)) { |
| 3143 | pr_err("Invalid value in qcom,qpnp-ibb-limit-maximum-current\n"); |
| 3144 | return -EINVAL; |
| 3145 | } |
| 3146 | |
| 3147 | mask = IBB_CURRENT_LIMIT_MASK; |
| 3148 | } |
| 3149 | |
| 3150 | rc = of_property_read_u32(of_node, |
| 3151 | "qcom,qpnp-ibb-debounce-cycle", &tmp); |
| 3152 | if (!rc) { |
| 3153 | for (i = 0; i < ARRAY_SIZE(ibb_debounce_table); i++) |
| 3154 | if (ibb_debounce_table[i] == tmp) |
| 3155 | break; |
| 3156 | |
| 3157 | if (i == ARRAY_SIZE(ibb_debounce_table)) { |
| 3158 | pr_err("Invalid value in qcom,qpnp-ibb-debounce-cycle\n"); |
| 3159 | return -EINVAL; |
| 3160 | } |
| 3161 | |
| 3162 | val |= (i << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT); |
| 3163 | mask |= IBB_CURRENT_LIMIT_DEBOUNCE_MASK; |
| 3164 | } |
| 3165 | |
| 3166 | if (of_property_read_bool(of_node, |
| 3167 | "qcom,qpnp-ibb-limit-max-current-enable")) { |
| 3168 | val |= IBB_CURRENT_LIMIT_EN; |
| 3169 | mask |= IBB_CURRENT_LIMIT_EN; |
| 3170 | } |
| 3171 | |
| 3172 | rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, |
| 3173 | REG_IBB_CURRENT_LIMIT, mask, val); |
| 3174 | if (rc < 0) { |
| 3175 | pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", |
| 3176 | REG_IBB_CURRENT_LIMIT, rc); |
| 3177 | return rc; |
| 3178 | } |
| 3179 | |
| 3180 | if (of_property_read_bool(of_node, |
| 3181 | "qcom,qpnp-ibb-ring-suppression-enable")) { |
| 3182 | val = IBB_RING_SUPPRESSION_CTL_EN; |
| 3183 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 3184 | REG_IBB_RING_SUPPRESSION_CTL, |
| 3185 | &val, |
| 3186 | 1); |
| 3187 | if (rc < 0) { |
| 3188 | pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", |
| 3189 | REG_IBB_RING_SUPPRESSION_CTL, rc); |
| 3190 | return rc; |
| 3191 | } |
| 3192 | } |
| 3193 | |
| 3194 | if (of_property_read_bool(of_node, "qcom,qpnp-ibb-ps-enable")) { |
| 3195 | rc = qpnp_ibb_ps_config(labibb, true); |
| 3196 | if (rc < 0) { |
| 3197 | pr_err("qpnp_ibb_dt_init PS enable failed rc=%d\n", rc); |
| 3198 | return rc; |
| 3199 | } |
| 3200 | } else { |
| 3201 | rc = qpnp_ibb_ps_config(labibb, false); |
| 3202 | if (rc < 0) { |
| 3203 | pr_err("qpnp_ibb_dt_init PS disable failed rc=%d\n", |
| 3204 | rc); |
| 3205 | return rc; |
| 3206 | } |
| 3207 | } |
| 3208 | |
| 3209 | if (of_property_read_bool(of_node, |
| 3210 | "qcom,qpnp-ibb-smart-ps-enable")){ |
| 3211 | of_property_read_u32(of_node, "qcom,qpnp-ibb-num-swire-trans", |
| 3212 | &labibb->ibb_vreg.num_swire_trans); |
| 3213 | |
| 3214 | of_property_read_u32(of_node, |
| 3215 | "qcom,qpnp-ibb-neg-curr-limit", &tmp); |
| 3216 | |
| 3217 | rc = labibb->ibb_ver_ops->smart_ps_config(labibb, true, |
| 3218 | labibb->ibb_vreg.num_swire_trans, tmp); |
| 3219 | if (rc < 0) { |
| 3220 | pr_err("qpnp_ibb_dt_init smart PS enable failed rc=%d\n", |
| 3221 | rc); |
| 3222 | return rc; |
| 3223 | } |
| 3224 | |
| 3225 | } |
| 3226 | |
| 3227 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-init-voltage", |
| 3228 | &(labibb->ibb_vreg.curr_volt)); |
| 3229 | if (rc < 0) { |
| 3230 | pr_err("get qcom,qpnp-ibb-init-voltage failed, rc = %d\n", rc); |
| 3231 | return rc; |
| 3232 | } |
| 3233 | |
| 3234 | if (of_property_read_bool(of_node, |
| 3235 | "qcom,qpnp-ibb-use-default-voltage")) |
| 3236 | rc = labibb->ibb_ver_ops->set_default_voltage(labibb, true); |
| 3237 | else |
| 3238 | rc = labibb->ibb_ver_ops->set_default_voltage(labibb, false); |
| 3239 | |
| 3240 | if (rc < 0) |
| 3241 | return rc; |
| 3242 | |
| 3243 | if (of_property_read_bool(of_node, "qcom,qpnp-ibb-overload-blank")) { |
| 3244 | rc = qpnp_ibb_vreg_ok_ctl(labibb, of_node); |
| 3245 | if (rc < 0) |
| 3246 | return rc; |
| 3247 | } |
| 3248 | |
| 3249 | return 0; |
| 3250 | } |
| 3251 | |
| 3252 | static int qpnp_ibb_regulator_enable(struct regulator_dev *rdev) |
| 3253 | { |
| 3254 | int rc, delay, retries = 10; |
| 3255 | u8 val; |
| 3256 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 3257 | |
| 3258 | if (!labibb->ibb_vreg.vreg_enabled && !labibb->swire_control) { |
| 3259 | |
| 3260 | if (!labibb->standalone) |
| 3261 | return qpnp_labibb_regulator_enable(labibb); |
| 3262 | |
| 3263 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN); |
| 3264 | if (rc < 0) { |
| 3265 | pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); |
| 3266 | return rc; |
| 3267 | } |
| 3268 | |
| 3269 | delay = labibb->ibb_vreg.soft_start; |
| 3270 | while (retries--) { |
| 3271 | /* Wait for a small period before reading IBB_STATUS1 */ |
| 3272 | usleep_range(delay, delay + 100); |
| 3273 | |
| 3274 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 3275 | REG_IBB_STATUS1, &val, 1); |
| 3276 | if (rc < 0) { |
| 3277 | pr_err("qpnp_ibb_regulator_enable read register %x failed rc = %d\n", |
| 3278 | REG_IBB_STATUS1, rc); |
| 3279 | return rc; |
| 3280 | } |
| 3281 | |
| 3282 | if (val & IBB_STATUS1_VREG_OK) |
| 3283 | break; |
| 3284 | } |
| 3285 | |
| 3286 | if (!(val & IBB_STATUS1_VREG_OK)) { |
| 3287 | pr_err("qpnp_ibb_regulator_enable failed\n"); |
| 3288 | return -EINVAL; |
| 3289 | } |
| 3290 | |
| 3291 | labibb->ibb_vreg.vreg_enabled = 1; |
| 3292 | } |
| 3293 | return 0; |
| 3294 | } |
| 3295 | |
| 3296 | static int qpnp_ibb_regulator_disable(struct regulator_dev *rdev) |
| 3297 | { |
| 3298 | int rc; |
| 3299 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 3300 | |
| 3301 | if (labibb->ibb_vreg.vreg_enabled && !labibb->swire_control) { |
| 3302 | |
| 3303 | if (!labibb->standalone) |
| 3304 | return qpnp_labibb_regulator_disable(labibb); |
| 3305 | |
| 3306 | rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); |
| 3307 | if (rc < 0) { |
| 3308 | pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); |
| 3309 | return rc; |
| 3310 | } |
| 3311 | |
| 3312 | labibb->ibb_vreg.vreg_enabled = 0; |
| 3313 | } |
| 3314 | return 0; |
| 3315 | } |
| 3316 | |
| 3317 | static int qpnp_ibb_regulator_is_enabled(struct regulator_dev *rdev) |
| 3318 | { |
| 3319 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 3320 | |
| 3321 | if (labibb->swire_control) |
| 3322 | return 0; |
| 3323 | |
| 3324 | return labibb->ibb_vreg.vreg_enabled; |
| 3325 | } |
| 3326 | |
| 3327 | static int qpnp_ibb_regulator_set_voltage(struct regulator_dev *rdev, |
| 3328 | int min_uV, int max_uV, unsigned int *selector) |
| 3329 | { |
| 3330 | int rc = 0; |
| 3331 | |
| 3332 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 3333 | |
| 3334 | if (labibb->swire_control) |
| 3335 | return 0; |
| 3336 | |
| 3337 | rc = labibb->ibb_ver_ops->set_voltage(labibb, min_uV, max_uV); |
| 3338 | return rc; |
| 3339 | } |
| 3340 | |
| 3341 | |
| 3342 | static int qpnp_ibb_regulator_get_voltage(struct regulator_dev *rdev) |
| 3343 | { |
| 3344 | struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); |
| 3345 | |
| 3346 | if (labibb->swire_control) |
| 3347 | return 0; |
| 3348 | |
| 3349 | return labibb->ibb_vreg.curr_volt; |
| 3350 | } |
| 3351 | |
| 3352 | static struct regulator_ops qpnp_ibb_ops = { |
| 3353 | .enable = qpnp_ibb_regulator_enable, |
| 3354 | .disable = qpnp_ibb_regulator_disable, |
| 3355 | .is_enabled = qpnp_ibb_regulator_is_enabled, |
| 3356 | .set_voltage = qpnp_ibb_regulator_set_voltage, |
| 3357 | .get_voltage = qpnp_ibb_regulator_get_voltage, |
| 3358 | }; |
| 3359 | |
| 3360 | static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, |
| 3361 | struct device_node *of_node) |
| 3362 | { |
| 3363 | int rc = 0; |
| 3364 | struct regulator_init_data *init_data; |
| 3365 | struct regulator_desc *rdesc = &labibb->ibb_vreg.rdesc; |
| 3366 | struct regulator_config cfg = {}; |
| 3367 | u8 val, ibb_enable_ctl, index; |
| 3368 | u32 tmp; |
| 3369 | |
| 3370 | if (!of_node) { |
| 3371 | dev_err(labibb->dev, "qpnp ibb regulator device tree node is missing\n"); |
| 3372 | return -EINVAL; |
| 3373 | } |
| 3374 | |
| 3375 | init_data = of_get_regulator_init_data(labibb->dev, of_node, rdesc); |
| 3376 | if (!init_data) { |
| 3377 | pr_err("unable to get regulator init data for qpnp ibb regulator\n"); |
| 3378 | return -ENOMEM; |
| 3379 | } |
| 3380 | |
| 3381 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-min-voltage", |
| 3382 | &(labibb->ibb_vreg.min_volt)); |
| 3383 | if (rc < 0) { |
| 3384 | pr_err("qcom,qpnp-ibb-min-voltage is missing, rc = %d\n", |
| 3385 | rc); |
| 3386 | return rc; |
| 3387 | } |
| 3388 | |
| 3389 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-step-size", |
| 3390 | &(labibb->ibb_vreg.step_size)); |
| 3391 | if (rc < 0) { |
| 3392 | pr_err("qcom,qpnp-ibb-step-size is missing, rc = %d\n", rc); |
| 3393 | return rc; |
| 3394 | } |
| 3395 | |
| 3396 | rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slew-rate", |
| 3397 | &(labibb->ibb_vreg.slew_rate)); |
| 3398 | if (rc < 0) |
| 3399 | labibb->ibb_vreg.slew_rate = IBB_HW_DEFAULT_SLEW_RATE; |
| 3400 | |
| 3401 | rc = labibb->ibb_ver_ops->soft_start_ctl(labibb, of_node); |
| 3402 | if (rc < 0) { |
| 3403 | pr_err("qpnp_labibb_write register %x failed rc = %d\n", |
| 3404 | REG_IBB_SOFT_START_CTL, rc); |
| 3405 | return rc; |
| 3406 | } |
| 3407 | |
| 3408 | if (of_find_property(of_node, "qcom,output-voltage-one-pulse", NULL)) { |
| 3409 | if (!labibb->swire_control) { |
| 3410 | pr_err("output-voltage-one-pulse valid for SWIRE only\n"); |
| 3411 | return -EINVAL; |
| 3412 | } |
| 3413 | rc = of_property_read_u32(of_node, |
| 3414 | "qcom,output-voltage-one-pulse", &tmp); |
| 3415 | if (rc < 0) { |
| 3416 | pr_err("failed to read qcom,output-voltage-one-pulse rc=%d\n", |
| 3417 | rc); |
| 3418 | return rc; |
| 3419 | } |
| 3420 | if (tmp > MAX_OUTPUT_PULSE_VOLTAGE_MV || |
| 3421 | tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) { |
| 3422 | pr_err("Invalid one-pulse voltage range %d\n", tmp); |
| 3423 | return -EINVAL; |
| 3424 | } |
| 3425 | rc = labibb->ibb_ver_ops->voltage_at_one_pulse(labibb, tmp); |
| 3426 | if (rc < 0) |
| 3427 | return rc; |
| 3428 | } |
| 3429 | |
| 3430 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL, |
| 3431 | &ibb_enable_ctl, 1); |
| 3432 | if (rc < 0) { |
| 3433 | pr_err("qpnp_ibb_read register %x failed rc = %d\n", |
| 3434 | REG_IBB_ENABLE_CTL, rc); |
| 3435 | return rc; |
| 3436 | } |
| 3437 | |
| 3438 | /* |
| 3439 | * For pmi8998, override swire_control with what was configured |
| 3440 | * before by the bootloader. |
| 3441 | */ |
| 3442 | if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) |
| 3443 | labibb->swire_control = ibb_enable_ctl & |
| 3444 | IBB_ENABLE_CTL_SWIRE_RDY; |
| 3445 | |
| 3446 | if (ibb_enable_ctl & |
| 3447 | (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN)) { |
| 3448 | |
| 3449 | rc = labibb->ibb_ver_ops->get_mode(labibb); |
| 3450 | if (rc < 0) { |
| 3451 | pr_err("qpnp_labibb_read register %x failed rc = %d\n", |
| 3452 | REG_IBB_LCD_AMOLED_SEL, rc); |
| 3453 | return rc; |
| 3454 | } |
| 3455 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 3456 | REG_IBB_VOLTAGE, &val, 1); |
| 3457 | if (rc < 0) { |
| 3458 | pr_err("qpnp_labibb_read read register %x failed rc = %d\n", |
| 3459 | REG_IBB_VOLTAGE, rc); |
| 3460 | return rc; |
| 3461 | } |
| 3462 | |
| 3463 | labibb->ibb_vreg.curr_volt = |
| 3464 | (val & IBB_VOLTAGE_SET_MASK) * |
| 3465 | labibb->ibb_vreg.step_size + |
| 3466 | labibb->ibb_vreg.min_volt; |
| 3467 | |
| 3468 | if (labibb->mode == QPNP_LABIBB_LCD_MODE) { |
| 3469 | rc = of_property_read_u32(of_node, |
| 3470 | "qcom,qpnp-ibb-init-lcd-voltage", |
| 3471 | &(labibb->ibb_vreg.curr_volt)); |
| 3472 | if (rc < 0) { |
| 3473 | pr_err("get qcom,qpnp-ibb-init-lcd-voltage failed, rc = %d\n", |
| 3474 | rc); |
| 3475 | return rc; |
| 3476 | } |
| 3477 | } else if (!(val & IBB_VOLTAGE_OVERRIDE_EN)) { |
| 3478 | rc = of_property_read_u32(of_node, |
| 3479 | "qcom,qpnp-ibb-init-amoled-voltage", |
| 3480 | &(labibb->ibb_vreg.curr_volt)); |
| 3481 | if (rc < 0) { |
| 3482 | pr_err("get qcom,qpnp-ibb-init-amoled-voltage failed, rc = %d\n", |
| 3483 | rc); |
| 3484 | return rc; |
| 3485 | } |
| 3486 | |
| 3487 | } |
| 3488 | |
| 3489 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 3490 | REG_IBB_PWRUP_PWRDN_CTL_1, &val, 1); |
| 3491 | if (rc < 0) { |
| 3492 | pr_err("qpnp_labibb_config_init read register %x failed rc = %d\n", |
| 3493 | REG_IBB_PWRUP_PWRDN_CTL_1, rc); |
| 3494 | return rc; |
| 3495 | } |
| 3496 | |
| 3497 | index = (val & IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK) >> |
| 3498 | IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT; |
| 3499 | labibb->ibb_vreg.pwrup_dly = ibb_pwrup_dly_table[index]; |
| 3500 | index = val & IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK; |
| 3501 | labibb->ibb_vreg.pwrdn_dly = ibb_pwrdn_dly_table[index]; |
| 3502 | |
| 3503 | labibb->ibb_vreg.vreg_enabled = 1; |
| 3504 | } else { |
| 3505 | /* SWIRE_RDY and IBB_MODULE_EN not enabled */ |
| 3506 | rc = qpnp_ibb_dt_init(labibb, of_node); |
| 3507 | if (rc < 0) { |
| 3508 | pr_err("qpnp-ibb: wrong DT parameter specified: rc = %d\n", |
| 3509 | rc); |
| 3510 | return rc; |
| 3511 | } |
| 3512 | } |
| 3513 | |
| 3514 | if (labibb->mode == QPNP_LABIBB_AMOLED_MODE && |
| 3515 | qpnp_ibb_poff_ctl_required(labibb)) { |
| 3516 | |
| 3517 | val = IBB_OVERRIDE_NONOVERLAP | IBB_NFET_GATE_DELAY_2; |
| 3518 | rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, |
| 3519 | REG_IBB_NONOVERLAP_TIME_1, |
| 3520 | IBB_OVERRIDE_NONOVERLAP | IBB_NONOVERLAP_NFET_MASK, |
| 3521 | val); |
| 3522 | |
| 3523 | if (rc < 0) { |
| 3524 | pr_err("qpnp_labibb_sec_masked_write register %x failed rc = %d\n", |
| 3525 | REG_IBB_NONOVERLAP_TIME_1, rc); |
| 3526 | return rc; |
| 3527 | } |
| 3528 | |
| 3529 | val = IBB_N2P_MUX_SEL; |
| 3530 | rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, |
| 3531 | REG_IBB_NONOVERLAP_TIME_2, val); |
| 3532 | |
| 3533 | if (rc < 0) { |
| 3534 | pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", |
| 3535 | REG_IBB_NONOVERLAP_TIME_2, rc); |
| 3536 | return rc; |
| 3537 | } |
| 3538 | |
| 3539 | val = IBB_FASTER_PFET_OFF; |
| 3540 | rc = qpnp_labibb_masked_write(labibb, |
| 3541 | labibb->ibb_base + REG_IBB_SPARE_CTL, |
| 3542 | IBB_POFF_CTL_MASK, val); |
| 3543 | if (rc < 0) { |
| 3544 | pr_err("write to register %x failed rc = %d\n", |
| 3545 | REG_IBB_SPARE_CTL, rc); |
| 3546 | return rc; |
| 3547 | } |
| 3548 | } |
| 3549 | |
| 3550 | if (labibb->standalone) { |
| 3551 | val = 0; |
| 3552 | rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, |
| 3553 | REG_IBB_PWRUP_PWRDN_CTL_1, val); |
| 3554 | if (rc < 0) { |
| 3555 | pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", |
| 3556 | REG_IBB_PWRUP_PWRDN_CTL_1, rc); |
| 3557 | return rc; |
| 3558 | } |
| 3559 | labibb->ibb_vreg.pwrup_dly = 0; |
| 3560 | labibb->ibb_vreg.pwrdn_dly = 0; |
| 3561 | } |
| 3562 | |
| 3563 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_MODULE_RDY, |
| 3564 | &val, 1); |
| 3565 | if (rc < 0) { |
| 3566 | pr_err("qpnp_ibb_read read register %x failed rc = %d\n", |
| 3567 | REG_IBB_MODULE_RDY, rc); |
| 3568 | return rc; |
| 3569 | } |
| 3570 | |
| 3571 | if (!(val & IBB_MODULE_RDY_EN)) { |
| 3572 | val = IBB_MODULE_RDY_EN; |
| 3573 | |
| 3574 | rc = qpnp_labibb_write(labibb, labibb->ibb_base + |
| 3575 | REG_IBB_MODULE_RDY, &val, 1); |
| 3576 | |
| 3577 | if (rc < 0) { |
| 3578 | pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", |
| 3579 | REG_IBB_MODULE_RDY, rc); |
| 3580 | return rc; |
| 3581 | } |
| 3582 | } |
| 3583 | |
| 3584 | if (of_property_read_bool(of_node, |
| 3585 | "qcom,qpnp-ibb-enable-pfm-mode")) { |
| 3586 | rc = qpnp_ibb_pfm_mode_enable(labibb, of_node); |
| 3587 | if (rc < 0) |
| 3588 | return rc; |
| 3589 | } |
| 3590 | |
| 3591 | if (labibb->pbs_control) { |
| 3592 | rc = qpnp_labibb_pbs_mode_enable(labibb, of_node); |
| 3593 | if (rc < 0) |
| 3594 | return rc; |
| 3595 | } |
| 3596 | |
| 3597 | if (init_data->constraints.name) { |
| 3598 | rdesc->owner = THIS_MODULE; |
| 3599 | rdesc->type = REGULATOR_VOLTAGE; |
| 3600 | rdesc->ops = &qpnp_ibb_ops; |
| 3601 | rdesc->name = init_data->constraints.name; |
| 3602 | |
| 3603 | cfg.dev = labibb->dev; |
| 3604 | cfg.init_data = init_data; |
| 3605 | cfg.driver_data = labibb; |
| 3606 | cfg.of_node = of_node; |
| 3607 | |
| 3608 | if (of_get_property(labibb->dev->of_node, "parent-supply", |
| 3609 | NULL)) |
| 3610 | init_data->supply_regulator = "parent"; |
| 3611 | |
| 3612 | init_data->constraints.valid_ops_mask |
| 3613 | |= REGULATOR_CHANGE_VOLTAGE | |
| 3614 | REGULATOR_CHANGE_STATUS; |
| 3615 | |
| 3616 | labibb->ibb_vreg.rdev = regulator_register(rdesc, &cfg); |
| 3617 | if (IS_ERR(labibb->ibb_vreg.rdev)) { |
| 3618 | rc = PTR_ERR(labibb->ibb_vreg.rdev); |
| 3619 | labibb->ibb_vreg.rdev = NULL; |
| 3620 | pr_err("unable to get regulator init data for qpnp ibb regulator, rc = %d\n", |
| 3621 | rc); |
| 3622 | |
| 3623 | return rc; |
| 3624 | } |
| 3625 | } else { |
| 3626 | dev_err(labibb->dev, "qpnp ibb regulator name missing\n"); |
| 3627 | return -EINVAL; |
| 3628 | } |
| 3629 | |
| 3630 | return 0; |
| 3631 | } |
| 3632 | |
| 3633 | static int qpnp_lab_register_irq(struct device_node *child, |
| 3634 | struct qpnp_labibb *labibb) |
| 3635 | { |
| 3636 | if (is_lab_vreg_ok_irq_available(labibb)) { |
| 3637 | labibb->lab_vreg.lab_vreg_ok_irq = |
| 3638 | of_irq_get_byname(child, "lab-vreg-ok"); |
| 3639 | if (labibb->lab_vreg.lab_vreg_ok_irq < 0) { |
| 3640 | pr_err("Invalid lab-vreg-ok irq\n"); |
| 3641 | return -EINVAL; |
| 3642 | } |
| 3643 | } |
| 3644 | |
| 3645 | return 0; |
| 3646 | } |
| 3647 | |
| 3648 | static int qpnp_labibb_check_ttw_supported(struct qpnp_labibb *labibb) |
| 3649 | { |
| 3650 | int rc = 0; |
| 3651 | u8 val; |
| 3652 | |
| 3653 | switch (labibb->pmic_rev_id->pmic_subtype) { |
| 3654 | case PMI8996_SUBTYPE: |
| 3655 | rc = qpnp_labibb_read(labibb, labibb->ibb_base + |
| 3656 | REG_IBB_REVISION4, &val, 1); |
| 3657 | if (rc < 0) { |
| 3658 | pr_err("qpnp_labibb_read register %x failed rc = %d\n", |
| 3659 | REG_IBB_REVISION4, rc); |
| 3660 | return rc; |
| 3661 | } |
| 3662 | |
| 3663 | /* PMI8996 has revision 1 */ |
| 3664 | if (val < 1) { |
| 3665 | pr_err("TTW feature cannot be enabled for revision %d\n", |
| 3666 | val); |
| 3667 | labibb->ttw_en = false; |
| 3668 | } |
| 3669 | /* FORCE_LAB_ON in TTW is not required for PMI8996 */ |
| 3670 | labibb->ttw_force_lab_on = false; |
| 3671 | break; |
| 3672 | case PMI8950_SUBTYPE: |
| 3673 | /* TTW supported for all revisions */ |
| 3674 | break; |
| 3675 | default: |
| 3676 | pr_info("TTW mode not supported for PMIC-subtype = %d\n", |
| 3677 | labibb->pmic_rev_id->pmic_subtype); |
| 3678 | labibb->ttw_en = false; |
| 3679 | break; |
| 3680 | |
| 3681 | } |
| 3682 | return rc; |
| 3683 | } |
| 3684 | |
| 3685 | static int qpnp_labibb_regulator_probe(struct platform_device *pdev) |
| 3686 | { |
| 3687 | struct qpnp_labibb *labibb; |
| 3688 | unsigned int base; |
| 3689 | struct device_node *child, *revid_dev_node; |
| 3690 | const char *mode_name; |
| 3691 | u8 type, revision; |
| 3692 | int rc = 0; |
| 3693 | |
| 3694 | labibb = devm_kzalloc(&pdev->dev, sizeof(*labibb), GFP_KERNEL); |
| 3695 | if (labibb == NULL) |
| 3696 | return -ENOMEM; |
| 3697 | |
| 3698 | labibb->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 3699 | if (!labibb->regmap) { |
| 3700 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 3701 | return -EINVAL; |
| 3702 | } |
| 3703 | |
| 3704 | labibb->dev = &(pdev->dev); |
| 3705 | labibb->pdev = pdev; |
| 3706 | |
| 3707 | mutex_init(&(labibb->lab_vreg.lab_mutex)); |
| 3708 | mutex_init(&(labibb->ibb_vreg.ibb_mutex)); |
| 3709 | mutex_init(&(labibb->bus_mutex)); |
| 3710 | |
| 3711 | revid_dev_node = of_parse_phandle(labibb->dev->of_node, |
| 3712 | "qcom,pmic-revid", 0); |
| 3713 | if (!revid_dev_node) { |
| 3714 | pr_err("Missing qcom,pmic-revid property - driver failed\n"); |
| 3715 | return -EINVAL; |
| 3716 | } |
| 3717 | |
| 3718 | labibb->pmic_rev_id = get_revid_data(revid_dev_node); |
| 3719 | if (IS_ERR(labibb->pmic_rev_id)) { |
| 3720 | pr_debug("Unable to get revid data\n"); |
| 3721 | return -EPROBE_DEFER; |
| 3722 | } |
| 3723 | |
| 3724 | if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { |
| 3725 | labibb->ibb_ver_ops = &ibb_ops_v2; |
| 3726 | labibb->lab_ver_ops = &lab_ops_v2; |
| 3727 | } else { |
| 3728 | labibb->ibb_ver_ops = &ibb_ops_v1; |
| 3729 | labibb->lab_ver_ops = &lab_ops_v1; |
| 3730 | } |
| 3731 | |
| 3732 | if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { |
| 3733 | labibb->mode = QPNP_LABIBB_AMOLED_MODE; |
| 3734 | } else { |
| 3735 | rc = of_property_read_string(labibb->dev->of_node, |
| 3736 | "qcom,qpnp-labibb-mode", &mode_name); |
| 3737 | if (!rc) { |
| 3738 | if (strcmp("lcd", mode_name) == 0) { |
| 3739 | labibb->mode = QPNP_LABIBB_LCD_MODE; |
| 3740 | } else if (strcmp("amoled", mode_name) == 0) { |
| 3741 | labibb->mode = QPNP_LABIBB_AMOLED_MODE; |
| 3742 | } else { |
| 3743 | pr_err("Invalid device property in qcom,qpnp-labibb-mode: %s\n", |
| 3744 | mode_name); |
| 3745 | return -EINVAL; |
| 3746 | } |
| 3747 | } else { |
| 3748 | pr_err("qpnp_labibb: qcom,qpnp-labibb-mode is missing.\n"); |
| 3749 | return rc; |
| 3750 | } |
| 3751 | } |
| 3752 | |
| 3753 | labibb->standalone = of_property_read_bool(labibb->dev->of_node, |
| 3754 | "qcom,labibb-standalone"); |
| 3755 | |
| 3756 | labibb->ttw_en = of_property_read_bool(labibb->dev->of_node, |
| 3757 | "qcom,labibb-touch-to-wake-en"); |
| 3758 | if (labibb->ttw_en && labibb->mode != QPNP_LABIBB_LCD_MODE) { |
| 3759 | pr_err("Invalid mode for TTW\n"); |
| 3760 | return -EINVAL; |
| 3761 | } |
| 3762 | |
| 3763 | labibb->ttw_force_lab_on = of_property_read_bool( |
| 3764 | labibb->dev->of_node, "qcom,labibb-ttw-force-lab-on"); |
| 3765 | |
| 3766 | labibb->swire_control = of_property_read_bool(labibb->dev->of_node, |
| 3767 | "qcom,swire-control"); |
| 3768 | |
| 3769 | labibb->pbs_control = of_property_read_bool(labibb->dev->of_node, |
| 3770 | "qcom,pbs-control"); |
| 3771 | if (labibb->swire_control && labibb->mode != QPNP_LABIBB_AMOLED_MODE) { |
| 3772 | pr_err("Invalid mode for SWIRE control\n"); |
| 3773 | return -EINVAL; |
| 3774 | } |
| 3775 | |
| 3776 | if (labibb->swire_control) { |
| 3777 | labibb->skip_2nd_swire_cmd = |
| 3778 | of_property_read_bool(labibb->dev->of_node, |
| 3779 | "qcom,skip-2nd-swire-cmd"); |
| 3780 | |
| 3781 | rc = of_property_read_u32(labibb->dev->of_node, |
| 3782 | "qcom,swire-2nd-cmd-delay", |
| 3783 | &labibb->swire_2nd_cmd_delay); |
| 3784 | if (rc < 0) |
| 3785 | labibb->swire_2nd_cmd_delay = |
| 3786 | SWIRE_DEFAULT_2ND_CMD_DLY_MS; |
| 3787 | |
| 3788 | rc = of_property_read_u32(labibb->dev->of_node, |
| 3789 | "qcom,swire-ibb-ps-enable-delay", |
| 3790 | &labibb->swire_ibb_ps_enable_delay); |
| 3791 | if (rc < 0) |
| 3792 | labibb->swire_ibb_ps_enable_delay = |
| 3793 | SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS; |
| 3794 | } |
| 3795 | |
| 3796 | if (of_get_available_child_count(pdev->dev.of_node) == 0) { |
| 3797 | pr_err("no child nodes\n"); |
| 3798 | return -ENXIO; |
| 3799 | } |
| 3800 | |
| 3801 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
| 3802 | rc = of_property_read_u32(child, "reg", &base); |
| 3803 | if (rc < 0) { |
| 3804 | dev_err(&pdev->dev, |
| 3805 | "Couldn't find reg in node = %s rc = %d\n", |
| 3806 | child->full_name, rc); |
| 3807 | return rc; |
| 3808 | } |
| 3809 | |
| 3810 | rc = qpnp_labibb_read(labibb, base + REG_REVISION_2, |
| 3811 | &revision, 1); |
| 3812 | if (rc < 0) { |
| 3813 | pr_err("Reading REVISION_2 failed rc=%d\n", rc); |
| 3814 | goto fail_registration; |
| 3815 | } |
| 3816 | |
| 3817 | rc = qpnp_labibb_read(labibb, base + REG_PERPH_TYPE, |
| 3818 | &type, 1); |
| 3819 | if (rc < 0) { |
| 3820 | pr_err("Peripheral type read failed rc=%d\n", rc); |
| 3821 | goto fail_registration; |
| 3822 | } |
| 3823 | |
| 3824 | switch (type) { |
| 3825 | case QPNP_LAB_TYPE: |
| 3826 | labibb->lab_base = base; |
| 3827 | labibb->lab_dig_major = revision; |
| 3828 | rc = qpnp_lab_register_irq(child, labibb); |
| 3829 | if (rc) { |
| 3830 | pr_err("Failed to register LAB IRQ rc=%d\n", |
| 3831 | rc); |
| 3832 | goto fail_registration; |
| 3833 | } |
| 3834 | rc = register_qpnp_lab_regulator(labibb, child); |
| 3835 | if (rc < 0) |
| 3836 | goto fail_registration; |
| 3837 | break; |
| 3838 | |
| 3839 | case QPNP_IBB_TYPE: |
| 3840 | labibb->ibb_base = base; |
| 3841 | labibb->ibb_dig_major = revision; |
| 3842 | rc = register_qpnp_ibb_regulator(labibb, child); |
| 3843 | if (rc < 0) |
| 3844 | goto fail_registration; |
| 3845 | break; |
| 3846 | |
| 3847 | default: |
| 3848 | pr_err("qpnp_labibb: unknown peripheral type %x\n", |
| 3849 | type); |
| 3850 | rc = -EINVAL; |
| 3851 | goto fail_registration; |
| 3852 | } |
| 3853 | } |
| 3854 | |
| 3855 | if (labibb->ttw_en) { |
| 3856 | rc = qpnp_labibb_check_ttw_supported(labibb); |
| 3857 | if (rc < 0) { |
| 3858 | pr_err("pmic revision check failed for TTW rc=%d\n", |
| 3859 | rc); |
| 3860 | goto fail_registration; |
| 3861 | } |
| 3862 | } |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 3863 | |
| 3864 | INIT_WORK(&labibb->lab_vreg_ok_work, qpnp_lab_vreg_notifier_work); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 3865 | dev_set_drvdata(&pdev->dev, labibb); |
| 3866 | pr_info("LAB/IBB registered successfully, lab_vreg enable=%d ibb_vreg enable=%d swire_control=%d\n", |
| 3867 | labibb->lab_vreg.vreg_enabled, |
| 3868 | labibb->ibb_vreg.vreg_enabled, |
| 3869 | labibb->swire_control); |
| 3870 | |
| 3871 | return 0; |
| 3872 | |
| 3873 | fail_registration: |
| 3874 | if (labibb->lab_vreg.rdev) |
| 3875 | regulator_unregister(labibb->lab_vreg.rdev); |
| 3876 | if (labibb->ibb_vreg.rdev) |
| 3877 | regulator_unregister(labibb->ibb_vreg.rdev); |
| 3878 | |
| 3879 | return rc; |
| 3880 | } |
| 3881 | |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 3882 | int qpnp_labibb_notifier_register(struct notifier_block *nb) |
| 3883 | { |
| 3884 | return raw_notifier_chain_register(&labibb_notifier, nb); |
| 3885 | } |
| 3886 | EXPORT_SYMBOL(qpnp_labibb_notifier_register); |
| 3887 | |
| 3888 | int qpnp_labibb_notifier_unregister(struct notifier_block *nb) |
| 3889 | { |
| 3890 | return raw_notifier_chain_unregister(&labibb_notifier, nb); |
| 3891 | } |
| 3892 | EXPORT_SYMBOL(qpnp_labibb_notifier_unregister); |
| 3893 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 3894 | static int qpnp_labibb_regulator_remove(struct platform_device *pdev) |
| 3895 | { |
| 3896 | struct qpnp_labibb *labibb = dev_get_drvdata(&pdev->dev); |
| 3897 | |
| 3898 | if (labibb) { |
| 3899 | if (labibb->lab_vreg.rdev) |
| 3900 | regulator_unregister(labibb->lab_vreg.rdev); |
| 3901 | if (labibb->ibb_vreg.rdev) |
| 3902 | regulator_unregister(labibb->ibb_vreg.rdev); |
Kiran Gunda | 98db95a | 2017-02-10 16:06:13 +0530 | [diff] [blame] | 3903 | |
| 3904 | cancel_work_sync(&labibb->lab_vreg_ok_work); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 3905 | } |
| 3906 | return 0; |
| 3907 | } |
| 3908 | |
| 3909 | static const struct of_device_id spmi_match_table[] = { |
| 3910 | { .compatible = QPNP_LABIBB_REGULATOR_DRIVER_NAME, }, |
| 3911 | { }, |
| 3912 | }; |
| 3913 | |
| 3914 | static struct platform_driver qpnp_labibb_regulator_driver = { |
| 3915 | .driver = { |
| 3916 | .name = QPNP_LABIBB_REGULATOR_DRIVER_NAME, |
| 3917 | .of_match_table = spmi_match_table, |
| 3918 | }, |
| 3919 | .probe = qpnp_labibb_regulator_probe, |
| 3920 | .remove = qpnp_labibb_regulator_remove, |
| 3921 | }; |
| 3922 | |
| 3923 | static int __init qpnp_labibb_regulator_init(void) |
| 3924 | { |
| 3925 | return platform_driver_register(&qpnp_labibb_regulator_driver); |
| 3926 | } |
| 3927 | arch_initcall(qpnp_labibb_regulator_init); |
| 3928 | |
| 3929 | static void __exit qpnp_labibb_regulator_exit(void) |
| 3930 | { |
| 3931 | platform_driver_unregister(&qpnp_labibb_regulator_driver); |
| 3932 | } |
| 3933 | module_exit(qpnp_labibb_regulator_exit); |
| 3934 | |
| 3935 | MODULE_DESCRIPTION("QPNP labibb driver"); |
| 3936 | MODULE_LICENSE("GPL v2"); |