blob: 1fae1881648c5a87e9071d1dc9ade123baab0252 [file] [log] [blame]
Joerg Roedel9f10e5b2015-06-12 09:57:06 +02001
2#define pr_fmt(fmt) "DMAR-IR: " fmt
3
Yinghai Lu5aeecaf2008-08-19 20:49:59 -07004#include <linux/interrupt.h>
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -07005#include <linux/dmar.h>
Suresh Siddha2ae21012008-07-10 11:16:43 -07006#include <linux/spinlock.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +09007#include <linux/slab.h>
Suresh Siddha2ae21012008-07-10 11:16:43 -07008#include <linux/jiffies.h>
Suresh Siddha20f30972009-08-04 12:07:08 -07009#include <linux/hpet.h>
Suresh Siddha2ae21012008-07-10 11:16:43 -070010#include <linux/pci.h>
Suresh Siddhab6fcb332008-07-10 11:16:44 -070011#include <linux/irq.h>
Lv Zheng8b484632013-12-03 08:49:16 +080012#include <linux/intel-iommu.h>
13#include <linux/acpi.h>
Jiang Liub106ee62015-04-13 14:11:32 +080014#include <linux/irqdomain.h>
Joerg Roedelaf3b3582015-06-12 15:00:21 +020015#include <linux/crash_dump.h>
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -070016#include <asm/io_apic.h>
Yinghai Lu17483a12008-12-12 13:14:18 -080017#include <asm/smp.h>
Jaswinder Singh Rajput6d652ea2009-01-07 21:38:59 +053018#include <asm/cpu.h>
Suresh Siddha8a8f4222012-03-30 11:47:08 -070019#include <asm/irq_remapping.h>
Weidong Hanf007e992009-05-23 00:41:15 +080020#include <asm/pci-direct.h>
Joerg Roedel5e2b9302012-03-30 11:47:05 -070021#include <asm/msidef.h>
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -070022
Suresh Siddha8a8f4222012-03-30 11:47:08 -070023#include "irq_remapping.h"
Joerg Roedel736baef2012-03-30 11:47:00 -070024
Feng Wu2705a3d2015-06-09 13:20:32 +080025enum irq_mode {
26 IRQ_REMAPPING,
27 IRQ_POSTING,
28};
29
Joerg Roedeleef93fd2012-03-30 11:46:59 -070030struct ioapic_scope {
31 struct intel_iommu *iommu;
32 unsigned int id;
33 unsigned int bus; /* PCI bus number */
34 unsigned int devfn; /* PCI devfn number */
35};
36
37struct hpet_scope {
38 struct intel_iommu *iommu;
39 u8 id;
40 unsigned int bus;
41 unsigned int devfn;
42};
43
Jiang Liu099c5c02015-04-14 10:29:51 +080044struct irq_2_iommu {
45 struct intel_iommu *iommu;
46 u16 irte_index;
47 u16 sub_handle;
48 u8 irte_mask;
Feng Wu2705a3d2015-06-09 13:20:32 +080049 enum irq_mode mode;
Jiang Liu099c5c02015-04-14 10:29:51 +080050};
51
Jiang Liub106ee62015-04-13 14:11:32 +080052struct intel_ir_data {
53 struct irq_2_iommu irq_2_iommu;
54 struct irte irte_entry;
55 union {
56 struct msi_msg msi_entry;
57 };
58};
59
Joerg Roedeleef93fd2012-03-30 11:46:59 -070060#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
Jiang Liu13d09b62015-01-07 15:31:37 +080061#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
Joerg Roedeleef93fd2012-03-30 11:46:59 -070062
Jiang Liu13d09b62015-01-07 15:31:37 +080063static int __read_mostly eim_mode;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -070064static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
Suresh Siddha20f30972009-08-04 12:07:08 -070065static struct hpet_scope ir_hpet[MAX_HPET_TBS];
Chris Wrightd1423d52010-07-20 11:06:49 -070066
Jiang Liu3a5670e2014-02-19 14:07:33 +080067/*
68 * Lock ordering:
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
73 * Note:
74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
75 * in single-threaded environment with interrupt disabled, so no need to tabke
76 * the dmar_global_lock.
77 */
Thomas Gleixner96f8e982011-07-19 16:28:19 +020078static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
Jiang Liub106ee62015-04-13 14:11:32 +080079static struct irq_domain_ops intel_ir_domain_ops;
Thomas Gleixnerd585d062010-10-10 12:34:27 +020080
Joerg Roedelaf3b3582015-06-12 15:00:21 +020081static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
Jiang Liu694835d2014-01-06 14:18:16 +080082static int __init parse_ioapics_under_ir(void);
83
Joerg Roedelaf3b3582015-06-12 15:00:21 +020084static bool ir_pre_enabled(struct intel_iommu *iommu)
85{
86 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
87}
88
89static void clear_ir_pre_enabled(struct intel_iommu *iommu)
90{
91 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
92}
93
94static void init_ir_status(struct intel_iommu *iommu)
95{
96 u32 gsts;
97
98 gsts = readl(iommu->reg + DMAR_GSTS_REG);
99 if (gsts & DMA_GSTS_IRES)
100 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
101}
102
Jiang Liu8dedf4c2015-04-13 14:11:31 +0800103static int alloc_irte(struct intel_iommu *iommu, int irq,
104 struct irq_2_iommu *irq_iommu, u16 count)
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700105{
106 struct ir_table *table = iommu->ir_table;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700107 unsigned int mask = 0;
Suresh Siddha4c5502b2009-03-16 17:04:53 -0700108 unsigned long flags;
Dan Carpenter9f4c7442014-01-09 08:32:36 +0300109 int index;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700110
Thomas Gleixnerd585d062010-10-10 12:34:27 +0200111 if (!count || !irq_iommu)
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700112 return -1;
113
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700114 if (count > 1) {
115 count = __roundup_pow_of_two(count);
116 mask = ilog2(count);
117 }
118
119 if (mask > ecap_max_handle_mask(iommu->ecap)) {
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200120 pr_err("Requested mask %x exceeds the max invalidation handle"
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700121 " mask value %Lx\n", mask,
122 ecap_max_handle_mask(iommu->ecap));
123 return -1;
124 }
125
Thomas Gleixner96f8e982011-07-19 16:28:19 +0200126 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
Jiang Liu360eb3c2014-01-06 14:18:08 +0800127 index = bitmap_find_free_region(table->bitmap,
128 INTR_REMAP_TABLE_ENTRIES, mask);
129 if (index < 0) {
130 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
131 } else {
Jiang Liu360eb3c2014-01-06 14:18:08 +0800132 irq_iommu->iommu = iommu;
133 irq_iommu->irte_index = index;
134 irq_iommu->sub_handle = 0;
135 irq_iommu->irte_mask = mask;
Feng Wu2705a3d2015-06-09 13:20:32 +0800136 irq_iommu->mode = IRQ_REMAPPING;
Jiang Liu360eb3c2014-01-06 14:18:08 +0800137 }
Thomas Gleixner96f8e982011-07-19 16:28:19 +0200138 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700139
140 return index;
141}
142
Yu Zhao704126a2009-01-04 16:28:52 +0800143static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700144{
145 struct qi_desc desc;
146
147 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
148 | QI_IEC_SELECTIVE;
149 desc.high = 0;
150
Yu Zhao704126a2009-01-04 16:28:52 +0800151 return qi_submit_sync(&desc, iommu);
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700152}
153
Jiang Liu8dedf4c2015-04-13 14:11:31 +0800154static int modify_irte(struct irq_2_iommu *irq_iommu,
155 struct irte *irte_modified)
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700156{
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700157 struct intel_iommu *iommu;
Suresh Siddha4c5502b2009-03-16 17:04:53 -0700158 unsigned long flags;
Thomas Gleixnerd585d062010-10-10 12:34:27 +0200159 struct irte *irte;
160 int rc, index;
161
162 if (!irq_iommu)
163 return -1;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700164
Thomas Gleixner96f8e982011-07-19 16:28:19 +0200165 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700166
Yinghai Lue420dfb2008-08-19 20:50:21 -0700167 iommu = irq_iommu->iommu;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700168
Yinghai Lue420dfb2008-08-19 20:50:21 -0700169 index = irq_iommu->irte_index + irq_iommu->sub_handle;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700170 irte = &iommu->ir_table->base[index];
171
Feng Wu344cb4e2015-10-15 10:19:11 +0800172#if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
173 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
174 bool ret;
175
176 ret = cmpxchg_double(&irte->low, &irte->high,
177 irte->low, irte->high,
178 irte_modified->low, irte_modified->high);
179 /*
180 * We use cmpxchg16 to atomically update the 128-bit IRTE,
181 * and it cannot be updated by the hardware or other processors
182 * behind us, so the return value of cmpxchg16 should be the
183 * same as the old value.
184 */
185 WARN_ON(!ret);
186 } else
187#endif
188 {
189 set_64bit(&irte->low, irte_modified->low);
190 set_64bit(&irte->high, irte_modified->high);
191 }
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700192 __iommu_flush_cache(iommu, irte, sizeof(*irte));
193
Yu Zhao704126a2009-01-04 16:28:52 +0800194 rc = qi_flush_iec(iommu, index, 0);
Feng Wu2705a3d2015-06-09 13:20:32 +0800195
196 /* Update iommu mode according to the IRTE mode */
197 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
Thomas Gleixner96f8e982011-07-19 16:28:19 +0200198 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
Yu Zhao704126a2009-01-04 16:28:52 +0800199
200 return rc;
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700201}
202
Joerg Roedel263b5e82012-03-30 11:47:06 -0700203static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
Suresh Siddha20f30972009-08-04 12:07:08 -0700204{
205 int i;
206
207 for (i = 0; i < MAX_HPET_TBS; i++)
Jiang Liua7a3dad2014-11-09 22:48:00 +0800208 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
Suresh Siddha20f30972009-08-04 12:07:08 -0700209 return ir_hpet[i].iommu;
210 return NULL;
211}
212
Joerg Roedel263b5e82012-03-30 11:47:06 -0700213static struct intel_iommu *map_ioapic_to_ir(int apic)
Suresh Siddha89027d32008-07-10 11:16:56 -0700214{
215 int i;
216
217 for (i = 0; i < MAX_IO_APICS; i++)
Jiang Liua7a3dad2014-11-09 22:48:00 +0800218 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
Suresh Siddha89027d32008-07-10 11:16:56 -0700219 return ir_ioapic[i].iommu;
220 return NULL;
221}
222
Joerg Roedel263b5e82012-03-30 11:47:06 -0700223static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
Suresh Siddha75c46fa2008-07-10 11:16:57 -0700224{
225 struct dmar_drhd_unit *drhd;
226
227 drhd = dmar_find_matched_drhd_unit(dev);
228 if (!drhd)
229 return NULL;
230
231 return drhd->iommu;
232}
233
Weidong Hanc4658b42009-05-23 00:41:14 +0800234static int clear_entries(struct irq_2_iommu *irq_iommu)
235{
236 struct irte *start, *entry, *end;
237 struct intel_iommu *iommu;
238 int index;
239
240 if (irq_iommu->sub_handle)
241 return 0;
242
243 iommu = irq_iommu->iommu;
Jiang Liu8dedf4c2015-04-13 14:11:31 +0800244 index = irq_iommu->irte_index;
Weidong Hanc4658b42009-05-23 00:41:14 +0800245
246 start = iommu->ir_table->base + index;
247 end = start + (1 << irq_iommu->irte_mask);
248
249 for (entry = start; entry < end; entry++) {
Linus Torvaldsc513b672010-08-06 11:02:31 -0700250 set_64bit(&entry->low, 0);
251 set_64bit(&entry->high, 0);
Weidong Hanc4658b42009-05-23 00:41:14 +0800252 }
Jiang Liu360eb3c2014-01-06 14:18:08 +0800253 bitmap_release_region(iommu->ir_table->bitmap, index,
254 irq_iommu->irte_mask);
Weidong Hanc4658b42009-05-23 00:41:14 +0800255
256 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
257}
258
Weidong Hanf007e992009-05-23 00:41:15 +0800259/*
260 * source validation type
261 */
262#define SVT_NO_VERIFY 0x0 /* no verification is required */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300263#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
Weidong Hanf007e992009-05-23 00:41:15 +0800264#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
265
266/*
267 * source-id qualifier
268 */
269#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
270#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
271 * the third least significant bit
272 */
273#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
274 * the second and third least significant bits
275 */
276#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
277 * the least three significant bits
278 */
279
280/*
281 * set SVT, SQ and SID fields of irte to verify
282 * source ids of interrupt requests
283 */
284static void set_irte_sid(struct irte *irte, unsigned int svt,
285 unsigned int sq, unsigned int sid)
286{
Chris Wrightd1423d52010-07-20 11:06:49 -0700287 if (disable_sourceid_checking)
288 svt = SVT_NO_VERIFY;
Weidong Hanf007e992009-05-23 00:41:15 +0800289 irte->svt = svt;
290 irte->sq = sq;
291 irte->sid = sid;
292}
293
Joerg Roedel263b5e82012-03-30 11:47:06 -0700294static int set_ioapic_sid(struct irte *irte, int apic)
Weidong Hanf007e992009-05-23 00:41:15 +0800295{
296 int i;
297 u16 sid = 0;
298
299 if (!irte)
300 return -1;
301
Jiang Liu3a5670e2014-02-19 14:07:33 +0800302 down_read(&dmar_global_lock);
Weidong Hanf007e992009-05-23 00:41:15 +0800303 for (i = 0; i < MAX_IO_APICS; i++) {
Jiang Liua7a3dad2014-11-09 22:48:00 +0800304 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
Weidong Hanf007e992009-05-23 00:41:15 +0800305 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
306 break;
307 }
308 }
Jiang Liu3a5670e2014-02-19 14:07:33 +0800309 up_read(&dmar_global_lock);
Weidong Hanf007e992009-05-23 00:41:15 +0800310
311 if (sid == 0) {
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200312 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
Weidong Hanf007e992009-05-23 00:41:15 +0800313 return -1;
314 }
315
Jiang Liu2fe2c602014-01-06 14:18:17 +0800316 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
Weidong Hanf007e992009-05-23 00:41:15 +0800317
318 return 0;
319}
320
Joerg Roedel263b5e82012-03-30 11:47:06 -0700321static int set_hpet_sid(struct irte *irte, u8 id)
Suresh Siddha20f30972009-08-04 12:07:08 -0700322{
323 int i;
324 u16 sid = 0;
325
326 if (!irte)
327 return -1;
328
Jiang Liu3a5670e2014-02-19 14:07:33 +0800329 down_read(&dmar_global_lock);
Suresh Siddha20f30972009-08-04 12:07:08 -0700330 for (i = 0; i < MAX_HPET_TBS; i++) {
Jiang Liua7a3dad2014-11-09 22:48:00 +0800331 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
Suresh Siddha20f30972009-08-04 12:07:08 -0700332 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
333 break;
334 }
335 }
Jiang Liu3a5670e2014-02-19 14:07:33 +0800336 up_read(&dmar_global_lock);
Suresh Siddha20f30972009-08-04 12:07:08 -0700337
338 if (sid == 0) {
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200339 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
Suresh Siddha20f30972009-08-04 12:07:08 -0700340 return -1;
341 }
342
343 /*
344 * Should really use SQ_ALL_16. Some platforms are broken.
345 * While we figure out the right quirks for these broken platforms, use
346 * SQ_13_IGNORE_3 for now.
347 */
348 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
349
350 return 0;
351}
352
Alex Williamson579305f2014-07-03 09:51:43 -0600353struct set_msi_sid_data {
354 struct pci_dev *pdev;
355 u16 alias;
356};
357
358static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
359{
360 struct set_msi_sid_data *data = opaque;
361
362 data->pdev = pdev;
363 data->alias = alias;
364
365 return 0;
366}
367
Joerg Roedel263b5e82012-03-30 11:47:06 -0700368static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
Weidong Hanf007e992009-05-23 00:41:15 +0800369{
Alex Williamson579305f2014-07-03 09:51:43 -0600370 struct set_msi_sid_data data;
Weidong Hanf007e992009-05-23 00:41:15 +0800371
372 if (!irte || !dev)
373 return -1;
374
Alex Williamson579305f2014-07-03 09:51:43 -0600375 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
Weidong Hanf007e992009-05-23 00:41:15 +0800376
Alex Williamson579305f2014-07-03 09:51:43 -0600377 /*
378 * DMA alias provides us with a PCI device and alias. The only case
379 * where the it will return an alias on a different bus than the
380 * device is the case of a PCIe-to-PCI bridge, where the alias is for
381 * the subordinate bus. In this case we can only verify the bus.
382 *
383 * If the alias device is on a different bus than our source device
384 * then we have a topology based alias, use it.
385 *
386 * Otherwise, the alias is for a device DMA quirk and we cannot
387 * assume that MSI uses the same requester ID. Therefore use the
388 * original device.
389 */
390 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
391 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
392 PCI_DEVID(PCI_BUS_NUM(data.alias),
393 dev->bus->number));
394 else if (data.pdev->bus->number != dev->bus->number)
395 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
396 else
397 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
398 PCI_DEVID(dev->bus->number, dev->devfn));
Weidong Hanf007e992009-05-23 00:41:15 +0800399
400 return 0;
401}
402
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200403static int iommu_load_old_irte(struct intel_iommu *iommu)
404{
Dan Williamsdfddb962015-10-09 18:16:46 -0400405 struct irte *old_ir_table;
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200406 phys_addr_t irt_phys;
Joerg Roedel7c3c9872015-06-12 15:06:26 +0200407 unsigned int i;
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200408 size_t size;
409 u64 irta;
410
411 if (!is_kdump_kernel()) {
412 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
413 iommu->name);
414 clear_ir_pre_enabled(iommu);
415 iommu_disable_irq_remapping(iommu);
416 return -EINVAL;
417 }
418
419 /* Check whether the old ir-table has the same size as ours */
420 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
421 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
422 != INTR_REMAP_TABLE_REG_SIZE)
423 return -EINVAL;
424
425 irt_phys = irta & VTD_PAGE_MASK;
426 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
427
428 /* Map the old IR table */
Dan Williamsdfddb962015-10-09 18:16:46 -0400429 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200430 if (!old_ir_table)
431 return -ENOMEM;
432
433 /* Copy data over */
Dan Williamsdfddb962015-10-09 18:16:46 -0400434 memcpy(iommu->ir_table->base, old_ir_table, size);
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200435
436 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
437
Joerg Roedel7c3c9872015-06-12 15:06:26 +0200438 /*
439 * Now check the table for used entries and mark those as
440 * allocated in the bitmap
441 */
442 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
443 if (iommu->ir_table->base[i].present)
444 bitmap_set(iommu->ir_table->bitmap, i, 1);
445 }
446
Dan Williamsdfddb962015-10-09 18:16:46 -0400447 memunmap(old_ir_table);
Dan Williams50690762015-07-30 12:54:01 -0400448
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200449 return 0;
450}
451
452
Suresh Siddha95a02e92012-03-30 11:47:07 -0700453static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700454{
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +0200455 unsigned long flags;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700456 u64 addr;
David Woodhousec416daa2009-05-10 20:30:58 +0100457 u32 sts;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700458
459 addr = virt_to_phys((void *)iommu->ir_table->base);
460
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200461 raw_spin_lock_irqsave(&iommu->register_lock, flags);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700462
463 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
464 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
465
466 /* Set interrupt-remapping table pointer */
Jan Kiszkaf63ef692014-08-11 13:13:25 +0200467 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700468
469 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
470 readl, (sts & DMA_GSTS_IRTPS), sts);
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200471 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700472
473 /*
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +0200474 * Global invalidation of interrupt entry cache to make sure the
475 * hardware uses the new irq remapping table.
Suresh Siddha2ae21012008-07-10 11:16:43 -0700476 */
477 qi_global_iec(iommu);
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +0200478}
479
480static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
481{
482 unsigned long flags;
483 u32 sts;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700484
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200485 raw_spin_lock_irqsave(&iommu->register_lock, flags);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700486
487 /* Enable interrupt-remapping */
Suresh Siddha2ae21012008-07-10 11:16:43 -0700488 iommu->gcmd |= DMA_GCMD_IRE;
Andy Lutomirskiaf8d1022013-02-01 14:57:43 -0800489 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
David Woodhousec416daa2009-05-10 20:30:58 +0100490 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700491
492 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
493 readl, (sts & DMA_GSTS_IRES), sts);
494
Andy Lutomirskiaf8d1022013-02-01 14:57:43 -0800495 /*
496 * With CFI clear in the Global Command register, we should be
497 * protected from dangerous (i.e. compatibility) interrupts
498 * regardless of x2apic status. Check just to be sure.
499 */
500 if (sts & DMA_GSTS_CFIS)
501 WARN(1, KERN_WARNING
502 "Compatibility-format IRQs enabled despite intr remapping;\n"
503 "you are vulnerable to IRQ injection.\n");
504
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200505 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700506}
507
Jiang Liua7a3dad2014-11-09 22:48:00 +0800508static int intel_setup_irq_remapping(struct intel_iommu *iommu)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700509{
510 struct ir_table *ir_table;
511 struct page *pages;
Jiang Liu360eb3c2014-01-06 14:18:08 +0800512 unsigned long *bitmap;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700513
Jiang Liua7a3dad2014-11-09 22:48:00 +0800514 if (iommu->ir_table)
515 return 0;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700516
Thomas Gleixnere3a981d2015-01-07 15:31:30 +0800517 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
Jiang Liua7a3dad2014-11-09 22:48:00 +0800518 if (!ir_table)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700519 return -ENOMEM;
520
Thomas Gleixnere3a981d2015-01-07 15:31:30 +0800521 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
Suresh Siddha824cd752009-10-02 11:01:23 -0700522 INTR_REMAP_PAGE_ORDER);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700523 if (!pages) {
Jiang Liu360eb3c2014-01-06 14:18:08 +0800524 pr_err("IR%d: failed to allocate pages of order %d\n",
525 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
Jiang Liua7a3dad2014-11-09 22:48:00 +0800526 goto out_free_table;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700527 }
528
Jiang Liu360eb3c2014-01-06 14:18:08 +0800529 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
530 sizeof(long), GFP_ATOMIC);
531 if (bitmap == NULL) {
532 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
Jiang Liua7a3dad2014-11-09 22:48:00 +0800533 goto out_free_pages;
Jiang Liu360eb3c2014-01-06 14:18:08 +0800534 }
535
Jiang Liub106ee62015-04-13 14:11:32 +0800536 iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
537 0, INTR_REMAP_TABLE_ENTRIES,
538 NULL, &intel_ir_domain_ops,
539 iommu);
540 if (!iommu->ir_domain) {
541 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
542 goto out_free_bitmap;
543 }
544 iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
545
Suresh Siddha2ae21012008-07-10 11:16:43 -0700546 ir_table->base = page_address(pages);
Jiang Liu360eb3c2014-01-06 14:18:08 +0800547 ir_table->bitmap = bitmap;
Jiang Liua7a3dad2014-11-09 22:48:00 +0800548 iommu->ir_table = ir_table;
Joerg Roedel9e4e49d2015-06-12 14:23:56 +0200549
550 /*
551 * If the queued invalidation is already initialized,
552 * shouldn't disable it.
553 */
554 if (!iommu->qi) {
555 /*
556 * Clear previous faults.
557 */
558 dmar_fault(-1, iommu);
559 dmar_disable_qi(iommu);
560
561 if (dmar_enable_qi(iommu)) {
562 pr_err("Failed to enable queued invalidation\n");
563 goto out_free_bitmap;
564 }
565 }
566
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200567 init_ir_status(iommu);
568
569 if (ir_pre_enabled(iommu)) {
570 if (iommu_load_old_irte(iommu))
571 pr_err("Failed to copy IR table for %s from previous kernel\n",
572 iommu->name);
573 else
574 pr_info("Copied IR table for %s from previous kernel\n",
575 iommu->name);
576 }
577
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +0200578 iommu_set_irq_remapping(iommu, eim_mode);
579
Suresh Siddha2ae21012008-07-10 11:16:43 -0700580 return 0;
Jiang Liua7a3dad2014-11-09 22:48:00 +0800581
Jiang Liub106ee62015-04-13 14:11:32 +0800582out_free_bitmap:
583 kfree(bitmap);
Jiang Liua7a3dad2014-11-09 22:48:00 +0800584out_free_pages:
585 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
586out_free_table:
587 kfree(ir_table);
Joerg Roedel9e4e49d2015-06-12 14:23:56 +0200588
589 iommu->ir_table = NULL;
590
Jiang Liua7a3dad2014-11-09 22:48:00 +0800591 return -ENOMEM;
592}
593
594static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
595{
596 if (iommu && iommu->ir_table) {
Jiang Liub106ee62015-04-13 14:11:32 +0800597 if (iommu->ir_msi_domain) {
598 irq_domain_remove(iommu->ir_msi_domain);
599 iommu->ir_msi_domain = NULL;
600 }
601 if (iommu->ir_domain) {
602 irq_domain_remove(iommu->ir_domain);
603 iommu->ir_domain = NULL;
604 }
Jiang Liua7a3dad2014-11-09 22:48:00 +0800605 free_pages((unsigned long)iommu->ir_table->base,
606 INTR_REMAP_PAGE_ORDER);
607 kfree(iommu->ir_table->bitmap);
608 kfree(iommu->ir_table);
609 iommu->ir_table = NULL;
610 }
Suresh Siddha2ae21012008-07-10 11:16:43 -0700611}
612
Suresh Siddhaeba67e52009-03-16 17:04:56 -0700613/*
614 * Disable Interrupt Remapping.
615 */
Suresh Siddha95a02e92012-03-30 11:47:07 -0700616static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
Suresh Siddhaeba67e52009-03-16 17:04:56 -0700617{
618 unsigned long flags;
619 u32 sts;
620
621 if (!ecap_ir_support(iommu->ecap))
622 return;
623
Fenghua Yub24696b2009-03-27 14:22:44 -0700624 /*
625 * global invalidation of interrupt entry cache before disabling
626 * interrupt-remapping.
627 */
628 qi_global_iec(iommu);
629
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200630 raw_spin_lock_irqsave(&iommu->register_lock, flags);
Suresh Siddhaeba67e52009-03-16 17:04:56 -0700631
632 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
633 if (!(sts & DMA_GSTS_IRES))
634 goto end;
635
636 iommu->gcmd &= ~DMA_GCMD_IRE;
637 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
638
639 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
640 readl, !(sts & DMA_GSTS_IRES), sts);
641
642end:
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200643 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
Suresh Siddhaeba67e52009-03-16 17:04:56 -0700644}
645
Suresh Siddha41750d32011-08-23 17:05:18 -0700646static int __init dmar_x2apic_optout(void)
647{
648 struct acpi_table_dmar *dmar;
649 dmar = (struct acpi_table_dmar *)dmar_tbl;
650 if (!dmar || no_x2apic_optout)
651 return 0;
652 return dmar->flags & DMAR_X2APIC_OPT_OUT;
653}
654
Thomas Gleixner11190302015-01-07 15:31:29 +0800655static void __init intel_cleanup_irq_remapping(void)
656{
657 struct dmar_drhd_unit *drhd;
658 struct intel_iommu *iommu;
659
660 for_each_iommu(iommu, drhd) {
661 if (ecap_ir_support(iommu->ecap)) {
662 iommu_disable_irq_remapping(iommu);
663 intel_teardown_irq_remapping(iommu);
664 }
665 }
666
667 if (x2apic_supported())
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200668 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
Thomas Gleixner11190302015-01-07 15:31:29 +0800669}
670
671static int __init intel_prepare_irq_remapping(void)
672{
673 struct dmar_drhd_unit *drhd;
674 struct intel_iommu *iommu;
Joerg Roedel23256d02015-06-12 14:15:49 +0200675 int eim = 0;
Thomas Gleixner11190302015-01-07 15:31:29 +0800676
Jiang Liu2966d952015-01-07 15:31:35 +0800677 if (irq_remap_broken) {
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200678 pr_warn("This system BIOS has enabled interrupt remapping\n"
Jiang Liu2966d952015-01-07 15:31:35 +0800679 "on a chipset that contains an erratum making that\n"
680 "feature unstable. To maintain system stability\n"
681 "interrupt remapping is being disabled. Please\n"
682 "contact your BIOS vendor for an update\n");
683 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
Jiang Liu2966d952015-01-07 15:31:35 +0800684 return -ENODEV;
685 }
686
Thomas Gleixner11190302015-01-07 15:31:29 +0800687 if (dmar_table_init() < 0)
Jiang Liu2966d952015-01-07 15:31:35 +0800688 return -ENODEV;
689
690 if (!dmar_ir_support())
691 return -ENODEV;
Thomas Gleixner11190302015-01-07 15:31:29 +0800692
Joerg Roedelb61e5e82015-11-02 19:57:31 +0900693 if (parse_ioapics_under_ir()) {
Joerg Roedel9f10e5b2015-06-12 09:57:06 +0200694 pr_info("Not enabling interrupt remapping\n");
Thomas Gleixner11190302015-01-07 15:31:29 +0800695 goto error;
696 }
697
Joerg Roedel69cf1d82015-01-07 15:31:36 +0800698 /* First make sure all IOMMUs support IRQ remapping */
Jiang Liu2966d952015-01-07 15:31:35 +0800699 for_each_iommu(iommu, drhd)
Joerg Roedel69cf1d82015-01-07 15:31:36 +0800700 if (!ecap_ir_support(iommu->ecap))
Thomas Gleixner11190302015-01-07 15:31:29 +0800701 goto error;
Joerg Roedel69cf1d82015-01-07 15:31:36 +0800702
Joerg Roedel23256d02015-06-12 14:15:49 +0200703 /* Detect remapping mode: lapic or x2apic */
704 if (x2apic_supported()) {
705 eim = !dmar_x2apic_optout();
706 if (!eim) {
707 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
708 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
709 }
710 }
711
712 for_each_iommu(iommu, drhd) {
713 if (eim && !ecap_eim_support(iommu->ecap)) {
714 pr_info("%s does not support EIM\n", iommu->name);
715 eim = 0;
716 }
717 }
718
719 eim_mode = eim;
720 if (eim)
721 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
722
Joerg Roedel9e4e49d2015-06-12 14:23:56 +0200723 /* Do the initializations early */
724 for_each_iommu(iommu, drhd) {
725 if (intel_setup_irq_remapping(iommu)) {
726 pr_err("Failed to setup irq remapping for %s\n",
727 iommu->name);
Joerg Roedel69cf1d82015-01-07 15:31:36 +0800728 goto error;
Joerg Roedel9e4e49d2015-06-12 14:23:56 +0200729 }
730 }
Joerg Roedel69cf1d82015-01-07 15:31:36 +0800731
Thomas Gleixner11190302015-01-07 15:31:29 +0800732 return 0;
Jiang Liu2966d952015-01-07 15:31:35 +0800733
Thomas Gleixner11190302015-01-07 15:31:29 +0800734error:
735 intel_cleanup_irq_remapping();
Jiang Liu2966d952015-01-07 15:31:35 +0800736 return -ENODEV;
Thomas Gleixner11190302015-01-07 15:31:29 +0800737}
738
Feng Wu3d9b98f2015-06-09 13:20:35 +0800739/*
740 * Set Posted-Interrupts capability.
741 */
742static inline void set_irq_posting_cap(void)
743{
744 struct dmar_drhd_unit *drhd;
745 struct intel_iommu *iommu;
746
747 if (!disable_irq_post) {
Feng Wu344cb4e2015-10-15 10:19:11 +0800748 /*
749 * If IRTE is in posted format, the 'pda' field goes across the
750 * 64-bit boundary, we need use cmpxchg16b to atomically update
751 * it. We only expose posted-interrupt when X86_FEATURE_CX16
752 * is supported. Actually, hardware platforms supporting PI
753 * should have X86_FEATURE_CX16 support, this has been confirmed
754 * with Intel hardware guys.
755 */
756 if ( cpu_has_cx16 )
757 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
Feng Wu3d9b98f2015-06-09 13:20:35 +0800758
759 for_each_iommu(iommu, drhd)
760 if (!cap_pi_support(iommu->cap)) {
761 intel_irq_remap_ops.capability &=
762 ~(1 << IRQ_POSTING_CAP);
763 break;
764 }
765 }
766}
767
Suresh Siddha95a02e92012-03-30 11:47:07 -0700768static int __init intel_enable_irq_remapping(void)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700769{
770 struct dmar_drhd_unit *drhd;
Jiang Liu7c919772014-01-06 14:18:18 +0800771 struct intel_iommu *iommu;
Quentin Lambert2f119c72015-02-06 10:59:53 +0100772 bool setup = false;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700773
774 /*
775 * Setup Interrupt-remapping for all the DRHD's now.
776 */
Jiang Liu7c919772014-01-06 14:18:18 +0800777 for_each_iommu(iommu, drhd) {
Joerg Roedel571dbbd2015-06-12 15:15:34 +0200778 if (!ir_pre_enabled(iommu))
779 iommu_enable_irq_remapping(iommu);
Quentin Lambert2f119c72015-02-06 10:59:53 +0100780 setup = true;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700781 }
782
783 if (!setup)
784 goto error;
785
Suresh Siddha95a02e92012-03-30 11:47:07 -0700786 irq_remapping_enabled = 1;
Joerg Roedelafcc8a42012-09-26 12:44:36 +0200787
Feng Wu3d9b98f2015-06-09 13:20:35 +0800788 set_irq_posting_cap();
789
Joerg Roedel23256d02015-06-12 14:15:49 +0200790 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
Suresh Siddha2ae21012008-07-10 11:16:43 -0700791
Joerg Roedel23256d02015-06-12 14:15:49 +0200792 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700793
794error:
Thomas Gleixner11190302015-01-07 15:31:29 +0800795 intel_cleanup_irq_remapping();
Suresh Siddha2ae21012008-07-10 11:16:43 -0700796 return -1;
797}
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700798
Jiang Liua7a3dad2014-11-09 22:48:00 +0800799static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
800 struct intel_iommu *iommu,
801 struct acpi_dmar_hardware_unit *drhd)
Suresh Siddha20f30972009-08-04 12:07:08 -0700802{
803 struct acpi_dmar_pci_path *path;
804 u8 bus;
Jiang Liua7a3dad2014-11-09 22:48:00 +0800805 int count, free = -1;
Suresh Siddha20f30972009-08-04 12:07:08 -0700806
807 bus = scope->bus;
808 path = (struct acpi_dmar_pci_path *)(scope + 1);
809 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
810 / sizeof(struct acpi_dmar_pci_path);
811
812 while (--count > 0) {
813 /*
814 * Access PCI directly due to the PCI
815 * subsystem isn't initialized yet.
816 */
Lv Zhengfa5f5082013-10-31 09:30:22 +0800817 bus = read_pci_config_byte(bus, path->device, path->function,
Suresh Siddha20f30972009-08-04 12:07:08 -0700818 PCI_SECONDARY_BUS);
819 path++;
820 }
Jiang Liua7a3dad2014-11-09 22:48:00 +0800821
822 for (count = 0; count < MAX_HPET_TBS; count++) {
823 if (ir_hpet[count].iommu == iommu &&
824 ir_hpet[count].id == scope->enumeration_id)
825 return 0;
826 else if (ir_hpet[count].iommu == NULL && free == -1)
827 free = count;
828 }
829 if (free == -1) {
830 pr_warn("Exceeded Max HPET blocks\n");
831 return -ENOSPC;
832 }
833
834 ir_hpet[free].iommu = iommu;
835 ir_hpet[free].id = scope->enumeration_id;
836 ir_hpet[free].bus = bus;
837 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
838 pr_info("HPET id %d under DRHD base 0x%Lx\n",
839 scope->enumeration_id, drhd->address);
840
841 return 0;
Suresh Siddha20f30972009-08-04 12:07:08 -0700842}
843
Jiang Liua7a3dad2014-11-09 22:48:00 +0800844static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
845 struct intel_iommu *iommu,
846 struct acpi_dmar_hardware_unit *drhd)
Weidong Hanf007e992009-05-23 00:41:15 +0800847{
848 struct acpi_dmar_pci_path *path;
849 u8 bus;
Jiang Liua7a3dad2014-11-09 22:48:00 +0800850 int count, free = -1;
Weidong Hanf007e992009-05-23 00:41:15 +0800851
852 bus = scope->bus;
853 path = (struct acpi_dmar_pci_path *)(scope + 1);
854 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
855 / sizeof(struct acpi_dmar_pci_path);
856
857 while (--count > 0) {
858 /*
859 * Access PCI directly due to the PCI
860 * subsystem isn't initialized yet.
861 */
Lv Zhengfa5f5082013-10-31 09:30:22 +0800862 bus = read_pci_config_byte(bus, path->device, path->function,
Weidong Hanf007e992009-05-23 00:41:15 +0800863 PCI_SECONDARY_BUS);
864 path++;
865 }
866
Jiang Liua7a3dad2014-11-09 22:48:00 +0800867 for (count = 0; count < MAX_IO_APICS; count++) {
868 if (ir_ioapic[count].iommu == iommu &&
869 ir_ioapic[count].id == scope->enumeration_id)
870 return 0;
871 else if (ir_ioapic[count].iommu == NULL && free == -1)
872 free = count;
873 }
874 if (free == -1) {
875 pr_warn("Exceeded Max IO APICS\n");
876 return -ENOSPC;
877 }
878
879 ir_ioapic[free].bus = bus;
880 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
881 ir_ioapic[free].iommu = iommu;
882 ir_ioapic[free].id = scope->enumeration_id;
883 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
884 scope->enumeration_id, drhd->address, iommu->seq_id);
885
886 return 0;
Weidong Hanf007e992009-05-23 00:41:15 +0800887}
888
Suresh Siddha20f30972009-08-04 12:07:08 -0700889static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
890 struct intel_iommu *iommu)
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700891{
Jiang Liua7a3dad2014-11-09 22:48:00 +0800892 int ret = 0;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700893 struct acpi_dmar_hardware_unit *drhd;
894 struct acpi_dmar_device_scope *scope;
895 void *start, *end;
896
897 drhd = (struct acpi_dmar_hardware_unit *)header;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700898 start = (void *)(drhd + 1);
899 end = ((void *)drhd) + header->length;
900
Jiang Liua7a3dad2014-11-09 22:48:00 +0800901 while (start < end && ret == 0) {
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700902 scope = start;
Jiang Liua7a3dad2014-11-09 22:48:00 +0800903 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
904 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
905 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
906 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700907 start += scope->length;
908 }
909
Jiang Liua7a3dad2014-11-09 22:48:00 +0800910 return ret;
911}
912
913static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
914{
915 int i;
916
917 for (i = 0; i < MAX_HPET_TBS; i++)
918 if (ir_hpet[i].iommu == iommu)
919 ir_hpet[i].iommu = NULL;
920
921 for (i = 0; i < MAX_IO_APICS; i++)
922 if (ir_ioapic[i].iommu == iommu)
923 ir_ioapic[i].iommu = NULL;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700924}
925
926/*
927 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
928 * hardware unit.
929 */
Jiang Liu694835d2014-01-06 14:18:16 +0800930static int __init parse_ioapics_under_ir(void)
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700931{
932 struct dmar_drhd_unit *drhd;
Jiang Liu7c919772014-01-06 14:18:18 +0800933 struct intel_iommu *iommu;
Quentin Lambert2f119c72015-02-06 10:59:53 +0100934 bool ir_supported = false;
Seth Forshee32ab31e2012-08-08 08:27:03 -0500935 int ioapic_idx;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700936
Joerg Roedel66ef9502015-10-23 11:57:13 +0200937 for_each_iommu(iommu, drhd) {
938 int ret;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700939
Joerg Roedel66ef9502015-10-23 11:57:13 +0200940 if (!ecap_ir_support(iommu->ecap))
941 continue;
942
943 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
944 if (ret)
945 return ret;
946
947 ir_supported = true;
948 }
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700949
Seth Forshee32ab31e2012-08-08 08:27:03 -0500950 if (!ir_supported)
Baoquan Hea13c8f22015-10-22 14:00:51 +0800951 return -ENODEV;
Seth Forshee32ab31e2012-08-08 08:27:03 -0500952
953 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
954 int ioapic_id = mpc_ioapic_id(ioapic_idx);
955 if (!map_ioapic_to_ir(ioapic_id)) {
956 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
957 "interrupt remapping will be disabled\n",
958 ioapic_id);
959 return -1;
960 }
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700961 }
962
Baoquan Hea13c8f22015-10-22 14:00:51 +0800963 return 0;
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700964}
Fenghua Yub24696b2009-03-27 14:22:44 -0700965
Rashika Kheria6a7885c2013-12-18 12:04:27 +0530966static int __init ir_dev_scope_init(void)
Suresh Siddhac2c72862011-08-23 17:05:19 -0700967{
Jiang Liu3a5670e2014-02-19 14:07:33 +0800968 int ret;
969
Suresh Siddha95a02e92012-03-30 11:47:07 -0700970 if (!irq_remapping_enabled)
Suresh Siddhac2c72862011-08-23 17:05:19 -0700971 return 0;
972
Jiang Liu3a5670e2014-02-19 14:07:33 +0800973 down_write(&dmar_global_lock);
974 ret = dmar_dev_scope_init();
975 up_write(&dmar_global_lock);
976
977 return ret;
Suresh Siddhac2c72862011-08-23 17:05:19 -0700978}
979rootfs_initcall(ir_dev_scope_init);
980
Suresh Siddha95a02e92012-03-30 11:47:07 -0700981static void disable_irq_remapping(void)
Fenghua Yub24696b2009-03-27 14:22:44 -0700982{
983 struct dmar_drhd_unit *drhd;
984 struct intel_iommu *iommu = NULL;
985
986 /*
987 * Disable Interrupt-remapping for all the DRHD's now.
988 */
989 for_each_iommu(iommu, drhd) {
990 if (!ecap_ir_support(iommu->ecap))
991 continue;
992
Suresh Siddha95a02e92012-03-30 11:47:07 -0700993 iommu_disable_irq_remapping(iommu);
Fenghua Yub24696b2009-03-27 14:22:44 -0700994 }
Feng Wu3d9b98f2015-06-09 13:20:35 +0800995
996 /*
997 * Clear Posted-Interrupts capability.
998 */
999 if (!disable_irq_post)
1000 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
Fenghua Yub24696b2009-03-27 14:22:44 -07001001}
1002
Suresh Siddha95a02e92012-03-30 11:47:07 -07001003static int reenable_irq_remapping(int eim)
Fenghua Yub24696b2009-03-27 14:22:44 -07001004{
1005 struct dmar_drhd_unit *drhd;
Quentin Lambert2f119c72015-02-06 10:59:53 +01001006 bool setup = false;
Fenghua Yub24696b2009-03-27 14:22:44 -07001007 struct intel_iommu *iommu = NULL;
1008
1009 for_each_iommu(iommu, drhd)
1010 if (iommu->qi)
1011 dmar_reenable_qi(iommu);
1012
1013 /*
1014 * Setup Interrupt-remapping for all the DRHD's now.
1015 */
1016 for_each_iommu(iommu, drhd) {
1017 if (!ecap_ir_support(iommu->ecap))
1018 continue;
1019
1020 /* Set up interrupt remapping for iommu.*/
Suresh Siddha95a02e92012-03-30 11:47:07 -07001021 iommu_set_irq_remapping(iommu, eim);
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +02001022 iommu_enable_irq_remapping(iommu);
Quentin Lambert2f119c72015-02-06 10:59:53 +01001023 setup = true;
Fenghua Yub24696b2009-03-27 14:22:44 -07001024 }
1025
1026 if (!setup)
1027 goto error;
1028
Feng Wu3d9b98f2015-06-09 13:20:35 +08001029 set_irq_posting_cap();
1030
Fenghua Yub24696b2009-03-27 14:22:44 -07001031 return 0;
1032
1033error:
1034 /*
1035 * handle error condition gracefully here!
1036 */
1037 return -1;
1038}
1039
Jiang Liu3c6e5672015-04-14 10:29:47 +08001040static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
Joerg Roedel0c3f1732012-03-30 11:47:02 -07001041{
1042 memset(irte, 0, sizeof(*irte));
1043
1044 irte->present = 1;
1045 irte->dst_mode = apic->irq_dest_mode;
1046 /*
1047 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1048 * actual level or edge trigger will be setup in the IO-APIC
1049 * RTE. This will help simplify level triggered irq migration.
1050 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1051 * irq migration in the presence of interrupt-remapping.
1052 */
1053 irte->trigger_mode = 0;
1054 irte->dlvry_mode = apic->irq_delivery_mode;
1055 irte->vector = vector;
1056 irte->dest_id = IRTE_DEST(dest);
1057 irte->redir_hint = 1;
1058}
1059
Jiang Liub106ee62015-04-13 14:11:32 +08001060static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1061{
1062 struct intel_iommu *iommu = NULL;
1063
1064 if (!info)
1065 return NULL;
1066
1067 switch (info->type) {
1068 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1069 iommu = map_ioapic_to_ir(info->ioapic_id);
1070 break;
1071 case X86_IRQ_ALLOC_TYPE_HPET:
1072 iommu = map_hpet_to_ir(info->hpet_id);
1073 break;
1074 case X86_IRQ_ALLOC_TYPE_MSI:
1075 case X86_IRQ_ALLOC_TYPE_MSIX:
1076 iommu = map_dev_to_ir(info->msi_dev);
1077 break;
1078 default:
1079 BUG_ON(1);
1080 break;
1081 }
1082
1083 return iommu ? iommu->ir_domain : NULL;
1084}
1085
1086static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1087{
1088 struct intel_iommu *iommu;
1089
1090 if (!info)
1091 return NULL;
1092
1093 switch (info->type) {
1094 case X86_IRQ_ALLOC_TYPE_MSI:
1095 case X86_IRQ_ALLOC_TYPE_MSIX:
1096 iommu = map_dev_to_ir(info->msi_dev);
1097 if (iommu)
1098 return iommu->ir_msi_domain;
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 return NULL;
1105}
1106
Joerg Roedel736baef2012-03-30 11:47:00 -07001107struct irq_remap_ops intel_irq_remap_ops = {
Thomas Gleixner11190302015-01-07 15:31:29 +08001108 .prepare = intel_prepare_irq_remapping,
Suresh Siddha95a02e92012-03-30 11:47:07 -07001109 .enable = intel_enable_irq_remapping,
1110 .disable = disable_irq_remapping,
1111 .reenable = reenable_irq_remapping,
Joerg Roedel4f3d8b62012-03-30 11:47:01 -07001112 .enable_faulting = enable_drhd_fault_handling,
Jiang Liub106ee62015-04-13 14:11:32 +08001113 .get_ir_irq_domain = intel_get_ir_irq_domain,
1114 .get_irq_domain = intel_get_irq_domain,
1115};
1116
1117/*
1118 * Migrate the IO-APIC irq in the presence of intr-remapping.
1119 *
1120 * For both level and edge triggered, irq migration is a simple atomic
1121 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1122 *
1123 * For level triggered, we eliminate the io-apic RTE modification (with the
1124 * updated vector information), by using a virtual vector (io-apic pin number).
1125 * Real vector that is used for interrupting cpu will be coming from
1126 * the interrupt-remapping table entry.
1127 *
1128 * As the migration is a simple atomic update of IRTE, the same mechanism
1129 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1130 */
1131static int
1132intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1133 bool force)
1134{
1135 struct intel_ir_data *ir_data = data->chip_data;
1136 struct irte *irte = &ir_data->irte_entry;
1137 struct irq_cfg *cfg = irqd_cfg(data);
1138 struct irq_data *parent = data->parent_data;
1139 int ret;
1140
1141 ret = parent->chip->irq_set_affinity(parent, mask, force);
1142 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1143 return ret;
1144
1145 /*
1146 * Atomically updates the IRTE with the new destination, vector
1147 * and flushes the interrupt entry cache.
1148 */
1149 irte->vector = cfg->vector;
1150 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
Feng Wud75f1522015-06-09 13:20:33 +08001151
1152 /* Update the hardware only if the interrupt is in remapped mode. */
1153 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1154 modify_irte(&ir_data->irq_2_iommu, irte);
Jiang Liub106ee62015-04-13 14:11:32 +08001155
1156 /*
1157 * After this point, all the interrupts will start arriving
1158 * at the new destination. So, time to cleanup the previous
1159 * vector allocation.
1160 */
Jiang Liuc6c20022015-04-14 10:30:02 +08001161 send_cleanup_vector(cfg);
Jiang Liub106ee62015-04-13 14:11:32 +08001162
1163 return IRQ_SET_MASK_OK_DONE;
1164}
1165
1166static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1167 struct msi_msg *msg)
1168{
1169 struct intel_ir_data *ir_data = irq_data->chip_data;
1170
1171 *msg = ir_data->msi_entry;
1172}
1173
Feng Wu85411862015-06-09 13:20:31 +08001174static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1175{
1176 struct intel_ir_data *ir_data = data->chip_data;
1177 struct vcpu_data *vcpu_pi_info = info;
1178
1179 /* stop posting interrupts, back to remapping mode */
1180 if (!vcpu_pi_info) {
1181 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1182 } else {
1183 struct irte irte_pi;
1184
1185 /*
1186 * We are not caching the posted interrupt entry. We
1187 * copy the data from the remapped entry and modify
1188 * the fields which are relevant for posted mode. The
1189 * cached remapped entry is used for switching back to
1190 * remapped mode.
1191 */
1192 memset(&irte_pi, 0, sizeof(irte_pi));
1193 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1194
1195 /* Update the posted mode fields */
1196 irte_pi.p_pst = 1;
1197 irte_pi.p_urgent = 0;
1198 irte_pi.p_vector = vcpu_pi_info->vector;
1199 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1200 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1201 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1202 ~(-1UL << PDA_HIGH_BIT);
1203
1204 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1205 }
1206
1207 return 0;
1208}
1209
Jiang Liub106ee62015-04-13 14:11:32 +08001210static struct irq_chip intel_ir_chip = {
1211 .irq_ack = ir_ack_apic_edge,
1212 .irq_set_affinity = intel_ir_set_affinity,
1213 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
Feng Wu85411862015-06-09 13:20:31 +08001214 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
Jiang Liub106ee62015-04-13 14:11:32 +08001215};
1216
1217static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1218 struct irq_cfg *irq_cfg,
1219 struct irq_alloc_info *info,
1220 int index, int sub_handle)
1221{
1222 struct IR_IO_APIC_route_entry *entry;
1223 struct irte *irte = &data->irte_entry;
1224 struct msi_msg *msg = &data->msi_entry;
1225
1226 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1227 switch (info->type) {
1228 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1229 /* Set source-id of interrupt request */
1230 set_ioapic_sid(irte, info->ioapic_id);
1231 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1232 info->ioapic_id, irte->present, irte->fpd,
1233 irte->dst_mode, irte->redir_hint,
1234 irte->trigger_mode, irte->dlvry_mode,
1235 irte->avail, irte->vector, irte->dest_id,
1236 irte->sid, irte->sq, irte->svt);
1237
1238 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1239 info->ioapic_entry = NULL;
1240 memset(entry, 0, sizeof(*entry));
1241 entry->index2 = (index >> 15) & 0x1;
1242 entry->zero = 0;
1243 entry->format = 1;
1244 entry->index = (index & 0x7fff);
1245 /*
1246 * IO-APIC RTE will be configured with virtual vector.
1247 * irq handler will do the explicit EOI to the io-apic.
1248 */
1249 entry->vector = info->ioapic_pin;
1250 entry->mask = 0; /* enable IRQ */
1251 entry->trigger = info->ioapic_trigger;
1252 entry->polarity = info->ioapic_polarity;
1253 if (info->ioapic_trigger)
1254 entry->mask = 1; /* Mask level triggered irqs. */
1255 break;
1256
1257 case X86_IRQ_ALLOC_TYPE_HPET:
1258 case X86_IRQ_ALLOC_TYPE_MSI:
1259 case X86_IRQ_ALLOC_TYPE_MSIX:
1260 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1261 set_hpet_sid(irte, info->hpet_id);
1262 else
1263 set_msi_sid(irte, info->msi_dev);
1264
1265 msg->address_hi = MSI_ADDR_BASE_HI;
1266 msg->data = sub_handle;
1267 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1268 MSI_ADDR_IR_SHV |
1269 MSI_ADDR_IR_INDEX1(index) |
1270 MSI_ADDR_IR_INDEX2(index);
1271 break;
1272
1273 default:
1274 BUG_ON(1);
1275 break;
1276 }
1277}
1278
1279static void intel_free_irq_resources(struct irq_domain *domain,
1280 unsigned int virq, unsigned int nr_irqs)
1281{
1282 struct irq_data *irq_data;
1283 struct intel_ir_data *data;
1284 struct irq_2_iommu *irq_iommu;
1285 unsigned long flags;
1286 int i;
Jiang Liub106ee62015-04-13 14:11:32 +08001287 for (i = 0; i < nr_irqs; i++) {
1288 irq_data = irq_domain_get_irq_data(domain, virq + i);
1289 if (irq_data && irq_data->chip_data) {
1290 data = irq_data->chip_data;
1291 irq_iommu = &data->irq_2_iommu;
1292 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1293 clear_entries(irq_iommu);
1294 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1295 irq_domain_reset_irq_data(irq_data);
1296 kfree(data);
1297 }
1298 }
1299}
1300
1301static int intel_irq_remapping_alloc(struct irq_domain *domain,
1302 unsigned int virq, unsigned int nr_irqs,
1303 void *arg)
1304{
1305 struct intel_iommu *iommu = domain->host_data;
1306 struct irq_alloc_info *info = arg;
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001307 struct intel_ir_data *data, *ird;
Jiang Liub106ee62015-04-13 14:11:32 +08001308 struct irq_data *irq_data;
1309 struct irq_cfg *irq_cfg;
1310 int i, ret, index;
1311
1312 if (!info || !iommu)
1313 return -EINVAL;
1314 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1315 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1316 return -EINVAL;
1317
1318 /*
1319 * With IRQ remapping enabled, don't need contiguous CPU vectors
1320 * to support multiple MSI interrupts.
1321 */
1322 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1323 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1324
1325 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1326 if (ret < 0)
1327 return ret;
1328
1329 ret = -ENOMEM;
1330 data = kzalloc(sizeof(*data), GFP_KERNEL);
1331 if (!data)
1332 goto out_free_parent;
1333
1334 down_read(&dmar_global_lock);
1335 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1336 up_read(&dmar_global_lock);
1337 if (index < 0) {
1338 pr_warn("Failed to allocate IRTE\n");
1339 kfree(data);
1340 goto out_free_parent;
1341 }
1342
1343 for (i = 0; i < nr_irqs; i++) {
1344 irq_data = irq_domain_get_irq_data(domain, virq + i);
1345 irq_cfg = irqd_cfg(irq_data);
1346 if (!irq_data || !irq_cfg) {
1347 ret = -EINVAL;
1348 goto out_free_data;
1349 }
1350
1351 if (i > 0) {
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001352 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1353 if (!ird)
Jiang Liub106ee62015-04-13 14:11:32 +08001354 goto out_free_data;
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001355 /* Initialize the common data */
1356 ird->irq_2_iommu = data->irq_2_iommu;
1357 ird->irq_2_iommu.sub_handle = i;
1358 } else {
1359 ird = data;
Jiang Liub106ee62015-04-13 14:11:32 +08001360 }
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001361
Jiang Liub106ee62015-04-13 14:11:32 +08001362 irq_data->hwirq = (index << 16) + i;
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001363 irq_data->chip_data = ird;
Jiang Liub106ee62015-04-13 14:11:32 +08001364 irq_data->chip = &intel_ir_chip;
Thomas Gleixner9d4c0312015-05-04 10:47:40 +08001365 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
Jiang Liub106ee62015-04-13 14:11:32 +08001366 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1367 }
1368 return 0;
1369
1370out_free_data:
1371 intel_free_irq_resources(domain, virq, i);
1372out_free_parent:
1373 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1374 return ret;
1375}
1376
1377static void intel_irq_remapping_free(struct irq_domain *domain,
1378 unsigned int virq, unsigned int nr_irqs)
1379{
1380 intel_free_irq_resources(domain, virq, nr_irqs);
1381 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1382}
1383
1384static void intel_irq_remapping_activate(struct irq_domain *domain,
1385 struct irq_data *irq_data)
1386{
1387 struct intel_ir_data *data = irq_data->chip_data;
1388
1389 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1390}
1391
1392static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1393 struct irq_data *irq_data)
1394{
1395 struct intel_ir_data *data = irq_data->chip_data;
1396 struct irte entry;
1397
1398 memset(&entry, 0, sizeof(entry));
1399 modify_irte(&data->irq_2_iommu, &entry);
1400}
1401
1402static struct irq_domain_ops intel_ir_domain_ops = {
1403 .alloc = intel_irq_remapping_alloc,
1404 .free = intel_irq_remapping_free,
1405 .activate = intel_irq_remapping_activate,
1406 .deactivate = intel_irq_remapping_deactivate,
Joerg Roedel736baef2012-03-30 11:47:00 -07001407};
Jiang Liu6b197242014-11-09 22:47:58 +08001408
Jiang Liua7a3dad2014-11-09 22:48:00 +08001409/*
1410 * Support of Interrupt Remapping Unit Hotplug
1411 */
1412static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1413{
1414 int ret;
1415 int eim = x2apic_enabled();
1416
1417 if (eim && !ecap_eim_support(iommu->ecap)) {
1418 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1419 iommu->reg_phys, iommu->ecap);
1420 return -ENODEV;
1421 }
1422
1423 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1424 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1425 iommu->reg_phys);
1426 return -ENODEV;
1427 }
1428
1429 /* TODO: check all IOAPICs are covered by IOMMU */
1430
1431 /* Setup Interrupt-remapping now. */
1432 ret = intel_setup_irq_remapping(iommu);
1433 if (ret) {
Joerg Roedel9e4e49d2015-06-12 14:23:56 +02001434 pr_err("Failed to setup irq remapping for %s\n",
1435 iommu->name);
Jiang Liua7a3dad2014-11-09 22:48:00 +08001436 intel_teardown_irq_remapping(iommu);
1437 ir_remove_ioapic_hpet_scope(iommu);
Joerg Roedel9e4e49d2015-06-12 14:23:56 +02001438 } else {
Joerg Roedeld4d1c0f2015-06-12 14:35:54 +02001439 iommu_enable_irq_remapping(iommu);
Jiang Liua7a3dad2014-11-09 22:48:00 +08001440 }
1441
1442 return ret;
1443}
1444
Jiang Liu6b197242014-11-09 22:47:58 +08001445int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1446{
Jiang Liua7a3dad2014-11-09 22:48:00 +08001447 int ret = 0;
1448 struct intel_iommu *iommu = dmaru->iommu;
1449
1450 if (!irq_remapping_enabled)
1451 return 0;
1452 if (iommu == NULL)
1453 return -EINVAL;
1454 if (!ecap_ir_support(iommu->ecap))
1455 return 0;
Feng Wuc1d99332015-06-09 13:20:37 +08001456 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1457 !cap_pi_support(iommu->cap))
1458 return -EBUSY;
Jiang Liua7a3dad2014-11-09 22:48:00 +08001459
1460 if (insert) {
1461 if (!iommu->ir_table)
1462 ret = dmar_ir_add(dmaru, iommu);
1463 } else {
1464 if (iommu->ir_table) {
1465 if (!bitmap_empty(iommu->ir_table->bitmap,
1466 INTR_REMAP_TABLE_ENTRIES)) {
1467 ret = -EBUSY;
1468 } else {
1469 iommu_disable_irq_remapping(iommu);
1470 intel_teardown_irq_remapping(iommu);
1471 ir_remove_ioapic_hpet_scope(iommu);
1472 }
1473 }
1474 }
1475
1476 return ret;
Jiang Liu6b197242014-11-09 22:47:58 +08001477}