Yinghai Lu | 5aeecaf | 2008-08-19 20:49:59 -0700 | [diff] [blame] | 1 | #include <linux/interrupt.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 2 | #include <linux/dmar.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3 | #include <linux/spinlock.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 4 | #include <linux/slab.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 5 | #include <linux/jiffies.h> |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 6 | #include <linux/hpet.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 7 | #include <linux/pci.h> |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 8 | #include <linux/irq.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 9 | #include <asm/io_apic.h> |
Yinghai Lu | 17483a1 | 2008-12-12 13:14:18 -0800 | [diff] [blame] | 10 | #include <asm/smp.h> |
Jaswinder Singh Rajput | 6d652ea | 2009-01-07 21:38:59 +0530 | [diff] [blame] | 11 | #include <asm/cpu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 12 | #include <linux/intel-iommu.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 13 | #include "intr_remapping.h" |
Alexander Beregalov | 46f06b72 | 2009-04-06 16:45:28 +0100 | [diff] [blame] | 14 | #include <acpi/acpi.h> |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 15 | #include <asm/pci-direct.h> |
| 16 | #include "pci.h" |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 17 | |
| 18 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 19 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
| 20 | static int ir_ioapic_num, ir_hpet_num; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 21 | int intr_remapping_enabled; |
| 22 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 23 | static int disable_intremap; |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 24 | static int disable_sourceid_checking; |
| 25 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 26 | static __init int setup_nointremap(char *str) |
| 27 | { |
| 28 | disable_intremap = 1; |
| 29 | return 0; |
| 30 | } |
| 31 | early_param("nointremap", setup_nointremap); |
| 32 | |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 33 | static __init int setup_intremap(char *str) |
| 34 | { |
| 35 | if (!str) |
| 36 | return -EINVAL; |
| 37 | |
| 38 | if (!strncmp(str, "on", 2)) |
| 39 | disable_intremap = 0; |
| 40 | else if (!strncmp(str, "off", 3)) |
| 41 | disable_intremap = 1; |
| 42 | else if (!strncmp(str, "nosid", 5)) |
| 43 | disable_sourceid_checking = 1; |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | early_param("intremap", setup_intremap); |
| 48 | |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 49 | static DEFINE_SPINLOCK(irq_2_ir_lock); |
| 50 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 51 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
| 52 | { |
Thomas Gleixner | 349d676 | 2010-10-10 12:29:27 +0200 | [diff] [blame] | 53 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
| 54 | return cfg ? &cfg->irq_2_iommu : NULL; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 55 | } |
| 56 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 57 | int irq_remapped(int irq) |
| 58 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 59 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 60 | |
| 61 | return irq_iommu ? irq_iommu->iommu != NULL : 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | int get_irte(int irq, struct irte *entry) |
| 65 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 66 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 67 | unsigned long flags; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 68 | int index; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 69 | |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 70 | if (!entry || !irq_iommu) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 71 | return -1; |
| 72 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 73 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 74 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 75 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 76 | *entry = *(irq_iommu->iommu->ir_table->base + index); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 77 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 78 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
| 83 | { |
| 84 | struct ir_table *table = iommu->ir_table; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 85 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 86 | u16 index, start_index; |
| 87 | unsigned int mask = 0; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 88 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 89 | int i; |
| 90 | |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 91 | if (!count || !irq_iommu) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 92 | return -1; |
| 93 | |
| 94 | /* |
| 95 | * start the IRTE search from index 0. |
| 96 | */ |
| 97 | index = start_index = 0; |
| 98 | |
| 99 | if (count > 1) { |
| 100 | count = __roundup_pow_of_two(count); |
| 101 | mask = ilog2(count); |
| 102 | } |
| 103 | |
| 104 | if (mask > ecap_max_handle_mask(iommu->ecap)) { |
| 105 | printk(KERN_ERR |
| 106 | "Requested mask %x exceeds the max invalidation handle" |
| 107 | " mask value %Lx\n", mask, |
| 108 | ecap_max_handle_mask(iommu->ecap)); |
| 109 | return -1; |
| 110 | } |
| 111 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 112 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 113 | do { |
| 114 | for (i = index; i < index + count; i++) |
| 115 | if (table->base[i].present) |
| 116 | break; |
| 117 | /* empty index found */ |
| 118 | if (i == index + count) |
| 119 | break; |
| 120 | |
| 121 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; |
| 122 | |
| 123 | if (index == start_index) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 124 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 125 | printk(KERN_ERR "can't allocate an IRTE\n"); |
| 126 | return -1; |
| 127 | } |
| 128 | } while (1); |
| 129 | |
| 130 | for (i = index; i < index + count; i++) |
| 131 | table->base[i].present = 1; |
| 132 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 133 | irq_iommu->iommu = iommu; |
| 134 | irq_iommu->irte_index = index; |
| 135 | irq_iommu->sub_handle = 0; |
| 136 | irq_iommu->irte_mask = mask; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 137 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 138 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 139 | |
| 140 | return index; |
| 141 | } |
| 142 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 143 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 144 | { |
| 145 | struct qi_desc desc; |
| 146 | |
| 147 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) |
| 148 | | QI_IEC_SELECTIVE; |
| 149 | desc.high = 0; |
| 150 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 151 | return qi_submit_sync(&desc, iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
| 155 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 156 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 157 | unsigned long flags; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 158 | int index; |
| 159 | |
| 160 | if (!irq_iommu) |
| 161 | return -1; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 162 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 163 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 164 | *sub_handle = irq_iommu->sub_handle; |
| 165 | index = irq_iommu->irte_index; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 166 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 167 | return index; |
| 168 | } |
| 169 | |
| 170 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
| 171 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 172 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 173 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 174 | |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 175 | if (!irq_iommu) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 176 | return -1; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 177 | |
| 178 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 179 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 180 | irq_iommu->iommu = iommu; |
| 181 | irq_iommu->irte_index = index; |
| 182 | irq_iommu->sub_handle = subhandle; |
| 183 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 184 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 185 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 190 | int modify_irte(int irq, struct irte *irte_modified) |
| 191 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 192 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 193 | struct intel_iommu *iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 194 | unsigned long flags; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 195 | struct irte *irte; |
| 196 | int rc, index; |
| 197 | |
| 198 | if (!irq_iommu) |
| 199 | return -1; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 200 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 201 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 202 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 203 | iommu = irq_iommu->iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 204 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 205 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 206 | irte = &iommu->ir_table->base[index]; |
| 207 | |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 208 | set_64bit(&irte->low, irte_modified->low); |
| 209 | set_64bit(&irte->high, irte_modified->high); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 210 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
| 211 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 212 | rc = qi_flush_iec(iommu, index, 0); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 213 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 214 | |
| 215 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 216 | } |
| 217 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 218 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
| 219 | { |
| 220 | int i; |
| 221 | |
| 222 | for (i = 0; i < MAX_HPET_TBS; i++) |
| 223 | if (ir_hpet[i].id == hpet_id) |
| 224 | return ir_hpet[i].iommu; |
| 225 | return NULL; |
| 226 | } |
| 227 | |
Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 228 | struct intel_iommu *map_ioapic_to_ir(int apic) |
| 229 | { |
| 230 | int i; |
| 231 | |
| 232 | for (i = 0; i < MAX_IO_APICS; i++) |
| 233 | if (ir_ioapic[i].id == apic) |
| 234 | return ir_ioapic[i].iommu; |
| 235 | return NULL; |
| 236 | } |
| 237 | |
Suresh Siddha | 75c46fa | 2008-07-10 11:16:57 -0700 | [diff] [blame] | 238 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
| 239 | { |
| 240 | struct dmar_drhd_unit *drhd; |
| 241 | |
| 242 | drhd = dmar_find_matched_drhd_unit(dev); |
| 243 | if (!drhd) |
| 244 | return NULL; |
| 245 | |
| 246 | return drhd->iommu; |
| 247 | } |
| 248 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 249 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
| 250 | { |
| 251 | struct irte *start, *entry, *end; |
| 252 | struct intel_iommu *iommu; |
| 253 | int index; |
| 254 | |
| 255 | if (irq_iommu->sub_handle) |
| 256 | return 0; |
| 257 | |
| 258 | iommu = irq_iommu->iommu; |
| 259 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 260 | |
| 261 | start = iommu->ir_table->base + index; |
| 262 | end = start + (1 << irq_iommu->irte_mask); |
| 263 | |
| 264 | for (entry = start; entry < end; entry++) { |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 265 | set_64bit(&entry->low, 0); |
| 266 | set_64bit(&entry->high, 0); |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
| 270 | } |
| 271 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 272 | int free_irte(int irq) |
| 273 | { |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 274 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 275 | unsigned long flags; |
Thomas Gleixner | d585d06 | 2010-10-10 12:34:27 +0200 | [diff] [blame^] | 276 | int rc; |
| 277 | |
| 278 | if (!irq_iommu) |
| 279 | return -1; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 280 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 281 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 282 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 283 | rc = clear_entries(irq_iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 284 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 285 | irq_iommu->iommu = NULL; |
| 286 | irq_iommu->irte_index = 0; |
| 287 | irq_iommu->sub_handle = 0; |
| 288 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 289 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 290 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 291 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 292 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 295 | /* |
| 296 | * source validation type |
| 297 | */ |
| 298 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ |
| 299 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */ |
| 300 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
| 301 | |
| 302 | /* |
| 303 | * source-id qualifier |
| 304 | */ |
| 305 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ |
| 306 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore |
| 307 | * the third least significant bit |
| 308 | */ |
| 309 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore |
| 310 | * the second and third least significant bits |
| 311 | */ |
| 312 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore |
| 313 | * the least three significant bits |
| 314 | */ |
| 315 | |
| 316 | /* |
| 317 | * set SVT, SQ and SID fields of irte to verify |
| 318 | * source ids of interrupt requests |
| 319 | */ |
| 320 | static void set_irte_sid(struct irte *irte, unsigned int svt, |
| 321 | unsigned int sq, unsigned int sid) |
| 322 | { |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 323 | if (disable_sourceid_checking) |
| 324 | svt = SVT_NO_VERIFY; |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 325 | irte->svt = svt; |
| 326 | irte->sq = sq; |
| 327 | irte->sid = sid; |
| 328 | } |
| 329 | |
| 330 | int set_ioapic_sid(struct irte *irte, int apic) |
| 331 | { |
| 332 | int i; |
| 333 | u16 sid = 0; |
| 334 | |
| 335 | if (!irte) |
| 336 | return -1; |
| 337 | |
| 338 | for (i = 0; i < MAX_IO_APICS; i++) { |
| 339 | if (ir_ioapic[i].id == apic) { |
| 340 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
| 341 | break; |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | if (sid == 0) { |
| 346 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); |
| 347 | return -1; |
| 348 | } |
| 349 | |
| 350 | set_irte_sid(irte, 1, 0, sid); |
| 351 | |
| 352 | return 0; |
| 353 | } |
| 354 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 355 | int set_hpet_sid(struct irte *irte, u8 id) |
| 356 | { |
| 357 | int i; |
| 358 | u16 sid = 0; |
| 359 | |
| 360 | if (!irte) |
| 361 | return -1; |
| 362 | |
| 363 | for (i = 0; i < MAX_HPET_TBS; i++) { |
| 364 | if (ir_hpet[i].id == id) { |
| 365 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
| 366 | break; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | if (sid == 0) { |
| 371 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); |
| 372 | return -1; |
| 373 | } |
| 374 | |
| 375 | /* |
| 376 | * Should really use SQ_ALL_16. Some platforms are broken. |
| 377 | * While we figure out the right quirks for these broken platforms, use |
| 378 | * SQ_13_IGNORE_3 for now. |
| 379 | */ |
| 380 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 385 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
| 386 | { |
| 387 | struct pci_dev *bridge; |
| 388 | |
| 389 | if (!irte || !dev) |
| 390 | return -1; |
| 391 | |
| 392 | /* PCIe device or Root Complex integrated PCI device */ |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 393 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 394 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 395 | (dev->bus->number << 8) | dev->devfn); |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | bridge = pci_find_upstream_pcie_bridge(dev); |
| 400 | if (bridge) { |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 401 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 402 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
| 403 | (bridge->bus->number << 8) | dev->bus->number); |
| 404 | else /* this is a legacy PCI bridge */ |
| 405 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 406 | (bridge->bus->number << 8) | bridge->devfn); |
| 407 | } |
| 408 | |
| 409 | return 0; |
| 410 | } |
| 411 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 412 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
| 413 | { |
| 414 | u64 addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 415 | u32 sts; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 416 | unsigned long flags; |
| 417 | |
| 418 | addr = virt_to_phys((void *)iommu->ir_table->base); |
| 419 | |
| 420 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 421 | |
| 422 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, |
| 423 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); |
| 424 | |
| 425 | /* Set interrupt-remapping table pointer */ |
Han, Weidong | 161fde0 | 2009-04-03 17:15:47 +0800 | [diff] [blame] | 426 | iommu->gcmd |= DMA_GCMD_SIRTP; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 427 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 428 | |
| 429 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 430 | readl, (sts & DMA_GSTS_IRTPS), sts); |
| 431 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 432 | |
| 433 | /* |
| 434 | * global invalidation of interrupt entry cache before enabling |
| 435 | * interrupt-remapping. |
| 436 | */ |
| 437 | qi_global_iec(iommu); |
| 438 | |
| 439 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 440 | |
| 441 | /* Enable interrupt-remapping */ |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 442 | iommu->gcmd |= DMA_GCMD_IRE; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 443 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 444 | |
| 445 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 446 | readl, (sts & DMA_GSTS_IRES), sts); |
| 447 | |
| 448 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 449 | } |
| 450 | |
| 451 | |
| 452 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) |
| 453 | { |
| 454 | struct ir_table *ir_table; |
| 455 | struct page *pages; |
| 456 | |
| 457 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), |
Suresh Siddha | fa4b57c | 2009-03-16 17:05:05 -0700 | [diff] [blame] | 458 | GFP_ATOMIC); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 459 | |
| 460 | if (!iommu->ir_table) |
| 461 | return -ENOMEM; |
| 462 | |
Suresh Siddha | 824cd75 | 2009-10-02 11:01:23 -0700 | [diff] [blame] | 463 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
| 464 | INTR_REMAP_PAGE_ORDER); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 465 | |
| 466 | if (!pages) { |
| 467 | printk(KERN_ERR "failed to allocate pages of order %d\n", |
| 468 | INTR_REMAP_PAGE_ORDER); |
| 469 | kfree(iommu->ir_table); |
| 470 | return -ENOMEM; |
| 471 | } |
| 472 | |
| 473 | ir_table->base = page_address(pages); |
| 474 | |
| 475 | iommu_set_intr_remapping(iommu, mode); |
| 476 | return 0; |
| 477 | } |
| 478 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 479 | /* |
| 480 | * Disable Interrupt Remapping. |
| 481 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 482 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 483 | { |
| 484 | unsigned long flags; |
| 485 | u32 sts; |
| 486 | |
| 487 | if (!ecap_ir_support(iommu->ecap)) |
| 488 | return; |
| 489 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 490 | /* |
| 491 | * global invalidation of interrupt entry cache before disabling |
| 492 | * interrupt-remapping. |
| 493 | */ |
| 494 | qi_global_iec(iommu); |
| 495 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 496 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 497 | |
| 498 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); |
| 499 | if (!(sts & DMA_GSTS_IRES)) |
| 500 | goto end; |
| 501 | |
| 502 | iommu->gcmd &= ~DMA_GCMD_IRE; |
| 503 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 504 | |
| 505 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 506 | readl, !(sts & DMA_GSTS_IRES), sts); |
| 507 | |
| 508 | end: |
| 509 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 510 | } |
| 511 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 512 | int __init intr_remapping_supported(void) |
| 513 | { |
| 514 | struct dmar_drhd_unit *drhd; |
| 515 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 516 | if (disable_intremap) |
| 517 | return 0; |
| 518 | |
Youquan Song | 074835f | 2009-09-09 12:05:39 -0400 | [diff] [blame] | 519 | if (!dmar_ir_support()) |
| 520 | return 0; |
| 521 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 522 | for_each_drhd_unit(drhd) { |
| 523 | struct intel_iommu *iommu = drhd->iommu; |
| 524 | |
| 525 | if (!ecap_ir_support(iommu->ecap)) |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | return 1; |
| 530 | } |
| 531 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 532 | int __init enable_intr_remapping(int eim) |
| 533 | { |
| 534 | struct dmar_drhd_unit *drhd; |
| 535 | int setup = 0; |
| 536 | |
Youquan Song | e936d07 | 2009-09-07 10:58:07 -0400 | [diff] [blame] | 537 | if (parse_ioapics_under_ir() != 1) { |
| 538 | printk(KERN_INFO "Not enable interrupt remapping\n"); |
| 539 | return -1; |
| 540 | } |
| 541 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 542 | for_each_drhd_unit(drhd) { |
| 543 | struct intel_iommu *iommu = drhd->iommu; |
| 544 | |
| 545 | /* |
Han, Weidong | 34aaaa9 | 2009-04-04 17:21:26 +0800 | [diff] [blame] | 546 | * If the queued invalidation is already initialized, |
| 547 | * shouldn't disable it. |
| 548 | */ |
| 549 | if (iommu->qi) |
| 550 | continue; |
| 551 | |
| 552 | /* |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 553 | * Clear previous faults. |
| 554 | */ |
| 555 | dmar_fault(-1, iommu); |
| 556 | |
| 557 | /* |
| 558 | * Disable intr remapping and queued invalidation, if already |
| 559 | * enabled prior to OS handover. |
| 560 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 561 | iommu_disable_intr_remapping(iommu); |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 562 | |
| 563 | dmar_disable_qi(iommu); |
| 564 | } |
| 565 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 566 | /* |
| 567 | * check for the Interrupt-remapping support |
| 568 | */ |
| 569 | for_each_drhd_unit(drhd) { |
| 570 | struct intel_iommu *iommu = drhd->iommu; |
| 571 | |
| 572 | if (!ecap_ir_support(iommu->ecap)) |
| 573 | continue; |
| 574 | |
| 575 | if (eim && !ecap_eim_support(iommu->ecap)) { |
| 576 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " |
| 577 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); |
| 578 | return -1; |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | /* |
| 583 | * Enable queued invalidation for all the DRHD's. |
| 584 | */ |
| 585 | for_each_drhd_unit(drhd) { |
| 586 | int ret; |
| 587 | struct intel_iommu *iommu = drhd->iommu; |
| 588 | ret = dmar_enable_qi(iommu); |
| 589 | |
| 590 | if (ret) { |
| 591 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " |
| 592 | " invalidation, ecap %Lx, ret %d\n", |
| 593 | drhd->reg_base_addr, iommu->ecap, ret); |
| 594 | return -1; |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | /* |
| 599 | * Setup Interrupt-remapping for all the DRHD's now. |
| 600 | */ |
| 601 | for_each_drhd_unit(drhd) { |
| 602 | struct intel_iommu *iommu = drhd->iommu; |
| 603 | |
| 604 | if (!ecap_ir_support(iommu->ecap)) |
| 605 | continue; |
| 606 | |
| 607 | if (setup_intr_remapping(iommu, eim)) |
| 608 | goto error; |
| 609 | |
| 610 | setup = 1; |
| 611 | } |
| 612 | |
| 613 | if (!setup) |
| 614 | goto error; |
| 615 | |
| 616 | intr_remapping_enabled = 1; |
| 617 | |
| 618 | return 0; |
| 619 | |
| 620 | error: |
| 621 | /* |
| 622 | * handle error condition gracefully here! |
| 623 | */ |
| 624 | return -1; |
| 625 | } |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 626 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 627 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
| 628 | struct intel_iommu *iommu) |
| 629 | { |
| 630 | struct acpi_dmar_pci_path *path; |
| 631 | u8 bus; |
| 632 | int count; |
| 633 | |
| 634 | bus = scope->bus; |
| 635 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 636 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 637 | / sizeof(struct acpi_dmar_pci_path); |
| 638 | |
| 639 | while (--count > 0) { |
| 640 | /* |
| 641 | * Access PCI directly due to the PCI |
| 642 | * subsystem isn't initialized yet. |
| 643 | */ |
| 644 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 645 | PCI_SECONDARY_BUS); |
| 646 | path++; |
| 647 | } |
| 648 | ir_hpet[ir_hpet_num].bus = bus; |
| 649 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 650 | ir_hpet[ir_hpet_num].iommu = iommu; |
| 651 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; |
| 652 | ir_hpet_num++; |
| 653 | } |
| 654 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 655 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
| 656 | struct intel_iommu *iommu) |
| 657 | { |
| 658 | struct acpi_dmar_pci_path *path; |
| 659 | u8 bus; |
| 660 | int count; |
| 661 | |
| 662 | bus = scope->bus; |
| 663 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 664 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 665 | / sizeof(struct acpi_dmar_pci_path); |
| 666 | |
| 667 | while (--count > 0) { |
| 668 | /* |
| 669 | * Access PCI directly due to the PCI |
| 670 | * subsystem isn't initialized yet. |
| 671 | */ |
| 672 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 673 | PCI_SECONDARY_BUS); |
| 674 | path++; |
| 675 | } |
| 676 | |
| 677 | ir_ioapic[ir_ioapic_num].bus = bus; |
| 678 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 679 | ir_ioapic[ir_ioapic_num].iommu = iommu; |
| 680 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; |
| 681 | ir_ioapic_num++; |
| 682 | } |
| 683 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 684 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
| 685 | struct intel_iommu *iommu) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 686 | { |
| 687 | struct acpi_dmar_hardware_unit *drhd; |
| 688 | struct acpi_dmar_device_scope *scope; |
| 689 | void *start, *end; |
| 690 | |
| 691 | drhd = (struct acpi_dmar_hardware_unit *)header; |
| 692 | |
| 693 | start = (void *)(drhd + 1); |
| 694 | end = ((void *)drhd) + header->length; |
| 695 | |
| 696 | while (start < end) { |
| 697 | scope = start; |
| 698 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { |
| 699 | if (ir_ioapic_num == MAX_IO_APICS) { |
| 700 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); |
| 701 | return -1; |
| 702 | } |
| 703 | |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 704 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
| 705 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, |
| 706 | drhd->address, iommu->seq_id); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 707 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 708 | ir_parse_one_ioapic_scope(scope, iommu); |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 709 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
| 710 | if (ir_hpet_num == MAX_HPET_TBS) { |
| 711 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); |
| 712 | return -1; |
| 713 | } |
| 714 | |
| 715 | printk(KERN_INFO "HPET id %d under DRHD base" |
| 716 | " 0x%Lx\n", scope->enumeration_id, |
| 717 | drhd->address); |
| 718 | |
| 719 | ir_parse_one_hpet_scope(scope, iommu); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 720 | } |
| 721 | start += scope->length; |
| 722 | } |
| 723 | |
| 724 | return 0; |
| 725 | } |
| 726 | |
| 727 | /* |
| 728 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping |
| 729 | * hardware unit. |
| 730 | */ |
| 731 | int __init parse_ioapics_under_ir(void) |
| 732 | { |
| 733 | struct dmar_drhd_unit *drhd; |
| 734 | int ir_supported = 0; |
| 735 | |
| 736 | for_each_drhd_unit(drhd) { |
| 737 | struct intel_iommu *iommu = drhd->iommu; |
| 738 | |
| 739 | if (ecap_ir_support(iommu->ecap)) { |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 740 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 741 | return -1; |
| 742 | |
| 743 | ir_supported = 1; |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | if (ir_supported && ir_ioapic_num != nr_ioapics) { |
| 748 | printk(KERN_WARNING |
| 749 | "Not all IO-APIC's listed under remapping hardware\n"); |
| 750 | return -1; |
| 751 | } |
| 752 | |
| 753 | return ir_supported; |
| 754 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 755 | |
| 756 | void disable_intr_remapping(void) |
| 757 | { |
| 758 | struct dmar_drhd_unit *drhd; |
| 759 | struct intel_iommu *iommu = NULL; |
| 760 | |
| 761 | /* |
| 762 | * Disable Interrupt-remapping for all the DRHD's now. |
| 763 | */ |
| 764 | for_each_iommu(iommu, drhd) { |
| 765 | if (!ecap_ir_support(iommu->ecap)) |
| 766 | continue; |
| 767 | |
| 768 | iommu_disable_intr_remapping(iommu); |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | int reenable_intr_remapping(int eim) |
| 773 | { |
| 774 | struct dmar_drhd_unit *drhd; |
| 775 | int setup = 0; |
| 776 | struct intel_iommu *iommu = NULL; |
| 777 | |
| 778 | for_each_iommu(iommu, drhd) |
| 779 | if (iommu->qi) |
| 780 | dmar_reenable_qi(iommu); |
| 781 | |
| 782 | /* |
| 783 | * Setup Interrupt-remapping for all the DRHD's now. |
| 784 | */ |
| 785 | for_each_iommu(iommu, drhd) { |
| 786 | if (!ecap_ir_support(iommu->ecap)) |
| 787 | continue; |
| 788 | |
| 789 | /* Set up interrupt remapping for iommu.*/ |
| 790 | iommu_set_intr_remapping(iommu, eim); |
| 791 | setup = 1; |
| 792 | } |
| 793 | |
| 794 | if (!setup) |
| 795 | goto error; |
| 796 | |
| 797 | return 0; |
| 798 | |
| 799 | error: |
| 800 | /* |
| 801 | * handle error condition gracefully here! |
| 802 | */ |
| 803 | return -1; |
| 804 | } |
| 805 | |