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Lennert Buytenhek2e16a772008-10-07 13:46:22 +00001/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
Lennert Buytenheke84665c2009-03-20 09:52:09 +00003 * Copyright (c) 2008-2009 Marvell Semiconductor
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#include <linux/list.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000012#include <linux/module.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000013#include <linux/netdevice.h>
14#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000015#include <net/dsa.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000016
17#define REG_PORT(p) (8 + (p))
18#define REG_GLOBAL 0x0f
19
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
Peter Korsgaardfdb838c2011-03-07 05:49:47 +000022 return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000023}
24
25#define REG_READ(addr, reg) \
26 ({ \
27 int __ret; \
28 \
29 __ret = reg_read(ds, addr, reg); \
30 if (__ret < 0) \
31 return __ret; \
32 __ret; \
33 })
34
35
36static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
37{
Peter Korsgaardfdb838c2011-03-07 05:49:47 +000038 return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
39 reg, val);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000040}
41
42#define REG_WRITE(addr, reg, val) \
43 ({ \
44 int __ret; \
45 \
46 __ret = reg_write(ds, addr, reg, val); \
47 if (__ret < 0) \
48 return __ret; \
49 })
50
51static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
52{
53 int ret;
54
Peter Korsgaardfdb838c2011-03-07 05:49:47 +000055 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000056 if (ret >= 0) {
57 ret &= 0xfff0;
58 if (ret == 0x0600)
59 return "Marvell 88E6060";
60 }
61
62 return NULL;
63}
64
65static int mv88e6060_switch_reset(struct dsa_switch *ds)
66{
67 int i;
68 int ret;
69
Barry Grussling3675c8d2013-01-08 16:05:53 +000070 /* Set all ports to the disabled state. */
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000071 for (i = 0; i < 6; i++) {
72 ret = REG_READ(REG_PORT(i), 0x04);
73 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
74 }
75
Barry Grussling3675c8d2013-01-08 16:05:53 +000076 /* Wait for transmit queues to drain. */
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000077 msleep(2);
78
Barry Grussling3675c8d2013-01-08 16:05:53 +000079 /* Reset the switch. */
Lennert Buytenheke84665c2009-03-20 09:52:09 +000080 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000081
Barry Grussling3675c8d2013-01-08 16:05:53 +000082 /* Wait up to one second for reset to complete. */
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000083 for (i = 0; i < 1000; i++) {
84 ret = REG_READ(REG_GLOBAL, 0x00);
85 if ((ret & 0x8000) == 0x0000)
86 break;
87
88 msleep(1);
89 }
90 if (i == 1000)
91 return -ETIMEDOUT;
92
93 return 0;
94}
95
96static int mv88e6060_setup_global(struct dsa_switch *ds)
97{
Barry Grussling3675c8d2013-01-08 16:05:53 +000098 /* Disable discarding of frames with excessive collisions,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000099 * set the maximum frame size to 1536 bytes, and mask all
100 * interrupt sources.
101 */
102 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
103
Barry Grussling3675c8d2013-01-08 16:05:53 +0000104 /* Enable automatic address learning, set the address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000105 * database size to 1024 entries, and set the default aging
106 * time to 5 minutes.
107 */
108 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
109
110 return 0;
111}
112
113static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
114{
115 int addr = REG_PORT(p);
116
Barry Grussling3675c8d2013-01-08 16:05:53 +0000117 /* Do not force flow control, disable Ingress and Egress
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000118 * Header tagging, disable VLAN tunneling, and set the port
119 * state to Forwarding. Additionally, if this is the CPU
120 * port, enable Ingress and Egress Trailer tagging mode.
121 */
Lennert Buytenheke84665c2009-03-20 09:52:09 +0000122 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000123
Barry Grussling3675c8d2013-01-08 16:05:53 +0000124 /* Port based VLAN map: give each port its own address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000125 * database, allow the CPU port to talk to each of the 'real'
126 * ports, and allow each of the 'real' ports to only talk to
127 * the CPU port.
128 */
129 REG_WRITE(addr, 0x06,
130 ((p & 0xf) << 12) |
Lennert Buytenheke84665c2009-03-20 09:52:09 +0000131 (dsa_is_cpu_port(ds, p) ?
132 ds->phys_port_mask :
133 (1 << ds->dst->cpu_port)));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000134
Barry Grussling3675c8d2013-01-08 16:05:53 +0000135 /* Port Association Vector: when learning source addresses
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000136 * of packets, add the address to the address database using
137 * a port bitmap that has only the bit for this port set and
138 * the other bits clear.
139 */
140 REG_WRITE(addr, 0x0b, 1 << p);
141
142 return 0;
143}
144
145static int mv88e6060_setup(struct dsa_switch *ds)
146{
147 int i;
148 int ret;
149
150 ret = mv88e6060_switch_reset(ds);
151 if (ret < 0)
152 return ret;
153
154 /* @@@ initialise atu */
155
156 ret = mv88e6060_setup_global(ds);
157 if (ret < 0)
158 return ret;
159
160 for (i = 0; i < 6; i++) {
161 ret = mv88e6060_setup_port(ds, i);
162 if (ret < 0)
163 return ret;
164 }
165
166 return 0;
167}
168
169static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
170{
171 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
172 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
173 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
174
175 return 0;
176}
177
178static int mv88e6060_port_to_phy_addr(int port)
179{
180 if (port >= 0 && port <= 5)
181 return port;
182 return -1;
183}
184
185static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
186{
187 int addr;
188
189 addr = mv88e6060_port_to_phy_addr(port);
190 if (addr == -1)
191 return 0xffff;
192
193 return reg_read(ds, addr, regnum);
194}
195
196static int
197mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
198{
199 int addr;
200
201 addr = mv88e6060_port_to_phy_addr(port);
202 if (addr == -1)
203 return 0xffff;
204
205 return reg_write(ds, addr, regnum, val);
206}
207
208static void mv88e6060_poll_link(struct dsa_switch *ds)
209{
210 int i;
211
212 for (i = 0; i < DSA_MAX_PORTS; i++) {
213 struct net_device *dev;
Ingo Molnard3f644d2008-11-25 16:51:13 -0800214 int uninitialized_var(port_status);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000215 int link;
216 int speed;
217 int duplex;
218 int fc;
219
220 dev = ds->ports[i];
221 if (dev == NULL)
222 continue;
223
224 link = 0;
225 if (dev->flags & IFF_UP) {
226 port_status = reg_read(ds, REG_PORT(i), 0x00);
227 if (port_status < 0)
228 continue;
229
230 link = !!(port_status & 0x1000);
231 }
232
233 if (!link) {
234 if (netif_carrier_ok(dev)) {
235 printk(KERN_INFO "%s: link down\n", dev->name);
236 netif_carrier_off(dev);
237 }
238 continue;
239 }
240
241 speed = (port_status & 0x0100) ? 100 : 10;
242 duplex = (port_status & 0x0200) ? 1 : 0;
243 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
244
245 if (!netif_carrier_ok(dev)) {
246 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
247 "flow control %sabled\n", dev->name,
248 speed, duplex ? "full" : "half",
249 fc ? "en" : "dis");
250 netif_carrier_on(dev);
251 }
252 }
253}
254
255static struct dsa_switch_driver mv88e6060_switch_driver = {
256 .tag_protocol = htons(ETH_P_TRAILER),
257 .probe = mv88e6060_probe,
258 .setup = mv88e6060_setup,
259 .set_addr = mv88e6060_set_addr,
260 .phy_read = mv88e6060_phy_read,
261 .phy_write = mv88e6060_phy_write,
262 .poll_link = mv88e6060_poll_link,
263};
264
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800265static int __init mv88e6060_init(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000266{
267 register_switch_driver(&mv88e6060_switch_driver);
268 return 0;
269}
270module_init(mv88e6060_init);
271
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800272static void __exit mv88e6060_cleanup(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000273{
274 unregister_switch_driver(&mv88e6060_switch_driver);
275}
276module_exit(mv88e6060_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +0000277
278MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
279MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
280MODULE_LICENSE("GPL");
281MODULE_ALIAS("platform:mv88e6060");