| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/include/mach/spear300.h |
| 3 | * |
| 4 | * SPEAr300 Machine specific definition |
| 5 | * |
| 6 | * Copyright (C) 2009 ST Microelectronics |
| 7 | * Viresh Kumar<viresh.kumar@st.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifdef CONFIG_MACH_SPEAR300 |
| 15 | |
| 16 | #ifndef __MACH_SPEAR300_H |
| 17 | #define __MACH_SPEAR300_H |
| 18 | |
| 19 | /* Base address of various IPs */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 20 | #define SPEAR300_TELECOM_BASE UL(0x50000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 21 | |
| viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 22 | /* Interrupt registers offsets and masks */ |
| Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 23 | #define SPEAR300_INT_ENB_MASK_REG 0x54 |
| 24 | #define SPEAR300_INT_STS_MASK_REG 0x58 |
| 25 | #define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) |
| 26 | #define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) |
| 27 | #define SPEAR300_I2S_IRQ_MASK (1 << 2) |
| 28 | #define SPEAR300_TDM_IRQ_MASK (1 << 3) |
| 29 | #define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) |
| 30 | #define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) |
| 31 | #define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) |
| 32 | #define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) |
| 33 | #define SPEAR300_GPIO1_IRQ_MASK (1 << 8) |
| viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 34 | |
| Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 35 | #define SPEAR300_SHIRQ_RAS1_MASK 0x1FF |
| viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 36 | |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 37 | #define SPEAR300_CLCD_BASE UL(0x60000000) |
| 38 | #define SPEAR300_SDHCI_BASE UL(0x70000000) |
| 39 | #define SPEAR300_NAND_0_BASE UL(0x80000000) |
| 40 | #define SPEAR300_NAND_1_BASE UL(0x84000000) |
| 41 | #define SPEAR300_NAND_2_BASE UL(0x88000000) |
| 42 | #define SPEAR300_NAND_3_BASE UL(0x8c000000) |
| 43 | #define SPEAR300_NOR_0_BASE UL(0x90000000) |
| 44 | #define SPEAR300_NOR_1_BASE UL(0x91000000) |
| 45 | #define SPEAR300_NOR_2_BASE UL(0x92000000) |
| 46 | #define SPEAR300_NOR_3_BASE UL(0x93000000) |
| 47 | #define SPEAR300_FSMC_BASE UL(0x94000000) |
| 48 | #define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) |
| 49 | #define SPEAR300_KEYBOARD_BASE UL(0xA0000000) |
| 50 | #define SPEAR300_GPIO_BASE UL(0xA9000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 51 | |
| 52 | #endif /* __MACH_SPEAR300_H */ |
| 53 | |
| 54 | #endif /* CONFIG_MACH_SPEAR300 */ |