Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | The following describes the current state of the NetWinder's floating point |
| 2 | emulator. |
| 3 | |
| 4 | In the following nomenclature is used to describe the floating point |
| 5 | instructions. It follows the conventions in the ARM manual. |
| 6 | |
| 7 | <S|D|E> = <single|double|extended>, no default |
| 8 | {P|M|Z} = {round to +infinity,round to -infinity,round to zero}, |
| 9 | default = round to nearest |
| 10 | |
| 11 | Note: items enclosed in {} are optional. |
| 12 | |
| 13 | Floating Point Coprocessor Data Transfer Instructions (CPDT) |
| 14 | ------------------------------------------------------------ |
| 15 | |
| 16 | LDF/STF - load and store floating |
| 17 | |
| 18 | <LDF|STF>{cond}<S|D|E> Fd, Rn |
| 19 | <LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!} |
| 20 | <LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression> |
| 21 | |
| 22 | These instructions are fully implemented. |
| 23 | |
| 24 | LFM/SFM - load and store multiple floating |
| 25 | |
| 26 | Form 1 syntax: |
| 27 | <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn] |
| 28 | <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!} |
| 29 | <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression> |
| 30 | |
| 31 | Form 2 syntax: |
| 32 | <LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!} |
| 33 | |
| 34 | These instructions are fully implemented. They store/load three words |
| 35 | for each floating point register into the memory location given in the |
| 36 | instruction. The format in memory is unlikely to be compatible with |
| 37 | other implementations, in particular the actual hardware. Specific |
| 38 | mention of this is made in the ARM manuals. |
| 39 | |
| 40 | Floating Point Coprocessor Register Transfer Instructions (CPRT) |
| 41 | ---------------------------------------------------------------- |
| 42 | |
| 43 | Conversions, read/write status/control register instructions |
| 44 | |
| 45 | FLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating point |
| 46 | FIX{cond}{P,M,Z} Rd, Fn Convert floating point to integer |
| 47 | WFS{cond} Rd Write floating point status register |
| 48 | RFS{cond} Rd Read floating point status register |
| 49 | WFC{cond} Rd Write floating point control register |
| 50 | RFC{cond} Rd Read floating point control register |
| 51 | |
| 52 | FLT/FIX are fully implemented. |
| 53 | |
| 54 | RFS/WFS are fully implemented. |
| 55 | |
| 56 | RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and |
| 57 | presently check the CPU mode, and do an invalid instruction trap if not called |
| 58 | from supervisor mode. |
| 59 | |
| 60 | Compare instructions |
| 61 | |
| 62 | CMF{cond} Fn, Fm Compare floating |
| 63 | CMFE{cond} Fn, Fm Compare floating with exception |
| 64 | CNF{cond} Fn, Fm Compare negated floating |
| 65 | CNFE{cond} Fn, Fm Compare negated floating with exception |
| 66 | |
| 67 | These are fully implemented. |
| 68 | |
| 69 | Floating Point Coprocessor Data Instructions (CPDT) |
| 70 | --------------------------------------------------- |
| 71 | |
| 72 | Dyadic operations: |
| 73 | |
| 74 | ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add |
| 75 | SUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtract |
| 76 | RSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtract |
| 77 | MUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiply |
| 78 | DVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divide |
| 79 | RDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divide |
| 80 | |
| 81 | These are fully implemented. |
| 82 | |
| 83 | FML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiply |
| 84 | FDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divide |
| 85 | FRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divide |
| 86 | |
| 87 | These are fully implemented as well. They use the same algorithm as the |
| 88 | non-fast versions. Hence, in this implementation their performance is |
| 89 | equivalent to the MUF/DVF/RDV instructions. This is acceptable according |
| 90 | to the ARM manual. The manual notes these are defined only for single |
| 91 | operands, on the actual FPA11 hardware they do not work for double or |
| 92 | extended precision operands. The emulator currently does not check |
| 93 | the requested permissions conditions, and performs the requested operation. |
| 94 | |
| 95 | RMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainder |
| 96 | |
| 97 | This is fully implemented. |
| 98 | |
| 99 | Monadic operations: |
| 100 | |
| 101 | MVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move |
| 102 | MNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negated |
| 103 | |
| 104 | These are fully implemented. |
| 105 | |
| 106 | ABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute value |
| 107 | SQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square root |
| 108 | RND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - round |
| 109 | |
| 110 | These are fully implemented. |
| 111 | |
| 112 | URD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized round |
| 113 | NRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalize |
| 114 | |
| 115 | These are implemented. URD is implemented using the same code as the RND |
| 116 | instruction. Since URD cannot return a unnormalized number, NRM becomes |
| 117 | a NOP. |
| 118 | |
| 119 | Library calls: |
| 120 | |
| 121 | POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power |
| 122 | RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power |
| 123 | POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2) |
| 124 | |
| 125 | LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10 |
| 126 | LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e |
| 127 | EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent |
| 128 | SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine |
| 129 | COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine |
| 130 | TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent |
| 131 | ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine |
| 132 | ACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine |
| 133 | ATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent |
| 134 | |
| 135 | These are not implemented. They are not currently issued by the compiler, |
| 136 | and are handled by routines in libc. These are not implemented by the FPA11 |
| 137 | hardware, but are handled by the floating point support code. They should |
| 138 | be implemented in future versions. |
| 139 | |
| 140 | Signalling: |
| 141 | |
| 142 | Signals are implemented. However current ELF kernels produced by Rebel.com |
| 143 | have a bug in them that prevents the module from generating a SIGFPE. This |
| 144 | is caused by a failure to alias fp_current to the kernel variable |
| 145 | current_set[0] correctly. |
| 146 | |
| 147 | The kernel provided with this distribution (vmlinux-nwfpe-0.93) contains |
| 148 | a fix for this problem and also incorporates the current version of the |
| 149 | emulator directly. It is possible to run with no floating point module |
| 150 | loaded with this kernel. It is provided as a demonstration of the |
| 151 | technology and for those who want to do floating point work that depends |
| 152 | on signals. It is not strictly necessary to use the module. |
| 153 | |
| 154 | A module (either the one provided by Russell King, or the one in this |
| 155 | distribution) can be loaded to replace the functionality of the emulator |
| 156 | built into the kernel. |