Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 1 | /* |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 2 | * Board setup routines for the Marvell EV-64360-BP Evaluation Board. |
| 3 | * |
| 4 | * Author: Lee Nicks <allinux@gmail.com> |
| 5 | * |
| 6 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il |
| 7 | * Based on code done by - Mark A. Greer <mgreer@mvista.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | */ |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/kdev_t.h> |
| 17 | #include <linux/console.h> |
| 18 | #include <linux/initrd.h> |
| 19 | #include <linux/root_dev.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/seq_file.h> |
| 22 | #include <linux/bootmem.h> |
| 23 | #include <linux/mtd/physmap.h> |
| 24 | #include <linux/mv643xx.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 26 | #include <asm/page.h> |
| 27 | #include <asm/time.h> |
| 28 | #include <asm/smp.h> |
| 29 | #include <asm/todc.h> |
| 30 | #include <asm/bootinfo.h> |
| 31 | #include <asm/ppcboot.h> |
| 32 | #include <asm/mv64x60.h> |
Paul Mackerras | fd582ec | 2005-10-11 22:08:12 +1000 | [diff] [blame] | 33 | #include <asm/machdep.h> |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 34 | #include <platforms/ev64360.h> |
| 35 | |
| 36 | #define BOARD_VENDOR "Marvell" |
| 37 | #define BOARD_MACHINE "EV-64360-BP" |
| 38 | |
| 39 | static struct mv64x60_handle bh; |
| 40 | static void __iomem *sram_base; |
| 41 | |
| 42 | static u32 ev64360_flash_size_0; |
| 43 | static u32 ev64360_flash_size_1; |
| 44 | |
| 45 | static u32 ev64360_bus_frequency; |
| 46 | |
| 47 | unsigned char __res[sizeof(bd_t)]; |
| 48 | |
Lee Nicks | 2104da9 | 2005-11-07 00:58:10 -0800 | [diff] [blame] | 49 | TODC_ALLOC(); |
| 50 | |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 51 | static int __init |
| 52 | ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 53 | { |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | static void __init |
| 58 | ev64360_setup_bridge(void) |
| 59 | { |
| 60 | struct mv64x60_setup_info si; |
| 61 | int i; |
| 62 | |
| 63 | memset(&si, 0, sizeof(si)); |
| 64 | |
| 65 | si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; |
| 66 | |
| 67 | #ifdef CONFIG_PCI |
| 68 | si.pci_1.enable_bus = 1; |
| 69 | si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR; |
| 70 | si.pci_1.pci_io.pci_base_hi = 0; |
| 71 | si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR; |
| 72 | si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE; |
| 73 | si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; |
| 74 | si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR; |
| 75 | si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR; |
| 76 | si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR; |
| 77 | si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE; |
| 78 | si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; |
| 79 | si.pci_1.pci_cmd_bits = 0; |
| 80 | si.pci_1.latency_timer = 0x80; |
| 81 | #else |
| 82 | si.pci_0.enable_bus = 0; |
| 83 | si.pci_1.enable_bus = 0; |
| 84 | #endif |
| 85 | |
| 86 | for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { |
| 87 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
| 88 | si.cpu_prot_options[i] = 0; |
| 89 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; |
| 90 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; |
| 91 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; |
| 92 | |
| 93 | si.pci_1.acc_cntl_options[i] = |
| 94 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | |
| 95 | MV64360_PCI_ACC_CNTL_SWAP_NONE | |
| 96 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | |
| 97 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; |
| 98 | #else |
| 99 | si.cpu_prot_options[i] = 0; |
| 100 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ |
| 101 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ |
| 102 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ |
| 103 | |
| 104 | si.pci_1.acc_cntl_options[i] = |
| 105 | MV64360_PCI_ACC_CNTL_SNOOP_WB | |
| 106 | MV64360_PCI_ACC_CNTL_SWAP_NONE | |
| 107 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | |
| 108 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; |
| 109 | #endif |
| 110 | } |
| 111 | |
| 112 | if (mv64x60_init(&bh, &si)) |
| 113 | printk(KERN_WARNING "Bridge initialization failed.\n"); |
| 114 | |
| 115 | #ifdef CONFIG_PCI |
| 116 | pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ |
| 117 | ppc_md.pci_swizzle = common_swizzle; |
| 118 | ppc_md.pci_map_irq = ev64360_map_irq; |
| 119 | ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; |
| 120 | |
| 121 | mv64x60_set_bus(&bh, 1, 0); |
| 122 | bh.hose_b->first_busno = 0; |
| 123 | bh.hose_b->last_busno = 0xff; |
| 124 | #endif |
| 125 | } |
| 126 | |
| 127 | /* Bridge & platform setup routines */ |
| 128 | void __init |
| 129 | ev64360_intr_setup(void) |
| 130 | { |
| 131 | /* MPP 8, 9, and 10 */ |
| 132 | mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); |
| 133 | |
| 134 | /* |
| 135 | * Define GPP 8,9,and 10 interrupt polarity as active low |
| 136 | * input signal and level triggered |
| 137 | */ |
| 138 | mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700); |
| 139 | mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700); |
| 140 | |
| 141 | /* Config GPP intr ctlr to respond to level trigger */ |
| 142 | mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); |
| 143 | |
| 144 | /* Erranum FEr PCI-#8 */ |
| 145 | mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); |
| 146 | mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); |
| 147 | |
| 148 | /* |
| 149 | * Dismiss and then enable interrupt on GPP interrupt cause |
| 150 | * for CPU #0 |
| 151 | */ |
| 152 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700); |
| 153 | mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700); |
| 154 | |
| 155 | /* |
| 156 | * Dismiss and then enable interrupt on CPU #0 high cause reg |
| 157 | * BIT25 summarizes GPP interrupts 8-15 |
| 158 | */ |
| 159 | mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25)); |
| 160 | } |
| 161 | |
| 162 | void __init |
| 163 | ev64360_setup_peripherals(void) |
| 164 | { |
| 165 | u32 base; |
| 166 | |
| 167 | /* Set up window for boot CS */ |
| 168 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, |
| 169 | EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0); |
| 170 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); |
| 171 | |
| 172 | /* We only use the 32-bit flash */ |
| 173 | mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base, |
| 174 | &ev64360_flash_size_0); |
| 175 | ev64360_flash_size_1 = 0; |
| 176 | |
| 177 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, |
| 178 | EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); |
| 179 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); |
| 180 | |
Lee Nicks | 2104da9 | 2005-11-07 00:58:10 -0800 | [diff] [blame] | 181 | TODC_INIT(TODC_TYPE_DS1501, 0, 0, |
| 182 | ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8); |
| 183 | |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 184 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, |
| 185 | EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); |
| 186 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); |
| 187 | sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); |
| 188 | |
| 189 | /* Set up Enet->SRAM window */ |
| 190 | mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, |
| 191 | EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); |
| 192 | bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); |
| 193 | |
| 194 | /* Give enet r/w access to memory region */ |
| 195 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); |
| 196 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); |
| 197 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); |
| 198 | |
| 199 | mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); |
| 200 | mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, |
| 201 | ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); |
| 202 | |
| 203 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
| 204 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); |
| 205 | #else |
| 206 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); |
| 207 | #endif |
| 208 | |
| 209 | /* |
| 210 | * Setting the SRAM to 0. Note that this generates parity errors on |
| 211 | * internal data path in SRAM since it's first time accessing it |
| 212 | * while after reset it's not configured. |
| 213 | */ |
| 214 | memset(sram_base, 0, MV64360_SRAM_SIZE); |
| 215 | |
| 216 | /* set up PCI interrupt controller */ |
| 217 | ev64360_intr_setup(); |
| 218 | } |
| 219 | |
| 220 | static void __init |
| 221 | ev64360_setup_arch(void) |
| 222 | { |
| 223 | if (ppc_md.progress) |
| 224 | ppc_md.progress("ev64360_setup_arch: enter", 0); |
| 225 | |
| 226 | set_tb(0, 0); |
| 227 | |
| 228 | #ifdef CONFIG_BLK_DEV_INITRD |
| 229 | if (initrd_start) |
| 230 | ROOT_DEV = Root_RAM0; |
| 231 | else |
| 232 | #endif |
| 233 | #ifdef CONFIG_ROOT_NFS |
| 234 | ROOT_DEV = Root_NFS; |
| 235 | #else |
| 236 | ROOT_DEV = Root_SDA2; |
| 237 | #endif |
| 238 | |
| 239 | /* |
| 240 | * Set up the L2CR register. |
| 241 | */ |
| 242 | _set_L2CR(L2CR_L2E | L2CR_L2PE); |
| 243 | |
| 244 | if (ppc_md.progress) |
| 245 | ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0); |
| 246 | |
| 247 | ev64360_setup_bridge(); |
| 248 | ev64360_setup_peripherals(); |
| 249 | ev64360_bus_frequency = ev64360_bus_freq(); |
| 250 | |
| 251 | printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks " |
| 252 | "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE); |
| 253 | if (ppc_md.progress) |
| 254 | ppc_md.progress("ev64360_setup_arch: exit", 0); |
| 255 | } |
| 256 | |
| 257 | /* Platform device data fixup routines. */ |
| 258 | #if defined(CONFIG_SERIAL_MPSC) |
| 259 | static void __init |
| 260 | ev64360_fixup_mpsc_pdata(struct platform_device *pdev) |
| 261 | { |
| 262 | struct mpsc_pdata *pdata; |
| 263 | |
| 264 | pdata = (struct mpsc_pdata *)pdev->dev.platform_data; |
| 265 | |
| 266 | pdata->max_idle = 40; |
| 267 | pdata->default_baud = EV64360_DEFAULT_BAUD; |
| 268 | pdata->brg_clk_src = EV64360_MPSC_CLK_SRC; |
| 269 | /* |
| 270 | * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, |
| 271 | * TCLK == SysCLK but on 64460, they are separate pins. |
| 272 | * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz. |
| 273 | */ |
| 274 | pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX); |
| 275 | } |
| 276 | #endif |
| 277 | |
| 278 | #if defined(CONFIG_MV643XX_ETH) |
| 279 | static void __init |
| 280 | ev64360_fixup_eth_pdata(struct platform_device *pdev) |
| 281 | { |
| 282 | struct mv643xx_eth_platform_data *eth_pd; |
| 283 | static u16 phy_addr[] = { |
| 284 | EV64360_ETH0_PHY_ADDR, |
| 285 | EV64360_ETH1_PHY_ADDR, |
| 286 | EV64360_ETH2_PHY_ADDR, |
| 287 | }; |
| 288 | |
| 289 | eth_pd = pdev->dev.platform_data; |
| 290 | eth_pd->force_phy_addr = 1; |
| 291 | eth_pd->phy_addr = phy_addr[pdev->id]; |
| 292 | eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE; |
| 293 | eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE; |
| 294 | } |
| 295 | #endif |
| 296 | |
Adrian Cox | bbbe121 | 2006-03-08 22:10:20 +0000 | [diff] [blame] | 297 | static int |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 298 | ev64360_platform_notify(struct device *dev) |
| 299 | { |
| 300 | static struct { |
| 301 | char *bus_id; |
| 302 | void ((*rtn)(struct platform_device *pdev)); |
| 303 | } dev_map[] = { |
| 304 | #if defined(CONFIG_SERIAL_MPSC) |
| 305 | { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata }, |
| 306 | { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata }, |
| 307 | #endif |
| 308 | #if defined(CONFIG_MV643XX_ETH) |
| 309 | { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata }, |
| 310 | { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata }, |
| 311 | { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata }, |
| 312 | #endif |
| 313 | }; |
| 314 | struct platform_device *pdev; |
| 315 | int i; |
| 316 | |
| 317 | if (dev && dev->bus_id) |
| 318 | for (i=0; i<ARRAY_SIZE(dev_map); i++) |
| 319 | if (!strncmp(dev->bus_id, dev_map[i].bus_id, |
| 320 | BUS_ID_SIZE)) { |
| 321 | |
| 322 | pdev = container_of(dev, |
| 323 | struct platform_device, dev); |
| 324 | dev_map[i].rtn(pdev); |
| 325 | } |
| 326 | |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | #ifdef CONFIG_MTD_PHYSMAP |
| 331 | |
| 332 | #ifndef MB |
| 333 | #define MB (1 << 20) |
| 334 | #endif |
| 335 | |
| 336 | /* |
| 337 | * MTD Layout. |
| 338 | * |
| 339 | * FLASH Amount: 0xff000000 - 0xffffffff |
| 340 | * ------------- ----------------------- |
| 341 | * Reserved: 0xff000000 - 0xff03ffff |
| 342 | * JFFS2 file system: 0xff040000 - 0xffefffff |
| 343 | * U-boot: 0xfff00000 - 0xffffffff |
| 344 | */ |
| 345 | static int __init |
| 346 | ev64360_setup_mtd(void) |
| 347 | { |
| 348 | u32 size; |
| 349 | int ptbl_entries; |
| 350 | static struct mtd_partition *ptbl; |
| 351 | |
| 352 | size = ev64360_flash_size_0 + ev64360_flash_size_1; |
| 353 | if (!size) |
| 354 | return -ENOMEM; |
| 355 | |
| 356 | ptbl_entries = 3; |
| 357 | |
Burman Yan | 95b93a0 | 2006-11-15 21:10:29 +0200 | [diff] [blame] | 358 | if ((ptbl = kzalloc(ptbl_entries * sizeof(struct mtd_partition), |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 359 | GFP_KERNEL)) == NULL) { |
| 360 | |
| 361 | printk(KERN_WARNING "Can't alloc MTD partition table\n"); |
| 362 | return -ENOMEM; |
| 363 | } |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 364 | |
| 365 | ptbl[0].name = "reserved"; |
| 366 | ptbl[0].offset = 0; |
| 367 | ptbl[0].size = EV64360_MTD_RESERVED_SIZE; |
| 368 | ptbl[1].name = "jffs2"; |
| 369 | ptbl[1].offset = EV64360_MTD_RESERVED_SIZE; |
| 370 | ptbl[1].size = EV64360_MTD_JFFS2_SIZE; |
| 371 | ptbl[2].name = "U-BOOT"; |
| 372 | ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE; |
| 373 | ptbl[2].size = EV64360_MTD_UBOOT_SIZE; |
| 374 | |
| 375 | physmap_map.size = size; |
| 376 | physmap_set_partitions(ptbl, ptbl_entries); |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | arch_initcall(ev64360_setup_mtd); |
| 381 | #endif |
| 382 | |
| 383 | static void |
| 384 | ev64360_restart(char *cmd) |
| 385 | { |
| 386 | ulong i = 0xffffffff; |
| 387 | volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000); |
| 388 | |
| 389 | /* issue hard reset */ |
| 390 | rtc_base[0xf] = 0x80; |
| 391 | rtc_base[0xc] = 0x00; |
| 392 | rtc_base[0xd] = 0x01; |
| 393 | rtc_base[0xf] = 0x83; |
| 394 | |
| 395 | while (i-- > 0) ; |
| 396 | panic("restart failed\n"); |
| 397 | } |
| 398 | |
| 399 | static void |
| 400 | ev64360_halt(void) |
| 401 | { |
| 402 | while (1) ; |
| 403 | /* NOTREACHED */ |
| 404 | } |
| 405 | |
| 406 | static void |
| 407 | ev64360_power_off(void) |
| 408 | { |
| 409 | ev64360_halt(); |
| 410 | /* NOTREACHED */ |
| 411 | } |
| 412 | |
| 413 | static int |
| 414 | ev64360_show_cpuinfo(struct seq_file *m) |
| 415 | { |
| 416 | seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); |
| 417 | seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); |
| 418 | seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000); |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | static void __init |
| 424 | ev64360_calibrate_decr(void) |
| 425 | { |
| 426 | u32 freq; |
| 427 | |
| 428 | freq = ev64360_bus_frequency / 4; |
| 429 | |
| 430 | printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", |
| 431 | (long)freq / 1000000, (long)freq % 1000000); |
| 432 | |
| 433 | tb_ticks_per_jiffy = freq / HZ; |
| 434 | tb_to_us = mulhwu_scale_factor(freq, 1000000); |
| 435 | } |
| 436 | |
| 437 | unsigned long __init |
| 438 | ev64360_find_end_of_memory(void) |
| 439 | { |
| 440 | return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, |
| 441 | MV64x60_TYPE_MV64360); |
| 442 | } |
| 443 | |
| 444 | static inline void |
| 445 | ev64360_set_bat(void) |
| 446 | { |
| 447 | mb(); |
| 448 | mtspr(SPRN_DBAT2U, 0xf0001ffe); |
| 449 | mtspr(SPRN_DBAT2L, 0xf000002a); |
| 450 | mb(); |
| 451 | } |
| 452 | |
| 453 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) |
| 454 | static void __init |
| 455 | ev64360_map_io(void) |
| 456 | { |
| 457 | io_block_mapping(CONFIG_MV64X60_NEW_BASE, \ |
| 458 | CONFIG_MV64X60_NEW_BASE, \ |
| 459 | 0x00020000, _PAGE_IO); |
| 460 | } |
| 461 | #endif |
| 462 | |
| 463 | void __init |
| 464 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 465 | unsigned long r6, unsigned long r7) |
| 466 | { |
| 467 | parse_bootinfo(find_bootinfo()); |
| 468 | |
| 469 | /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) |
| 470 | * are non-zero, then we should use the board info from the bd_t |
| 471 | * structure and the cmdline pointed to by r6 instead of the |
| 472 | * information from birecs, if any. Otherwise, use the information |
Simon Arlott | a8de5ce | 2007-05-12 05:42:54 +1000 | [diff] [blame] | 473 | * from birecs as discovered by the preceding call to |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 474 | * parse_bootinfo(). This rule should work with both PPCBoot, which |
| 475 | * uses a bd_t board info structure, and the kernel boot wrapper, |
| 476 | * which uses birecs. |
| 477 | */ |
| 478 | if (r3 && r6) { |
| 479 | /* copy board info structure */ |
| 480 | memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); |
| 481 | /* copy command line */ |
| 482 | *(char *)(r7+KERNELBASE) = 0; |
| 483 | strcpy(cmd_line, (char *)(r6+KERNELBASE)); |
| 484 | } |
| 485 | #ifdef CONFIG_ISA |
| 486 | isa_mem_base = 0; |
| 487 | #endif |
| 488 | |
| 489 | ppc_md.setup_arch = ev64360_setup_arch; |
| 490 | ppc_md.show_cpuinfo = ev64360_show_cpuinfo; |
| 491 | ppc_md.init_IRQ = mv64360_init_irq; |
| 492 | ppc_md.get_irq = mv64360_get_irq; |
| 493 | ppc_md.restart = ev64360_restart; |
| 494 | ppc_md.power_off = ev64360_power_off; |
| 495 | ppc_md.halt = ev64360_halt; |
| 496 | ppc_md.find_end_of_memory = ev64360_find_end_of_memory; |
Lee Nicks | 2104da9 | 2005-11-07 00:58:10 -0800 | [diff] [blame] | 497 | ppc_md.init = NULL; |
| 498 | |
| 499 | ppc_md.time_init = todc_time_init; |
| 500 | ppc_md.set_rtc_time = todc_set_rtc_time; |
| 501 | ppc_md.get_rtc_time = todc_get_rtc_time; |
| 502 | ppc_md.nvram_read_val = todc_direct_read_val; |
| 503 | ppc_md.nvram_write_val = todc_direct_write_val; |
Lee Nicks | 3acb234 | 2005-09-03 15:55:48 -0700 | [diff] [blame] | 504 | ppc_md.calibrate_decr = ev64360_calibrate_decr; |
| 505 | |
| 506 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) |
| 507 | ppc_md.setup_io_mappings = ev64360_map_io; |
| 508 | ppc_md.progress = mv64x60_mpsc_progress; |
| 509 | mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); |
| 510 | #endif |
| 511 | |
| 512 | #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) |
| 513 | platform_notify = ev64360_platform_notify; |
| 514 | #endif |
| 515 | |
| 516 | ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */ |
| 517 | } |