Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/cpu.h> |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame^] | 19 | #include <linux/cpu_pm.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_address.h> |
| 24 | #include <linux/of_irq.h> |
| 25 | #include <linux/percpu.h> |
| 26 | #include <linux/slab.h> |
| 27 | |
| 28 | #include <linux/irqchip/arm-gic-v3.h> |
| 29 | |
| 30 | #include <asm/cputype.h> |
| 31 | #include <asm/exception.h> |
| 32 | #include <asm/smp_plat.h> |
| 33 | |
| 34 | #include "irq-gic-common.h" |
| 35 | #include "irqchip.h" |
| 36 | |
| 37 | struct gic_chip_data { |
| 38 | void __iomem *dist_base; |
| 39 | void __iomem **redist_base; |
| 40 | void __percpu __iomem **rdist; |
| 41 | struct irq_domain *domain; |
| 42 | u64 redist_stride; |
| 43 | u32 redist_regions; |
| 44 | unsigned int irq_nr; |
| 45 | }; |
| 46 | |
| 47 | static struct gic_chip_data gic_data __read_mostly; |
| 48 | |
| 49 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdist)) |
| 50 | #define gic_data_rdist_rd_base() (*gic_data_rdist()) |
| 51 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
| 52 | |
| 53 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ |
| 54 | #define DEFAULT_PMR_VALUE 0xf0 |
| 55 | |
| 56 | static inline unsigned int gic_irq(struct irq_data *d) |
| 57 | { |
| 58 | return d->hwirq; |
| 59 | } |
| 60 | |
| 61 | static inline int gic_irq_in_rdist(struct irq_data *d) |
| 62 | { |
| 63 | return gic_irq(d) < 32; |
| 64 | } |
| 65 | |
| 66 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
| 67 | { |
| 68 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ |
| 69 | return gic_data_rdist_sgi_base(); |
| 70 | |
| 71 | if (d->hwirq <= 1023) /* SPI -> dist_base */ |
| 72 | return gic_data.dist_base; |
| 73 | |
| 74 | if (d->hwirq >= 8192) |
| 75 | BUG(); /* LPI Detected!!! */ |
| 76 | |
| 77 | return NULL; |
| 78 | } |
| 79 | |
| 80 | static void gic_do_wait_for_rwp(void __iomem *base) |
| 81 | { |
| 82 | u32 count = 1000000; /* 1s! */ |
| 83 | |
| 84 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { |
| 85 | count--; |
| 86 | if (!count) { |
| 87 | pr_err_ratelimited("RWP timeout, gone fishing\n"); |
| 88 | return; |
| 89 | } |
| 90 | cpu_relax(); |
| 91 | udelay(1); |
| 92 | }; |
| 93 | } |
| 94 | |
| 95 | /* Wait for completion of a distributor change */ |
| 96 | static void gic_dist_wait_for_rwp(void) |
| 97 | { |
| 98 | gic_do_wait_for_rwp(gic_data.dist_base); |
| 99 | } |
| 100 | |
| 101 | /* Wait for completion of a redistributor change */ |
| 102 | static void gic_redist_wait_for_rwp(void) |
| 103 | { |
| 104 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); |
| 105 | } |
| 106 | |
| 107 | /* Low level accessors */ |
| 108 | static u64 gic_read_iar(void) |
| 109 | { |
| 110 | u64 irqstat; |
| 111 | |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 112 | asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 113 | return irqstat; |
| 114 | } |
| 115 | |
| 116 | static void gic_write_pmr(u64 val) |
| 117 | { |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 118 | asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | static void gic_write_ctlr(u64 val) |
| 122 | { |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 123 | asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 124 | isb(); |
| 125 | } |
| 126 | |
| 127 | static void gic_write_grpen1(u64 val) |
| 128 | { |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 129 | asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 130 | isb(); |
| 131 | } |
| 132 | |
| 133 | static void gic_write_sgi1r(u64 val) |
| 134 | { |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 135 | asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void gic_enable_sre(void) |
| 139 | { |
| 140 | u64 val; |
| 141 | |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 142 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 143 | val |= ICC_SRE_EL1_SRE; |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 144 | asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 145 | isb(); |
| 146 | |
| 147 | /* |
| 148 | * Need to check that the SRE bit has actually been set. If |
| 149 | * not, it means that SRE is disabled at EL2. We're going to |
| 150 | * die painfully, and there is nothing we can do about it. |
| 151 | * |
| 152 | * Kindly inform the luser. |
| 153 | */ |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 154 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 155 | if (!(val & ICC_SRE_EL1_SRE)) |
| 156 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); |
| 157 | } |
| 158 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 159 | static void gic_enable_redist(bool enable) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 160 | { |
| 161 | void __iomem *rbase; |
| 162 | u32 count = 1000000; /* 1s! */ |
| 163 | u32 val; |
| 164 | |
| 165 | rbase = gic_data_rdist_rd_base(); |
| 166 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 167 | val = readl_relaxed(rbase + GICR_WAKER); |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 168 | if (enable) |
| 169 | /* Wake up this CPU redistributor */ |
| 170 | val &= ~GICR_WAKER_ProcessorSleep; |
| 171 | else |
| 172 | val |= GICR_WAKER_ProcessorSleep; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 173 | writel_relaxed(val, rbase + GICR_WAKER); |
| 174 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 175 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
| 176 | val = readl_relaxed(rbase + GICR_WAKER); |
| 177 | if (!(val & GICR_WAKER_ProcessorSleep)) |
| 178 | return; /* No PM support in this redistributor */ |
| 179 | } |
| 180 | |
| 181 | while (count--) { |
| 182 | val = readl_relaxed(rbase + GICR_WAKER); |
| 183 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) |
| 184 | break; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 185 | cpu_relax(); |
| 186 | udelay(1); |
| 187 | }; |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 188 | if (!count) |
| 189 | pr_err_ratelimited("redistributor failed to %s...\n", |
| 190 | enable ? "wakeup" : "sleep"); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /* |
| 194 | * Routines to disable, enable, EOI and route interrupts |
| 195 | */ |
| 196 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
| 197 | { |
| 198 | u32 mask = 1 << (gic_irq(d) % 32); |
| 199 | void (*rwp_wait)(void); |
| 200 | void __iomem *base; |
| 201 | |
| 202 | if (gic_irq_in_rdist(d)) { |
| 203 | base = gic_data_rdist_sgi_base(); |
| 204 | rwp_wait = gic_redist_wait_for_rwp; |
| 205 | } else { |
| 206 | base = gic_data.dist_base; |
| 207 | rwp_wait = gic_dist_wait_for_rwp; |
| 208 | } |
| 209 | |
| 210 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); |
| 211 | rwp_wait(); |
| 212 | } |
| 213 | |
| 214 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 215 | { |
| 216 | u32 mask = 1 << (gic_irq(d) % 32); |
| 217 | void __iomem *base; |
| 218 | |
| 219 | if (gic_irq_in_rdist(d)) |
| 220 | base = gic_data_rdist_sgi_base(); |
| 221 | else |
| 222 | base = gic_data.dist_base; |
| 223 | |
| 224 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); |
| 225 | } |
| 226 | |
| 227 | static void gic_mask_irq(struct irq_data *d) |
| 228 | { |
| 229 | gic_poke_irq(d, GICD_ICENABLER); |
| 230 | } |
| 231 | |
| 232 | static void gic_unmask_irq(struct irq_data *d) |
| 233 | { |
| 234 | gic_poke_irq(d, GICD_ISENABLER); |
| 235 | } |
| 236 | |
| 237 | static void gic_eoi_irq(struct irq_data *d) |
| 238 | { |
| 239 | gic_write_eoir(gic_irq(d)); |
| 240 | } |
| 241 | |
| 242 | static int gic_set_type(struct irq_data *d, unsigned int type) |
| 243 | { |
| 244 | unsigned int irq = gic_irq(d); |
| 245 | void (*rwp_wait)(void); |
| 246 | void __iomem *base; |
| 247 | |
| 248 | /* Interrupt configuration for SGIs can't be changed */ |
| 249 | if (irq < 16) |
| 250 | return -EINVAL; |
| 251 | |
| 252 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
| 253 | return -EINVAL; |
| 254 | |
| 255 | if (gic_irq_in_rdist(d)) { |
| 256 | base = gic_data_rdist_sgi_base(); |
| 257 | rwp_wait = gic_redist_wait_for_rwp; |
| 258 | } else { |
| 259 | base = gic_data.dist_base; |
| 260 | rwp_wait = gic_dist_wait_for_rwp; |
| 261 | } |
| 262 | |
| 263 | gic_configure_irq(irq, type, base, rwp_wait); |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | static u64 gic_mpidr_to_affinity(u64 mpidr) |
| 269 | { |
| 270 | u64 aff; |
| 271 | |
| 272 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
| 273 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 274 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 275 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 276 | |
| 277 | return aff; |
| 278 | } |
| 279 | |
| 280 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
| 281 | { |
| 282 | u64 irqnr; |
| 283 | |
| 284 | do { |
| 285 | irqnr = gic_read_iar(); |
| 286 | |
| 287 | if (likely(irqnr > 15 && irqnr < 1020)) { |
| 288 | u64 irq = irq_find_mapping(gic_data.domain, irqnr); |
| 289 | if (likely(irq)) { |
| 290 | handle_IRQ(irq, regs); |
| 291 | continue; |
| 292 | } |
| 293 | |
| 294 | WARN_ONCE(true, "Unexpected SPI received!\n"); |
| 295 | gic_write_eoir(irqnr); |
| 296 | } |
| 297 | if (irqnr < 16) { |
| 298 | gic_write_eoir(irqnr); |
| 299 | #ifdef CONFIG_SMP |
| 300 | handle_IPI(irqnr, regs); |
| 301 | #else |
| 302 | WARN_ONCE(true, "Unexpected SGI received!\n"); |
| 303 | #endif |
| 304 | continue; |
| 305 | } |
| 306 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); |
| 307 | } |
| 308 | |
| 309 | static void __init gic_dist_init(void) |
| 310 | { |
| 311 | unsigned int i; |
| 312 | u64 affinity; |
| 313 | void __iomem *base = gic_data.dist_base; |
| 314 | |
| 315 | /* Disable the distributor */ |
| 316 | writel_relaxed(0, base + GICD_CTLR); |
| 317 | gic_dist_wait_for_rwp(); |
| 318 | |
| 319 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
| 320 | |
| 321 | /* Enable distributor with ARE, Group1 */ |
| 322 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, |
| 323 | base + GICD_CTLR); |
| 324 | |
| 325 | /* |
| 326 | * Set all global interrupts to the boot CPU only. ARE must be |
| 327 | * enabled. |
| 328 | */ |
| 329 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); |
| 330 | for (i = 32; i < gic_data.irq_nr; i++) |
| 331 | writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); |
| 332 | } |
| 333 | |
| 334 | static int gic_populate_rdist(void) |
| 335 | { |
| 336 | u64 mpidr = cpu_logical_map(smp_processor_id()); |
| 337 | u64 typer; |
| 338 | u32 aff; |
| 339 | int i; |
| 340 | |
| 341 | /* |
| 342 | * Convert affinity to a 32bit value that can be matched to |
| 343 | * GICR_TYPER bits [63:32]. |
| 344 | */ |
| 345 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | |
| 346 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 347 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 348 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 349 | |
| 350 | for (i = 0; i < gic_data.redist_regions; i++) { |
| 351 | void __iomem *ptr = gic_data.redist_base[i]; |
| 352 | u32 reg; |
| 353 | |
| 354 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 355 | if (reg != GIC_PIDR2_ARCH_GICv3 && |
| 356 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ |
| 357 | pr_warn("No redistributor present @%p\n", ptr); |
| 358 | break; |
| 359 | } |
| 360 | |
| 361 | do { |
| 362 | typer = readq_relaxed(ptr + GICR_TYPER); |
| 363 | if ((typer >> 32) == aff) { |
| 364 | gic_data_rdist_rd_base() = ptr; |
| 365 | pr_info("CPU%d: found redistributor %llx @%p\n", |
| 366 | smp_processor_id(), |
| 367 | (unsigned long long)mpidr, ptr); |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | if (gic_data.redist_stride) { |
| 372 | ptr += gic_data.redist_stride; |
| 373 | } else { |
| 374 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ |
| 375 | if (typer & GICR_TYPER_VLPIS) |
| 376 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ |
| 377 | } |
| 378 | } while (!(typer & GICR_TYPER_LAST)); |
| 379 | } |
| 380 | |
| 381 | /* We couldn't even deal with ourselves... */ |
| 382 | WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", |
| 383 | smp_processor_id(), (unsigned long long)mpidr); |
| 384 | return -ENODEV; |
| 385 | } |
| 386 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame^] | 387 | static void gic_cpu_sys_reg_init(void) |
| 388 | { |
| 389 | /* Enable system registers */ |
| 390 | gic_enable_sre(); |
| 391 | |
| 392 | /* Set priority mask register */ |
| 393 | gic_write_pmr(DEFAULT_PMR_VALUE); |
| 394 | |
| 395 | /* EOI deactivates interrupt too (mode 0) */ |
| 396 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); |
| 397 | |
| 398 | /* ... and let's hit the road... */ |
| 399 | gic_write_grpen1(1); |
| 400 | } |
| 401 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 402 | static void gic_cpu_init(void) |
| 403 | { |
| 404 | void __iomem *rbase; |
| 405 | |
| 406 | /* Register ourselves with the rest of the world */ |
| 407 | if (gic_populate_rdist()) |
| 408 | return; |
| 409 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 410 | gic_enable_redist(true); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 411 | |
| 412 | rbase = gic_data_rdist_sgi_base(); |
| 413 | |
| 414 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
| 415 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame^] | 416 | /* initialise system registers */ |
| 417 | gic_cpu_sys_reg_init(); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | #ifdef CONFIG_SMP |
| 421 | static int gic_secondary_init(struct notifier_block *nfb, |
| 422 | unsigned long action, void *hcpu) |
| 423 | { |
| 424 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
| 425 | gic_cpu_init(); |
| 426 | return NOTIFY_OK; |
| 427 | } |
| 428 | |
| 429 | /* |
| 430 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high |
| 431 | * priority because the GIC needs to be up before the ARM generic timers. |
| 432 | */ |
| 433 | static struct notifier_block gic_cpu_notifier = { |
| 434 | .notifier_call = gic_secondary_init, |
| 435 | .priority = 100, |
| 436 | }; |
| 437 | |
| 438 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
| 439 | u64 cluster_id) |
| 440 | { |
| 441 | int cpu = *base_cpu; |
| 442 | u64 mpidr = cpu_logical_map(cpu); |
| 443 | u16 tlist = 0; |
| 444 | |
| 445 | while (cpu < nr_cpu_ids) { |
| 446 | /* |
| 447 | * If we ever get a cluster of more than 16 CPUs, just |
| 448 | * scream and skip that CPU. |
| 449 | */ |
| 450 | if (WARN_ON((mpidr & 0xff) >= 16)) |
| 451 | goto out; |
| 452 | |
| 453 | tlist |= 1 << (mpidr & 0xf); |
| 454 | |
| 455 | cpu = cpumask_next(cpu, mask); |
| 456 | if (cpu == nr_cpu_ids) |
| 457 | goto out; |
| 458 | |
| 459 | mpidr = cpu_logical_map(cpu); |
| 460 | |
| 461 | if (cluster_id != (mpidr & ~0xffUL)) { |
| 462 | cpu--; |
| 463 | goto out; |
| 464 | } |
| 465 | } |
| 466 | out: |
| 467 | *base_cpu = cpu; |
| 468 | return tlist; |
| 469 | } |
| 470 | |
| 471 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
| 472 | { |
| 473 | u64 val; |
| 474 | |
| 475 | val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | |
| 476 | MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 | |
| 477 | irq << 24 | |
| 478 | MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 | |
| 479 | tlist); |
| 480 | |
| 481 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
| 482 | gic_write_sgi1r(val); |
| 483 | } |
| 484 | |
| 485 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
| 486 | { |
| 487 | int cpu; |
| 488 | |
| 489 | if (WARN_ON(irq >= 16)) |
| 490 | return; |
| 491 | |
| 492 | /* |
| 493 | * Ensure that stores to Normal memory are visible to the |
| 494 | * other CPUs before issuing the IPI. |
| 495 | */ |
| 496 | smp_wmb(); |
| 497 | |
| 498 | for_each_cpu_mask(cpu, *mask) { |
| 499 | u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
| 500 | u16 tlist; |
| 501 | |
| 502 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); |
| 503 | gic_send_sgi(cluster_id, tlist, irq); |
| 504 | } |
| 505 | |
| 506 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ |
| 507 | isb(); |
| 508 | } |
| 509 | |
| 510 | static void gic_smp_init(void) |
| 511 | { |
| 512 | set_smp_cross_call(gic_raise_softirq); |
| 513 | register_cpu_notifier(&gic_cpu_notifier); |
| 514 | } |
| 515 | |
| 516 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 517 | bool force) |
| 518 | { |
| 519 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 520 | void __iomem *reg; |
| 521 | int enabled; |
| 522 | u64 val; |
| 523 | |
| 524 | if (gic_irq_in_rdist(d)) |
| 525 | return -EINVAL; |
| 526 | |
| 527 | /* If interrupt was enabled, disable it first */ |
| 528 | enabled = gic_peek_irq(d, GICD_ISENABLER); |
| 529 | if (enabled) |
| 530 | gic_mask_irq(d); |
| 531 | |
| 532 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); |
| 533 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); |
| 534 | |
| 535 | writeq_relaxed(val, reg); |
| 536 | |
| 537 | /* |
| 538 | * If the interrupt was enabled, enabled it again. Otherwise, |
| 539 | * just wait for the distributor to have digested our changes. |
| 540 | */ |
| 541 | if (enabled) |
| 542 | gic_unmask_irq(d); |
| 543 | else |
| 544 | gic_dist_wait_for_rwp(); |
| 545 | |
| 546 | return IRQ_SET_MASK_OK; |
| 547 | } |
| 548 | #else |
| 549 | #define gic_set_affinity NULL |
| 550 | #define gic_smp_init() do { } while(0) |
| 551 | #endif |
| 552 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame^] | 553 | #ifdef CONFIG_CPU_PM |
| 554 | static int gic_cpu_pm_notifier(struct notifier_block *self, |
| 555 | unsigned long cmd, void *v) |
| 556 | { |
| 557 | if (cmd == CPU_PM_EXIT) { |
| 558 | gic_enable_redist(true); |
| 559 | gic_cpu_sys_reg_init(); |
| 560 | } else if (cmd == CPU_PM_ENTER) { |
| 561 | gic_write_grpen1(0); |
| 562 | gic_enable_redist(false); |
| 563 | } |
| 564 | return NOTIFY_OK; |
| 565 | } |
| 566 | |
| 567 | static struct notifier_block gic_cpu_pm_notifier_block = { |
| 568 | .notifier_call = gic_cpu_pm_notifier, |
| 569 | }; |
| 570 | |
| 571 | static void gic_cpu_pm_init(void) |
| 572 | { |
| 573 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); |
| 574 | } |
| 575 | |
| 576 | #else |
| 577 | static inline void gic_cpu_pm_init(void) { } |
| 578 | #endif /* CONFIG_CPU_PM */ |
| 579 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 580 | static struct irq_chip gic_chip = { |
| 581 | .name = "GICv3", |
| 582 | .irq_mask = gic_mask_irq, |
| 583 | .irq_unmask = gic_unmask_irq, |
| 584 | .irq_eoi = gic_eoi_irq, |
| 585 | .irq_set_type = gic_set_type, |
| 586 | .irq_set_affinity = gic_set_affinity, |
| 587 | }; |
| 588 | |
| 589 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 590 | irq_hw_number_t hw) |
| 591 | { |
| 592 | /* SGIs are private to the core kernel */ |
| 593 | if (hw < 16) |
| 594 | return -EPERM; |
| 595 | /* PPIs */ |
| 596 | if (hw < 32) { |
| 597 | irq_set_percpu_devid(irq); |
| 598 | irq_set_chip_and_handler(irq, &gic_chip, |
| 599 | handle_percpu_devid_irq); |
| 600 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
| 601 | } |
| 602 | /* SPIs */ |
| 603 | if (hw >= 32 && hw < gic_data.irq_nr) { |
| 604 | irq_set_chip_and_handler(irq, &gic_chip, |
| 605 | handle_fasteoi_irq); |
| 606 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 607 | } |
| 608 | irq_set_chip_data(irq, d->host_data); |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | static int gic_irq_domain_xlate(struct irq_domain *d, |
| 613 | struct device_node *controller, |
| 614 | const u32 *intspec, unsigned int intsize, |
| 615 | unsigned long *out_hwirq, unsigned int *out_type) |
| 616 | { |
| 617 | if (d->of_node != controller) |
| 618 | return -EINVAL; |
| 619 | if (intsize < 3) |
| 620 | return -EINVAL; |
| 621 | |
| 622 | switch(intspec[0]) { |
| 623 | case 0: /* SPI */ |
| 624 | *out_hwirq = intspec[1] + 32; |
| 625 | break; |
| 626 | case 1: /* PPI */ |
| 627 | *out_hwirq = intspec[1] + 16; |
| 628 | break; |
| 629 | default: |
| 630 | return -EINVAL; |
| 631 | } |
| 632 | |
| 633 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | static const struct irq_domain_ops gic_irq_domain_ops = { |
| 638 | .map = gic_irq_domain_map, |
| 639 | .xlate = gic_irq_domain_xlate, |
| 640 | }; |
| 641 | |
| 642 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
| 643 | { |
| 644 | void __iomem *dist_base; |
| 645 | void __iomem **redist_base; |
| 646 | u64 redist_stride; |
| 647 | u32 redist_regions; |
| 648 | u32 reg; |
| 649 | int gic_irqs; |
| 650 | int err; |
| 651 | int i; |
| 652 | |
| 653 | dist_base = of_iomap(node, 0); |
| 654 | if (!dist_base) { |
| 655 | pr_err("%s: unable to map gic dist registers\n", |
| 656 | node->full_name); |
| 657 | return -ENXIO; |
| 658 | } |
| 659 | |
| 660 | reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 661 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { |
| 662 | pr_err("%s: no distributor detected, giving up\n", |
| 663 | node->full_name); |
| 664 | err = -ENODEV; |
| 665 | goto out_unmap_dist; |
| 666 | } |
| 667 | |
| 668 | if (of_property_read_u32(node, "#redistributor-regions", &redist_regions)) |
| 669 | redist_regions = 1; |
| 670 | |
| 671 | redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL); |
| 672 | if (!redist_base) { |
| 673 | err = -ENOMEM; |
| 674 | goto out_unmap_dist; |
| 675 | } |
| 676 | |
| 677 | for (i = 0; i < redist_regions; i++) { |
| 678 | redist_base[i] = of_iomap(node, 1 + i); |
| 679 | if (!redist_base[i]) { |
| 680 | pr_err("%s: couldn't map region %d\n", |
| 681 | node->full_name, i); |
| 682 | err = -ENODEV; |
| 683 | goto out_unmap_rdist; |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) |
| 688 | redist_stride = 0; |
| 689 | |
| 690 | gic_data.dist_base = dist_base; |
| 691 | gic_data.redist_base = redist_base; |
| 692 | gic_data.redist_regions = redist_regions; |
| 693 | gic_data.redist_stride = redist_stride; |
| 694 | |
| 695 | /* |
| 696 | * Find out how many interrupts are supported. |
| 697 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) |
| 698 | */ |
| 699 | gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f; |
| 700 | gic_irqs = (gic_irqs + 1) * 32; |
| 701 | if (gic_irqs > 1020) |
| 702 | gic_irqs = 1020; |
| 703 | gic_data.irq_nr = gic_irqs; |
| 704 | |
| 705 | gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, |
| 706 | &gic_data); |
| 707 | gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist)); |
| 708 | |
| 709 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) { |
| 710 | err = -ENOMEM; |
| 711 | goto out_free; |
| 712 | } |
| 713 | |
| 714 | set_handle_irq(gic_handle_irq); |
| 715 | |
| 716 | gic_smp_init(); |
| 717 | gic_dist_init(); |
| 718 | gic_cpu_init(); |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame^] | 719 | gic_cpu_pm_init(); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 720 | |
| 721 | return 0; |
| 722 | |
| 723 | out_free: |
| 724 | if (gic_data.domain) |
| 725 | irq_domain_remove(gic_data.domain); |
| 726 | free_percpu(gic_data.rdist); |
| 727 | out_unmap_rdist: |
| 728 | for (i = 0; i < redist_regions; i++) |
| 729 | if (redist_base[i]) |
| 730 | iounmap(redist_base[i]); |
| 731 | kfree(redist_base); |
| 732 | out_unmap_dist: |
| 733 | iounmap(dist_base); |
| 734 | return err; |
| 735 | } |
| 736 | |
| 737 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |